1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include <linux/module.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/slab.h>
30#include <linux/string.h>
31#include <linux/timer.h>
32#include <linux/ioport.h>
33#include <linux/major.h>
34#include <linux/blkdev.h>
35#include <linux/interrupt.h>
36#include <linux/pci.h>
37#include <linux/delay.h>
38#include <linux/ctype.h>
39#include <linux/dma-mapping.h>
40
41#include <asm/dma.h>
42#include <asm/system.h>
43#include <asm/io.h>
44
45#include <scsi/scsi.h>
46#include <scsi/scsi_cmnd.h>
47#include <scsi/scsi_device.h>
48#include <scsi/scsi_host.h>
49#include <scsi/scsi_ioctl.h>
50
51#include "nsp32.h"
52
53
54
55
56
57static int trans_mode = 0;
58module_param (trans_mode, int, 0);
59MODULE_PARM_DESC(trans_mode, "transfer mode (0: BIOS(default) 1: Async 2: Ultra20M");
60#define ASYNC_MODE 1
61#define ULTRA20M_MODE 2
62
63static int auto_param = 0;
64module_param (auto_param, bool, 0);
65MODULE_PARM_DESC(auto_param, "AutoParameter mode (0: ON(default) 1: OFF)");
66
67static int disc_priv = 1;
68module_param (disc_priv, bool, 0);
69MODULE_PARM_DESC(disc_priv, "disconnection privilege mode (0: ON 1: OFF(default))");
70
71MODULE_AUTHOR("YOKOTA Hiroshi <yokota@netlab.is.tsukuba.ac.jp>, GOTO Masanori <gotom@debian.or.jp>");
72MODULE_DESCRIPTION("Workbit NinjaSCSI-32Bi/UDE CardBus/PCI SCSI host bus adapter module");
73MODULE_LICENSE("GPL");
74
75static const char *nsp32_release_version = "1.2";
76
77
78
79
80
81static struct pci_device_id nsp32_pci_table[] __devinitdata = {
82 {
83 .vendor = PCI_VENDOR_ID_IODATA,
84 .device = PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II,
85 .subvendor = PCI_ANY_ID,
86 .subdevice = PCI_ANY_ID,
87 .driver_data = MODEL_IODATA,
88 },
89 {
90 .vendor = PCI_VENDOR_ID_WORKBIT,
91 .device = PCI_DEVICE_ID_NINJASCSI_32BI_KME,
92 .subvendor = PCI_ANY_ID,
93 .subdevice = PCI_ANY_ID,
94 .driver_data = MODEL_KME,
95 },
96 {
97 .vendor = PCI_VENDOR_ID_WORKBIT,
98 .device = PCI_DEVICE_ID_NINJASCSI_32BI_WBT,
99 .subvendor = PCI_ANY_ID,
100 .subdevice = PCI_ANY_ID,
101 .driver_data = MODEL_WORKBIT,
102 },
103 {
104 .vendor = PCI_VENDOR_ID_WORKBIT,
105 .device = PCI_DEVICE_ID_WORKBIT_STANDARD,
106 .subvendor = PCI_ANY_ID,
107 .subdevice = PCI_ANY_ID,
108 .driver_data = MODEL_PCI_WORKBIT,
109 },
110 {
111 .vendor = PCI_VENDOR_ID_WORKBIT,
112 .device = PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC,
113 .subvendor = PCI_ANY_ID,
114 .subdevice = PCI_ANY_ID,
115 .driver_data = MODEL_LOGITEC,
116 },
117 {
118 .vendor = PCI_VENDOR_ID_WORKBIT,
119 .device = PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC,
120 .subvendor = PCI_ANY_ID,
121 .subdevice = PCI_ANY_ID,
122 .driver_data = MODEL_PCI_LOGITEC,
123 },
124 {
125 .vendor = PCI_VENDOR_ID_WORKBIT,
126 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO,
127 .subvendor = PCI_ANY_ID,
128 .subdevice = PCI_ANY_ID,
129 .driver_data = MODEL_PCI_MELCO,
130 },
131 {
132 .vendor = PCI_VENDOR_ID_WORKBIT,
133 .device = PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II,
134 .subvendor = PCI_ANY_ID,
135 .subdevice = PCI_ANY_ID,
136 .driver_data = MODEL_PCI_MELCO,
137 },
138 {0,0,},
139};
140MODULE_DEVICE_TABLE(pci, nsp32_pci_table);
141
142static nsp32_hw_data nsp32_data_base;
143
144
145
146
147
148
149
150static nsp32_sync_table nsp32_sync_table_40M[] = {
151
152 {0x1, 0, 0x0c, 0x0c, SMPL_40M},
153 {0x2, 0, 0x0d, 0x18, SMPL_40M},
154 {0x3, 1, 0x19, 0x19, SMPL_40M},
155 {0x4, 1, 0x1a, 0x1f, SMPL_20M},
156 {0x5, 2, 0x20, 0x25, SMPL_20M},
157 {0x6, 2, 0x26, 0x31, SMPL_20M},
158 {0x7, 3, 0x32, 0x32, SMPL_20M},
159 {0x8, 3, 0x33, 0x38, SMPL_10M},
160 {0x9, 3, 0x39, 0x3e, SMPL_10M},
161};
162
163static nsp32_sync_table nsp32_sync_table_20M[] = {
164 {0x1, 0, 0x19, 0x19, SMPL_40M},
165 {0x2, 0, 0x1a, 0x25, SMPL_20M},
166 {0x3, 1, 0x26, 0x32, SMPL_20M},
167 {0x4, 1, 0x33, 0x3e, SMPL_10M},
168 {0x5, 2, 0x3f, 0x4b, SMPL_10M},
169 {0x6, 2, 0x4c, 0x57, SMPL_10M},
170 {0x7, 3, 0x58, 0x64, SMPL_10M},
171 {0x8, 3, 0x65, 0x70, SMPL_10M},
172 {0x9, 3, 0x71, 0x7d, SMPL_10M},
173};
174
175static nsp32_sync_table nsp32_sync_table_pci[] = {
176 {0x1, 0, 0x0c, 0x0f, SMPL_40M},
177 {0x2, 0, 0x10, 0x16, SMPL_40M},
178 {0x3, 1, 0x17, 0x1e, SMPL_20M},
179 {0x4, 1, 0x1f, 0x25, SMPL_20M},
180 {0x5, 2, 0x26, 0x2d, SMPL_20M},
181 {0x6, 2, 0x2e, 0x34, SMPL_10M},
182 {0x7, 3, 0x35, 0x3c, SMPL_10M},
183 {0x8, 3, 0x3d, 0x43, SMPL_10M},
184 {0x9, 3, 0x44, 0x4b, SMPL_10M},
185};
186
187
188
189
190
191static int __devinit nsp32_probe (struct pci_dev *, const struct pci_device_id *);
192static void __devexit nsp32_remove(struct pci_dev *);
193static int __init init_nsp32 (void);
194static void __exit exit_nsp32 (void);
195
196
197static int nsp32_proc_info (struct Scsi_Host *, char *, char **, off_t, int, int);
198
199static int nsp32_detect (struct pci_dev *pdev);
200static int nsp32_queuecommand(struct scsi_cmnd *,
201 void (*done)(struct scsi_cmnd *));
202static const char *nsp32_info (struct Scsi_Host *);
203static int nsp32_release (struct Scsi_Host *);
204
205
206static int nsp32_eh_abort (struct scsi_cmnd *);
207static int nsp32_eh_bus_reset (struct scsi_cmnd *);
208static int nsp32_eh_host_reset(struct scsi_cmnd *);
209
210
211static void nsp32_build_identify(struct scsi_cmnd *);
212static void nsp32_build_nop (struct scsi_cmnd *);
213static void nsp32_build_reject (struct scsi_cmnd *);
214static void nsp32_build_sdtr (struct scsi_cmnd *, unsigned char, unsigned char);
215
216
217static int nsp32_busfree_occur(struct scsi_cmnd *, unsigned short);
218static void nsp32_msgout_occur (struct scsi_cmnd *);
219static void nsp32_msgin_occur (struct scsi_cmnd *, unsigned long, unsigned short);
220
221static int nsp32_setup_sg_table (struct scsi_cmnd *);
222static int nsp32_selection_autopara(struct scsi_cmnd *);
223static int nsp32_selection_autoscsi(struct scsi_cmnd *);
224static void nsp32_scsi_done (struct scsi_cmnd *);
225static int nsp32_arbitration (struct scsi_cmnd *, unsigned int);
226static int nsp32_reselection (struct scsi_cmnd *, unsigned char);
227static void nsp32_adjust_busfree (struct scsi_cmnd *, unsigned int);
228static void nsp32_restart_autoscsi (struct scsi_cmnd *, unsigned short);
229
230
231static void nsp32_analyze_sdtr (struct scsi_cmnd *);
232static int nsp32_search_period_entry(nsp32_hw_data *, nsp32_target *, unsigned char);
233static void nsp32_set_async (nsp32_hw_data *, nsp32_target *);
234static void nsp32_set_max_sync (nsp32_hw_data *, nsp32_target *, unsigned char *, unsigned char *);
235static void nsp32_set_sync_entry (nsp32_hw_data *, nsp32_target *, int, unsigned char);
236
237
238static void nsp32_wait_req (nsp32_hw_data *, int);
239static void nsp32_wait_sack (nsp32_hw_data *, int);
240static void nsp32_sack_assert (nsp32_hw_data *);
241static void nsp32_sack_negate (nsp32_hw_data *);
242static void nsp32_do_bus_reset(nsp32_hw_data *);
243
244
245static irqreturn_t do_nsp32_isr(int, void *);
246
247
248static int nsp32hw_init(nsp32_hw_data *);
249
250
251static int nsp32_getprom_param (nsp32_hw_data *);
252static int nsp32_getprom_at24 (nsp32_hw_data *);
253static int nsp32_getprom_c16 (nsp32_hw_data *);
254static void nsp32_prom_start (nsp32_hw_data *);
255static void nsp32_prom_stop (nsp32_hw_data *);
256static int nsp32_prom_read (nsp32_hw_data *, int);
257static int nsp32_prom_read_bit (nsp32_hw_data *);
258static void nsp32_prom_write_bit(nsp32_hw_data *, int);
259static void nsp32_prom_set (nsp32_hw_data *, int, int);
260static int nsp32_prom_get (nsp32_hw_data *, int);
261
262
263static void nsp32_message (const char *, int, char *, char *, ...);
264#ifdef NSP32_DEBUG
265static void nsp32_dmessage(const char *, int, int, char *, ...);
266#endif
267
268
269
270
271static struct scsi_host_template nsp32_template = {
272 .proc_name = "nsp32",
273 .name = "Workbit NinjaSCSI-32Bi/UDE",
274 .proc_info = nsp32_proc_info,
275 .info = nsp32_info,
276 .queuecommand = nsp32_queuecommand,
277 .can_queue = 1,
278 .sg_tablesize = NSP32_SG_SIZE,
279 .max_sectors = 128,
280 .cmd_per_lun = 1,
281 .this_id = NSP32_HOST_SCSIID,
282 .use_clustering = DISABLE_CLUSTERING,
283 .eh_abort_handler = nsp32_eh_abort,
284 .eh_bus_reset_handler = nsp32_eh_bus_reset,
285 .eh_host_reset_handler = nsp32_eh_host_reset,
286
287};
288
289#include "nsp32_io.h"
290
291
292
293
294#ifndef NSP32_DEBUG
295# define NSP32_DEBUG_MASK 0x000000
296# define nsp32_msg(type, args...) nsp32_message ("", 0, (type), args)
297# define nsp32_dbg(mask, args...)
298#else
299# define NSP32_DEBUG_MASK 0xffffff
300# define nsp32_msg(type, args...) \
301 nsp32_message (__func__, __LINE__, (type), args)
302# define nsp32_dbg(mask, args...) \
303 nsp32_dmessage(__func__, __LINE__, (mask), args)
304#endif
305
306#define NSP32_DEBUG_QUEUECOMMAND BIT(0)
307#define NSP32_DEBUG_REGISTER BIT(1)
308#define NSP32_DEBUG_AUTOSCSI BIT(2)
309#define NSP32_DEBUG_INTR BIT(3)
310#define NSP32_DEBUG_SGLIST BIT(4)
311#define NSP32_DEBUG_BUSFREE BIT(5)
312#define NSP32_DEBUG_CDB_CONTENTS BIT(6)
313#define NSP32_DEBUG_RESELECTION BIT(7)
314#define NSP32_DEBUG_MSGINOCCUR BIT(8)
315#define NSP32_DEBUG_EEPROM BIT(9)
316#define NSP32_DEBUG_MSGOUTOCCUR BIT(10)
317#define NSP32_DEBUG_BUSRESET BIT(11)
318#define NSP32_DEBUG_RESTART BIT(12)
319#define NSP32_DEBUG_SYNC BIT(13)
320#define NSP32_DEBUG_WAIT BIT(14)
321#define NSP32_DEBUG_TARGETFLAG BIT(15)
322#define NSP32_DEBUG_PROC BIT(16)
323#define NSP32_DEBUG_INIT BIT(17)
324#define NSP32_SPECIAL_PRINT_REGISTER BIT(20)
325
326#define NSP32_DEBUG_BUF_LEN 100
327
328static void nsp32_message(const char *func, int line, char *type, char *fmt, ...)
329{
330 va_list args;
331 char buf[NSP32_DEBUG_BUF_LEN];
332
333 va_start(args, fmt);
334 vsnprintf(buf, sizeof(buf), fmt, args);
335 va_end(args);
336
337#ifndef NSP32_DEBUG
338 printk("%snsp32: %s\n", type, buf);
339#else
340 printk("%snsp32: %s (%d): %s\n", type, func, line, buf);
341#endif
342}
343
344#ifdef NSP32_DEBUG
345static void nsp32_dmessage(const char *func, int line, int mask, char *fmt, ...)
346{
347 va_list args;
348 char buf[NSP32_DEBUG_BUF_LEN];
349
350 va_start(args, fmt);
351 vsnprintf(buf, sizeof(buf), fmt, args);
352 va_end(args);
353
354 if (mask & NSP32_DEBUG_MASK) {
355 printk("nsp32-debug: 0x%x %s (%d): %s\n", mask, func, line, buf);
356 }
357}
358#endif
359
360#ifdef NSP32_DEBUG
361# include "nsp32_debug.c"
362#else
363# define show_command(arg)
364# define show_busphase(arg)
365# define show_autophase(arg)
366#endif
367
368
369
370
371static void nsp32_build_identify(struct scsi_cmnd *SCpnt)
372{
373 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
374 int pos = data->msgout_len;
375 int mode = FALSE;
376
377
378 if (disc_priv == 0) {
379
380 }
381
382 data->msgoutbuf[pos] = IDENTIFY(mode, SCpnt->device->lun); pos++;
383
384 data->msgout_len = pos;
385}
386
387
388
389
390static void nsp32_build_sdtr(struct scsi_cmnd *SCpnt,
391 unsigned char period,
392 unsigned char offset)
393{
394 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
395 int pos = data->msgout_len;
396
397 data->msgoutbuf[pos] = EXTENDED_MESSAGE; pos++;
398 data->msgoutbuf[pos] = EXTENDED_SDTR_LEN; pos++;
399 data->msgoutbuf[pos] = EXTENDED_SDTR; pos++;
400 data->msgoutbuf[pos] = period; pos++;
401 data->msgoutbuf[pos] = offset; pos++;
402
403 data->msgout_len = pos;
404}
405
406
407
408
409static void nsp32_build_nop(struct scsi_cmnd *SCpnt)
410{
411 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
412 int pos = data->msgout_len;
413
414 if (pos != 0) {
415 nsp32_msg(KERN_WARNING,
416 "Some messages are already contained!");
417 return;
418 }
419
420 data->msgoutbuf[pos] = NOP; pos++;
421 data->msgout_len = pos;
422}
423
424
425
426
427static void nsp32_build_reject(struct scsi_cmnd *SCpnt)
428{
429 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
430 int pos = data->msgout_len;
431
432 data->msgoutbuf[pos] = MESSAGE_REJECT; pos++;
433 data->msgout_len = pos;
434}
435
436
437
438
439#if 0
440static void nsp32_start_timer(struct scsi_cmnd *SCpnt, int time)
441{
442 unsigned int base = SCpnt->host->io_port;
443
444 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
445
446 if (time & (~TIMER_CNT_MASK)) {
447 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
448 }
449
450 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK);
451}
452#endif
453
454
455
456
457
458static int nsp32_selection_autopara(struct scsi_cmnd *SCpnt)
459{
460 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
461 unsigned int base = SCpnt->device->host->io_port;
462 unsigned int host_id = SCpnt->device->host->this_id;
463 unsigned char target = scmd_id(SCpnt);
464 nsp32_autoparam *param = data->autoparam;
465 unsigned char phase;
466 int i, ret;
467 unsigned int msgout;
468 u16_le s;
469
470 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
471
472
473
474
475 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
476 if (phase != BUSMON_BUS_FREE) {
477 nsp32_msg(KERN_WARNING, "bus busy");
478 show_busphase(phase & BUSMON_PHASE_MASK);
479 SCpnt->result = DID_BUS_BUSY << 16;
480 return FALSE;
481 }
482
483
484
485
486
487
488
489 if (data->msgout_len == 0) {
490 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
491 SCpnt->result = DID_ERROR << 16;
492 return FALSE;
493 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
494 msgout = 0;
495 for (i = 0; i < data->msgout_len; i++) {
496
497
498
499
500
501
502 msgout >>= 8;
503 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
504 }
505 msgout |= MV_VALID;
506 msgout |= (unsigned int)data->msgout_len;
507 } else {
508
509 msgout = 0;
510 }
511
512
513
514
515
516
517
518 memset(param, 0, sizeof(nsp32_autoparam));
519
520
521 for (i = 0; i < SCpnt->cmd_len; i++) {
522 param->cdb[4 * i] = SCpnt->cmnd[i];
523 }
524
525
526 param->msgout = cpu_to_le32(msgout);
527
528
529 param->syncreg = data->cur_target->syncreg;
530 param->ackwidth = data->cur_target->ackwidth;
531 param->target_id = BIT(host_id) | BIT(target);
532 param->sample_reg = data->cur_target->sample_reg;
533
534
535
536
537 param->command_control = cpu_to_le16(CLEAR_CDB_FIFO_POINTER |
538 AUTOSCSI_START |
539 AUTO_MSGIN_00_OR_04 |
540 AUTO_MSGIN_02 |
541 AUTO_ATN );
542
543
544
545 s = 0;
546 switch (data->trans_method) {
547 case NSP32_TRANSFER_BUSMASTER:
548 s |= BM_START;
549 break;
550 case NSP32_TRANSFER_MMIO:
551 s |= CB_MMIO_MODE;
552 break;
553 case NSP32_TRANSFER_PIO:
554 s |= CB_IO_MODE;
555 break;
556 default:
557 nsp32_msg(KERN_ERR, "unknown trans_method");
558 break;
559 }
560
561
562
563
564 s |= (TRANSFER_GO | ALL_COUNTER_CLR);
565 param->transfer_control = cpu_to_le16(s);
566
567
568 param->sgt_pointer = cpu_to_le32(data->cur_lunt->sglun_paddr);
569
570
571
572
573 nsp32_write4(base, SGT_ADR, data->auto_paddr);
574 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER |
575 AUTO_PARAMETER );
576
577
578
579
580 ret = nsp32_arbitration(SCpnt, base);
581
582 return ret;
583}
584
585
586
587
588
589static int nsp32_selection_autoscsi(struct scsi_cmnd *SCpnt)
590{
591 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
592 unsigned int base = SCpnt->device->host->io_port;
593 unsigned int host_id = SCpnt->device->host->this_id;
594 unsigned char target = scmd_id(SCpnt);
595 unsigned char phase;
596 int status;
597 unsigned short command = 0;
598 unsigned int msgout = 0;
599 unsigned short execph;
600 int i;
601
602 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "in");
603
604
605
606
607 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
608
609
610
611
612 phase = nsp32_read1(base, SCSI_BUS_MONITOR);
613 if(((phase & BUSMON_BSY) == 1) || (phase & BUSMON_SEL) == 1) {
614 nsp32_msg(KERN_WARNING, "bus busy");
615 SCpnt->result = DID_BUS_BUSY << 16;
616 status = 1;
617 goto out;
618 }
619
620
621
622
623 execph = nsp32_read2(base, SCSI_EXECUTE_PHASE);
624
625
626
627
628 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER);
629
630
631
632
633 for (i = 0; i < SCpnt->cmd_len; i++) {
634 nsp32_write1(base, COMMAND_DATA, SCpnt->cmnd[i]);
635 }
636 nsp32_dbg(NSP32_DEBUG_CDB_CONTENTS, "CDB[0]=[0x%x]", SCpnt->cmnd[0]);
637
638
639
640
641 nsp32_write1(base, SCSI_OUT_LATCH_TARGET_ID, BIT(host_id) | BIT(target));
642
643
644
645
646
647
648
649 if (data->msgout_len == 0) {
650 nsp32_msg(KERN_ERR, "SCSI MsgOut without any message!");
651 SCpnt->result = DID_ERROR << 16;
652 status = 1;
653 goto out;
654 } else if (data->msgout_len > 0 && data->msgout_len <= 3) {
655 msgout = 0;
656 for (i = 0; i < data->msgout_len; i++) {
657
658
659
660
661
662
663 msgout >>= 8;
664 msgout |= ((unsigned int)(data->msgoutbuf[i]) << 24);
665 }
666 msgout |= MV_VALID;
667 msgout |= (unsigned int)data->msgout_len;
668 nsp32_write4(base, SCSI_MSG_OUT, msgout);
669 } else {
670
671 nsp32_write4(base, SCSI_MSG_OUT, 0);
672 }
673
674
675
676
677 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
678
679
680
681
682
683
684
685 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
686
687
688
689
690 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
691
692
693
694
695
696 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
697
698
699
700
701 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
702
703 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
704 "syncreg=0x%x, ackwidth=0x%x, sgtpaddr=0x%x, id=0x%x",
705 nsp32_read1(base, SYNC_REG), nsp32_read1(base, ACK_WIDTH),
706 nsp32_read4(base, SGT_ADR), nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID));
707 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "msgout_len=%d, msgout=0x%x",
708 data->msgout_len, msgout);
709
710
711
712
713 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
714
715
716
717
718 command = 0;
719 command |= (TRANSFER_GO | ALL_COUNTER_CLR);
720 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
721 if (scsi_bufflen(SCpnt) > 0) {
722 command |= BM_START;
723 }
724 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
725 command |= CB_MMIO_MODE;
726 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
727 command |= CB_IO_MODE;
728 }
729 nsp32_write2(base, TRANSFER_CONTROL, command);
730
731
732
733
734 command = (CLEAR_CDB_FIFO_POINTER |
735 AUTOSCSI_START |
736 AUTO_MSGIN_00_OR_04 |
737 AUTO_MSGIN_02 |
738 AUTO_ATN );
739 nsp32_write2(base, COMMAND_CONTROL, command);
740
741
742
743
744 status = nsp32_arbitration(SCpnt, base);
745
746 out:
747
748
749
750 nsp32_write2(base, IRQ_CONTROL, 0);
751
752 return status;
753}
754
755
756
757
758
759
760
761
762
763
764static int nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base)
765{
766 unsigned char arbit;
767 int status = TRUE;
768 int time = 0;
769
770 do {
771 arbit = nsp32_read1(base, ARBIT_STATUS);
772 time++;
773 } while ((arbit & (ARBIT_WIN | ARBIT_FAIL)) == 0 &&
774 (time <= ARBIT_TIMEOUT_TIME));
775
776 nsp32_dbg(NSP32_DEBUG_AUTOSCSI,
777 "arbit: 0x%x, delay time: %d", arbit, time);
778
779 if (arbit & ARBIT_WIN) {
780
781 SCpnt->result = DID_OK << 16;
782 nsp32_index_write1(base, EXT_PORT, LED_ON);
783 } else if (arbit & ARBIT_FAIL) {
784
785 SCpnt->result = DID_BUS_BUSY << 16;
786 status = FALSE;
787 } else {
788
789
790
791
792 nsp32_dbg(NSP32_DEBUG_AUTOSCSI, "arbit timeout");
793 SCpnt->result = DID_NO_CONNECT << 16;
794 status = FALSE;
795 }
796
797
798
799
800 nsp32_write1(base, SET_ARBIT, ARBIT_CLEAR);
801
802 return status;
803}
804
805
806
807
808
809
810
811
812
813static int nsp32_reselection(struct scsi_cmnd *SCpnt, unsigned char newlun)
814{
815 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
816 unsigned int host_id = SCpnt->device->host->this_id;
817 unsigned int base = SCpnt->device->host->io_port;
818 unsigned char tmpid, newid;
819
820 nsp32_dbg(NSP32_DEBUG_RESELECTION, "enter");
821
822
823
824
825 tmpid = nsp32_read1(base, RESELECT_ID);
826 tmpid &= (~BIT(host_id));
827 newid = 0;
828 while (tmpid) {
829 if (tmpid & 1) {
830 break;
831 }
832 tmpid >>= 1;
833 newid++;
834 }
835
836
837
838
839
840
841 if (newid >= ARRAY_SIZE(data->lunt) || newlun >= ARRAY_SIZE(data->lunt[0])) {
842 nsp32_msg(KERN_WARNING, "unknown id/lun");
843 return FALSE;
844 } else if(data->lunt[newid][newlun].SCpnt == NULL) {
845 nsp32_msg(KERN_WARNING, "no SCSI command is processing");
846 return FALSE;
847 }
848
849 data->cur_id = newid;
850 data->cur_lun = newlun;
851 data->cur_target = &(data->target[newid]);
852 data->cur_lunt = &(data->lunt[newid][newlun]);
853
854
855 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
856
857 return TRUE;
858}
859
860
861
862
863
864
865
866
867static int nsp32_setup_sg_table(struct scsi_cmnd *SCpnt)
868{
869 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
870 struct scatterlist *sg;
871 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
872 int num, i;
873 u32_le l;
874
875 if (sgt == NULL) {
876 nsp32_dbg(NSP32_DEBUG_SGLIST, "SGT == null");
877 return FALSE;
878 }
879
880 num = scsi_dma_map(SCpnt);
881 if (!num)
882 return TRUE;
883 else if (num < 0)
884 return FALSE;
885 else {
886 scsi_for_each_sg(SCpnt, sg, num, i) {
887
888
889
890 sgt[i].addr = cpu_to_le32(sg_dma_address(sg));
891 sgt[i].len = cpu_to_le32(sg_dma_len(sg));
892
893 if (le32_to_cpu(sgt[i].len) > 0x10000) {
894 nsp32_msg(KERN_ERR,
895 "can't transfer over 64KB at a time, size=0x%lx", le32_to_cpu(sgt[i].len));
896 return FALSE;
897 }
898 nsp32_dbg(NSP32_DEBUG_SGLIST,
899 "num 0x%x : addr 0x%lx len 0x%lx",
900 i,
901 le32_to_cpu(sgt[i].addr),
902 le32_to_cpu(sgt[i].len ));
903 }
904
905
906 l = le32_to_cpu(sgt[num-1].len);
907 sgt[num-1].len = cpu_to_le32(l | SGTEND);
908 }
909
910 return TRUE;
911}
912
913static int nsp32_queuecommand(struct scsi_cmnd *SCpnt, void (*done)(struct scsi_cmnd *))
914{
915 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
916 nsp32_target *target;
917 nsp32_lunt *cur_lunt;
918 int ret;
919
920 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
921 "enter. target: 0x%x LUN: 0x%x cmnd: 0x%x cmndlen: 0x%x "
922 "use_sg: 0x%x reqbuf: 0x%lx reqlen: 0x%x",
923 SCpnt->device->id, SCpnt->device->lun, SCpnt->cmnd[0], SCpnt->cmd_len,
924 scsi_sg_count(SCpnt), scsi_sglist(SCpnt), scsi_bufflen(SCpnt));
925
926 if (data->CurrentSC != NULL) {
927 nsp32_msg(KERN_ERR, "Currentsc != NULL. Cancel this command request");
928 data->CurrentSC = NULL;
929 SCpnt->result = DID_NO_CONNECT << 16;
930 done(SCpnt);
931 return 0;
932 }
933
934
935 if (scmd_id(SCpnt) == SCpnt->device->host->this_id) {
936 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "terget==host???");
937 SCpnt->result = DID_BAD_TARGET << 16;
938 done(SCpnt);
939 return 0;
940 }
941
942
943 if (SCpnt->device->lun >= MAX_LUN) {
944 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "no more lun");
945 SCpnt->result = DID_BAD_TARGET << 16;
946 done(SCpnt);
947 return 0;
948 }
949
950 show_command(SCpnt);
951
952 SCpnt->scsi_done = done;
953 data->CurrentSC = SCpnt;
954 SCpnt->SCp.Status = CHECK_CONDITION;
955 SCpnt->SCp.Message = 0;
956 scsi_set_resid(SCpnt, scsi_bufflen(SCpnt));
957
958 SCpnt->SCp.ptr = (char *)scsi_sglist(SCpnt);
959 SCpnt->SCp.this_residual = scsi_bufflen(SCpnt);
960 SCpnt->SCp.buffer = NULL;
961 SCpnt->SCp.buffers_residual = 0;
962
963
964 data->msgout_len = 0;
965 data->msgin_len = 0;
966 cur_lunt = &(data->lunt[SCpnt->device->id][SCpnt->device->lun]);
967 cur_lunt->SCpnt = SCpnt;
968 cur_lunt->save_datp = 0;
969 cur_lunt->msgin03 = FALSE;
970 data->cur_lunt = cur_lunt;
971 data->cur_id = SCpnt->device->id;
972 data->cur_lun = SCpnt->device->lun;
973
974 ret = nsp32_setup_sg_table(SCpnt);
975 if (ret == FALSE) {
976 nsp32_msg(KERN_ERR, "SGT fail");
977 SCpnt->result = DID_ERROR << 16;
978 nsp32_scsi_done(SCpnt);
979 return 0;
980 }
981
982
983 nsp32_build_identify(SCpnt);
984
985
986
987
988
989
990 target = &data->target[scmd_id(SCpnt)];
991 data->cur_target = target;
992
993 if (!(target->sync_flag & (SDTR_DONE | SDTR_INITIATOR | SDTR_TARGET))) {
994 unsigned char period, offset;
995
996 if (trans_mode != ASYNC_MODE) {
997 nsp32_set_max_sync(data, target, &period, &offset);
998 nsp32_build_sdtr(SCpnt, period, offset);
999 target->sync_flag |= SDTR_INITIATOR;
1000 } else {
1001 nsp32_set_async(data, target);
1002 target->sync_flag |= SDTR_DONE;
1003 }
1004
1005 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1006 "SDTR: entry: %d start_period: 0x%x offset: 0x%x\n",
1007 target->limit_entry, period, offset);
1008 } else if (target->sync_flag & SDTR_INITIATOR) {
1009
1010
1011
1012
1013
1014 nsp32_set_async(data, target);
1015 target->sync_flag &= ~SDTR_INITIATOR;
1016 target->sync_flag |= SDTR_DONE;
1017
1018 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1019 "SDTR_INITIATOR: fall back to async");
1020 } else if (target->sync_flag & SDTR_TARGET) {
1021
1022
1023
1024
1025
1026 nsp32_set_async(data, target);
1027 target->sync_flag &= ~SDTR_TARGET;
1028 target->sync_flag |= SDTR_DONE;
1029
1030 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND,
1031 "Unknown SDTR from target is reached, fall back to async.");
1032 }
1033
1034 nsp32_dbg(NSP32_DEBUG_TARGETFLAG,
1035 "target: %d sync_flag: 0x%x syncreg: 0x%x ackwidth: 0x%x",
1036 SCpnt->device->id, target->sync_flag, target->syncreg,
1037 target->ackwidth);
1038
1039
1040 if (auto_param == 0) {
1041 ret = nsp32_selection_autopara(SCpnt);
1042 } else {
1043 ret = nsp32_selection_autoscsi(SCpnt);
1044 }
1045
1046 if (ret != TRUE) {
1047 nsp32_dbg(NSP32_DEBUG_QUEUECOMMAND, "selection fail");
1048 nsp32_scsi_done(SCpnt);
1049 }
1050
1051 return 0;
1052}
1053
1054
1055static int nsp32hw_init(nsp32_hw_data *data)
1056{
1057 unsigned int base = data->BaseAddress;
1058 unsigned short irq_stat;
1059 unsigned long lc_reg;
1060 unsigned char power;
1061
1062 lc_reg = nsp32_index_read4(base, CFG_LATE_CACHE);
1063 if ((lc_reg & 0xff00) == 0) {
1064 lc_reg |= (0x20 << 8);
1065 nsp32_index_write2(base, CFG_LATE_CACHE, lc_reg & 0xffff);
1066 }
1067
1068 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1069 nsp32_write2(base, TRANSFER_CONTROL, 0);
1070 nsp32_write4(base, BM_CNT, 0);
1071 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1072
1073 do {
1074 irq_stat = nsp32_read2(base, IRQ_STATUS);
1075 nsp32_dbg(NSP32_DEBUG_INIT, "irq_stat 0x%x", irq_stat);
1076 } while (irq_stat & IRQSTATUS_ANY_IRQ);
1077
1078
1079
1080
1081
1082 if ((data->trans_method & NSP32_TRANSFER_PIO) ||
1083 (data->trans_method & NSP32_TRANSFER_MMIO)) {
1084 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x40);
1085 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x40);
1086 } else if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1087 nsp32_index_write1(base, FIFO_FULL_SHLD_COUNT, 0x10);
1088 nsp32_index_write1(base, FIFO_EMPTY_SHLD_COUNT, 0x60);
1089 } else {
1090 nsp32_dbg(NSP32_DEBUG_INIT, "unknown transfer mode");
1091 }
1092
1093 nsp32_dbg(NSP32_DEBUG_INIT, "full 0x%x emp 0x%x",
1094 nsp32_index_read1(base, FIFO_FULL_SHLD_COUNT),
1095 nsp32_index_read1(base, FIFO_EMPTY_SHLD_COUNT));
1096
1097 nsp32_index_write1(base, CLOCK_DIV, data->clock);
1098 nsp32_index_write1(base, BM_CYCLE, MEMRD_CMD1 | SGT_AUTO_PARA_MEMED_CMD);
1099 nsp32_write1(base, PARITY_CONTROL, 0);
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116 nsp32_index_write2(base, MISC_WR,
1117 (SCSI_DIRECTION_DETECTOR_SELECT |
1118 DELAYED_BMSTART |
1119 MASTER_TERMINATION_SELECT |
1120 BMREQ_NEGATE_TIMING_SEL |
1121 AUTOSEL_TIMING_SEL |
1122 BMSTOP_CHANGE2_NONDATA_PHASE));
1123
1124 nsp32_index_write1(base, TERM_PWR_CONTROL, 0);
1125 power = nsp32_index_read1(base, TERM_PWR_CONTROL);
1126 if (!(power & SENSE)) {
1127 nsp32_msg(KERN_INFO, "term power on");
1128 nsp32_index_write1(base, TERM_PWR_CONTROL, BPWR);
1129 }
1130
1131 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1132 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1133
1134 nsp32_write1(base, SYNC_REG, 0);
1135 nsp32_write1(base, ACK_WIDTH, 0);
1136 nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME);
1137
1138
1139
1140
1141
1142 nsp32_index_write2(base, IRQ_SELECT, IRQSELECT_TIMER_IRQ |
1143 IRQSELECT_SCSIRESET_IRQ |
1144 IRQSELECT_FIFO_SHLD_IRQ |
1145 IRQSELECT_RESELECT_IRQ |
1146 IRQSELECT_PHASE_CHANGE_IRQ |
1147 IRQSELECT_AUTO_SCSI_SEQ_IRQ |
1148
1149 IRQSELECT_TARGET_ABORT_IRQ |
1150 IRQSELECT_MASTER_ABORT_IRQ );
1151 nsp32_write2(base, IRQ_CONTROL, 0);
1152
1153
1154 nsp32_index_write1(base, EXT_PORT_DDR, LED_OFF);
1155 nsp32_index_write1(base, EXT_PORT, LED_OFF);
1156
1157 return TRUE;
1158}
1159
1160
1161
1162static irqreturn_t do_nsp32_isr(int irq, void *dev_id)
1163{
1164 nsp32_hw_data *data = dev_id;
1165 unsigned int base = data->BaseAddress;
1166 struct scsi_cmnd *SCpnt = data->CurrentSC;
1167 unsigned short auto_stat, irq_stat, trans_stat;
1168 unsigned char busmon, busphase;
1169 unsigned long flags;
1170 int ret;
1171 int handled = 0;
1172 struct Scsi_Host *host = data->Host;
1173
1174 spin_lock_irqsave(host->host_lock, flags);
1175
1176
1177
1178
1179 irq_stat = nsp32_read2(base, IRQ_STATUS);
1180 nsp32_dbg(NSP32_DEBUG_INTR,
1181 "enter IRQ: %d, IRQstatus: 0x%x", irq, irq_stat);
1182
1183 if ((irq_stat & IRQSTATUS_ANY_IRQ) == 0) {
1184 nsp32_dbg(NSP32_DEBUG_INTR, "shared interrupt: irq other 0x%x", irq_stat);
1185 goto out2;
1186 }
1187 handled = 1;
1188 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
1189
1190 busmon = nsp32_read1(base, SCSI_BUS_MONITOR);
1191 busphase = busmon & BUSMON_PHASE_MASK;
1192
1193 trans_stat = nsp32_read2(base, TRANSFER_STATUS);
1194 if ((irq_stat == 0xffff) && (trans_stat == 0xffff)) {
1195 nsp32_msg(KERN_INFO, "card disconnect");
1196 if (data->CurrentSC != NULL) {
1197 nsp32_msg(KERN_INFO, "clean up current SCSI command");
1198 SCpnt->result = DID_BAD_TARGET << 16;
1199 nsp32_scsi_done(SCpnt);
1200 }
1201 goto out;
1202 }
1203
1204
1205 if (irq_stat & IRQSTATUS_TIMER_IRQ) {
1206 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1207 nsp32_write2(base, TIMER_SET, TIMER_STOP);
1208 goto out;
1209 }
1210
1211
1212 if (irq_stat & IRQSTATUS_SCSIRESET_IRQ) {
1213 nsp32_msg(KERN_INFO, "detected someone do bus reset");
1214 nsp32_do_bus_reset(data);
1215 if (SCpnt != NULL) {
1216 SCpnt->result = DID_RESET << 16;
1217 nsp32_scsi_done(SCpnt);
1218 }
1219 goto out;
1220 }
1221
1222 if (SCpnt == NULL) {
1223 nsp32_msg(KERN_WARNING, "SCpnt==NULL this can't be happened");
1224 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1225 goto out;
1226 }
1227
1228
1229
1230
1231
1232
1233
1234 if(irq_stat & IRQSTATUS_AUTOSCSI_IRQ) {
1235
1236 auto_stat = nsp32_read2(base, SCSI_EXECUTE_PHASE);
1237 nsp32_write2(base, SCSI_EXECUTE_PHASE, 0);
1238
1239
1240 if (auto_stat & SELECTION_TIMEOUT) {
1241 nsp32_dbg(NSP32_DEBUG_INTR,
1242 "selection timeout occurred");
1243
1244 SCpnt->result = DID_TIME_OUT << 16;
1245 nsp32_scsi_done(SCpnt);
1246 goto out;
1247 }
1248
1249 if (auto_stat & MSGOUT_PHASE) {
1250
1251
1252
1253
1254
1255
1256
1257 if (!(auto_stat & MSG_IN_OCCUER) &&
1258 (data->msgout_len <= 3)) {
1259
1260
1261
1262
1263 data->msgout_len = 0;
1264 };
1265
1266 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1267 }
1268
1269 if ((auto_stat & DATA_IN_PHASE) &&
1270 (scsi_get_resid(SCpnt) > 0) &&
1271 ((nsp32_read2(base, FIFO_REST_CNT) & FIFO_REST_MASK) != 0)) {
1272 printk( "auto+fifo\n");
1273
1274 }
1275
1276 if (auto_stat & (DATA_IN_PHASE | DATA_OUT_PHASE)) {
1277
1278 nsp32_dbg(NSP32_DEBUG_INTR,
1279 "Data in/out phase processed");
1280
1281
1282 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1283 nsp32_read4(base, BM_CNT));
1284 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1285 nsp32_read4(base, SGT_ADR));
1286 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1287 nsp32_read4(base, SACK_CNT));
1288 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1289 nsp32_read4(base, SAVED_SACK_CNT));
1290
1291 scsi_set_resid(SCpnt, 0);
1292 }
1293
1294
1295
1296
1297 if (auto_stat & MSG_IN_OCCUER) {
1298 nsp32_msgin_occur(SCpnt, irq_stat, auto_stat);
1299 }
1300
1301
1302
1303
1304 if (auto_stat & MSG_OUT_OCCUER) {
1305 nsp32_msgout_occur(SCpnt);
1306 }
1307
1308
1309
1310
1311 if (auto_stat & BUS_FREE_OCCUER) {
1312 ret = nsp32_busfree_occur(SCpnt, auto_stat);
1313 if (ret == TRUE) {
1314 goto out;
1315 }
1316 }
1317
1318 if (auto_stat & STATUS_PHASE) {
1319
1320
1321
1322
1323
1324
1325
1326 SCpnt->result = (int)nsp32_read1(base, SCSI_CSB_IN);
1327 }
1328
1329 if (auto_stat & ILLEGAL_PHASE) {
1330
1331 nsp32_msg(KERN_WARNING,
1332 "AUTO SCSI ILLEGAL PHASE OCCUR!!!!");
1333
1334
1335
1336
1337
1338
1339 nsp32_sack_assert(data);
1340 nsp32_wait_req(data, NEGATE);
1341 nsp32_sack_negate(data);
1342
1343 }
1344
1345 if (auto_stat & COMMAND_PHASE) {
1346
1347 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1348 }
1349
1350 if (auto_stat & AUTOSCSI_BUSY) {
1351
1352 }
1353
1354 show_autophase(auto_stat);
1355 }
1356
1357
1358 if (irq_stat & IRQSTATUS_FIFO_SHLD_IRQ) {
1359 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1360
1361 switch(busphase) {
1362 case BUSPHASE_DATA_OUT:
1363 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1364
1365
1366
1367 break;
1368
1369 case BUSPHASE_DATA_IN:
1370 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1371
1372
1373
1374 break;
1375
1376 case BUSPHASE_STATUS:
1377 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1378
1379 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1380
1381 break;
1382 default:
1383 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1384 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1385 show_busphase(busphase);
1386 break;
1387 }
1388
1389 goto out;
1390 }
1391
1392
1393 if (irq_stat & IRQSTATUS_PHASE_CHANGE_IRQ) {
1394 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1395
1396 switch(busphase) {
1397 case BUSPHASE_MESSAGE_IN:
1398 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1399 nsp32_msgin_occur(SCpnt, irq_stat, 0);
1400 break;
1401 default:
1402 nsp32_msg(KERN_WARNING, "phase chg/other phase?");
1403 nsp32_msg(KERN_WARNING, "irq_stat=0x%x trans_stat=0x%x\n",
1404 irq_stat, trans_stat);
1405 show_busphase(busphase);
1406 break;
1407 }
1408 goto out;
1409 }
1410
1411
1412 if (irq_stat & IRQSTATUS_PCI_IRQ) {
1413 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1414
1415 }
1416
1417
1418 if (irq_stat & IRQSTATUS_BMCNTERR_IRQ) {
1419 nsp32_msg(KERN_ERR, "Received unexpected BMCNTERR IRQ! ");
1420
1421
1422
1423
1424
1425 }
1426
1427#if 0
1428 nsp32_dbg(NSP32_DEBUG_INTR,
1429 "irq_stat=0x%x trans_stat=0x%x", irq_stat, trans_stat);
1430 show_busphase(busphase);
1431#endif
1432
1433 out:
1434
1435 nsp32_write2(base, IRQ_CONTROL, 0);
1436
1437 out2:
1438 spin_unlock_irqrestore(host->host_lock, flags);
1439
1440 nsp32_dbg(NSP32_DEBUG_INTR, "exit");
1441
1442 return IRQ_RETVAL(handled);
1443}
1444
1445#undef SPRINTF
1446#define SPRINTF(args...) \
1447 do { \
1448 if(length > (pos - buffer)) { \
1449 pos += snprintf(pos, length - (pos - buffer) + 1, ## args); \
1450 nsp32_dbg(NSP32_DEBUG_PROC, "buffer=0x%p pos=0x%p length=%d %d\n", buffer, pos, length, length - (pos - buffer));\
1451 } \
1452 } while(0)
1453
1454static int nsp32_proc_info(struct Scsi_Host *host, char *buffer, char **start,
1455 off_t offset, int length, int inout)
1456{
1457 char *pos = buffer;
1458 int thislength;
1459 unsigned long flags;
1460 nsp32_hw_data *data;
1461 int hostno;
1462 unsigned int base;
1463 unsigned char mode_reg;
1464 int id, speed;
1465 long model;
1466
1467
1468 if (inout == TRUE) {
1469 return -EINVAL;
1470 }
1471
1472 hostno = host->host_no;
1473 data = (nsp32_hw_data *)host->hostdata;
1474 base = host->io_port;
1475
1476 SPRINTF("NinjaSCSI-32 status\n\n");
1477 SPRINTF("Driver version: %s, $Revision: 1.33 $\n", nsp32_release_version);
1478 SPRINTF("SCSI host No.: %d\n", hostno);
1479 SPRINTF("IRQ: %d\n", host->irq);
1480 SPRINTF("IO: 0x%lx-0x%lx\n", host->io_port, host->io_port + host->n_io_port - 1);
1481 SPRINTF("MMIO(virtual address): 0x%lx-0x%lx\n", host->base, host->base + data->MmioLength - 1);
1482 SPRINTF("sg_tablesize: %d\n", host->sg_tablesize);
1483 SPRINTF("Chip revision: 0x%x\n", (nsp32_read2(base, INDEX_REG) >> 8) & 0xff);
1484
1485 mode_reg = nsp32_index_read1(base, CHIP_MODE);
1486 model = data->pci_devid->driver_data;
1487
1488#ifdef CONFIG_PM
1489 SPRINTF("Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no");
1490#endif
1491 SPRINTF("OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]);
1492
1493 spin_lock_irqsave(&(data->Lock), flags);
1494 SPRINTF("CurrentSC: 0x%p\n\n", data->CurrentSC);
1495 spin_unlock_irqrestore(&(data->Lock), flags);
1496
1497
1498 SPRINTF("SDTR status\n");
1499 for (id = 0; id < ARRAY_SIZE(data->target); id++) {
1500
1501 SPRINTF("id %d: ", id);
1502
1503 if (id == host->this_id) {
1504 SPRINTF("----- NinjaSCSI-32 host adapter\n");
1505 continue;
1506 }
1507
1508 if (data->target[id].sync_flag == SDTR_DONE) {
1509 if (data->target[id].period == 0 &&
1510 data->target[id].offset == ASYNC_OFFSET ) {
1511 SPRINTF("async");
1512 } else {
1513 SPRINTF(" sync");
1514 }
1515 } else {
1516 SPRINTF(" none");
1517 }
1518
1519 if (data->target[id].period != 0) {
1520
1521 speed = 1000000 / (data->target[id].period * 4);
1522
1523 SPRINTF(" transfer %d.%dMB/s, offset %d",
1524 speed / 1000,
1525 speed % 1000,
1526 data->target[id].offset
1527 );
1528 }
1529 SPRINTF("\n");
1530 }
1531
1532
1533 thislength = pos - (buffer + offset);
1534
1535 if(thislength < 0) {
1536 *start = NULL;
1537 return 0;
1538 }
1539
1540
1541 thislength = min(thislength, length);
1542 *start = buffer + offset;
1543
1544 return thislength;
1545}
1546#undef SPRINTF
1547
1548
1549
1550
1551
1552
1553
1554static void nsp32_scsi_done(struct scsi_cmnd *SCpnt)
1555{
1556 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1557 unsigned int base = SCpnt->device->host->io_port;
1558
1559 scsi_dma_unmap(SCpnt);
1560
1561
1562
1563
1564 nsp32_write2(base, TRANSFER_CONTROL, 0);
1565 nsp32_write4(base, BM_CNT, 0);
1566
1567
1568
1569
1570 (*SCpnt->scsi_done)(SCpnt);
1571
1572
1573
1574
1575 data->cur_lunt->SCpnt = NULL;
1576 data->cur_lunt = NULL;
1577 data->cur_target = NULL;
1578 data->CurrentSC = NULL;
1579}
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592static int nsp32_busfree_occur(struct scsi_cmnd *SCpnt, unsigned short execph)
1593{
1594 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1595 unsigned int base = SCpnt->device->host->io_port;
1596
1597 nsp32_dbg(NSP32_DEBUG_BUSFREE, "enter execph=0x%x", execph);
1598 show_autophase(execph);
1599
1600 nsp32_write4(base, BM_CNT, 0);
1601 nsp32_write2(base, TRANSFER_CONTROL, 0);
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614 if (execph & MSGIN_02_VALID) {
1615 nsp32_dbg(NSP32_DEBUG_BUSFREE, "MsgIn02_Valid");
1616
1617
1618
1619
1620
1621 if (!(execph & MSGIN_00_VALID) &&
1622 ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE))) {
1623 unsigned int sacklen, s_sacklen;
1624
1625
1626
1627
1628 sacklen = nsp32_read4(base, SACK_CNT );
1629 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
1630
1631
1632
1633
1634
1635 if (s_sacklen > 0) {
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647 if (sacklen != s_sacklen) {
1648 data->cur_lunt->msgin03 = FALSE;
1649 } else {
1650 data->cur_lunt->msgin03 = TRUE;
1651 }
1652
1653 nsp32_adjust_busfree(SCpnt, s_sacklen);
1654 }
1655 }
1656
1657
1658
1659 } else {
1660
1661
1662
1663 }
1664
1665 if (execph & MSGIN_03_VALID) {
1666
1667 }
1668
1669
1670
1671
1672 if (data->cur_target->sync_flag & SDTR_INITIATOR) {
1673
1674
1675
1676
1677 nsp32_set_async(data, data->cur_target);
1678 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
1679 data->cur_target->sync_flag |= SDTR_DONE;
1680 } else if (data->cur_target->sync_flag & SDTR_TARGET) {
1681
1682
1683
1684
1685 if (execph & (MSGIN_00_VALID | MSGIN_04_VALID)) {
1686
1687
1688
1689
1690 } else {
1691
1692
1693
1694
1695
1696 nsp32_set_async(data, data->cur_target);
1697 }
1698 data->cur_target->sync_flag &= ~SDTR_TARGET;
1699 data->cur_target->sync_flag |= SDTR_DONE;
1700 }
1701
1702
1703
1704
1705
1706
1707
1708 if (execph & MSGIN_00_VALID) {
1709
1710 nsp32_dbg(NSP32_DEBUG_BUSFREE, "command complete");
1711
1712 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1713 SCpnt->SCp.Message = 0;
1714 nsp32_dbg(NSP32_DEBUG_BUSFREE,
1715 "normal end stat=0x%x resid=0x%x\n",
1716 SCpnt->SCp.Status, scsi_get_resid(SCpnt));
1717 SCpnt->result = (DID_OK << 16) |
1718 (SCpnt->SCp.Message << 8) |
1719 (SCpnt->SCp.Status << 0);
1720 nsp32_scsi_done(SCpnt);
1721
1722 return TRUE;
1723 } else if (execph & MSGIN_04_VALID) {
1724
1725 SCpnt->SCp.Status = nsp32_read1(base, SCSI_CSB_IN);
1726 SCpnt->SCp.Message = 4;
1727
1728 nsp32_dbg(NSP32_DEBUG_BUSFREE, "disconnect");
1729 return TRUE;
1730 } else {
1731
1732 nsp32_msg(KERN_WARNING, "unexpected bus free occurred");
1733
1734
1735
1736 SCpnt->result = DID_ERROR << 16;
1737 nsp32_scsi_done(SCpnt);
1738 return TRUE;
1739 }
1740 return FALSE;
1741}
1742
1743
1744
1745
1746
1747
1748
1749
1750static void nsp32_adjust_busfree(struct scsi_cmnd *SCpnt, unsigned int s_sacklen)
1751{
1752 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1753 int old_entry = data->cur_entry;
1754 int new_entry;
1755 int sg_num = data->cur_lunt->sg_num;
1756 nsp32_sgtable *sgt = data->cur_lunt->sglun->sgt;
1757 unsigned int restlen, sentlen;
1758 u32_le len, addr;
1759
1760 nsp32_dbg(NSP32_DEBUG_SGLIST, "old resid=0x%x", scsi_get_resid(SCpnt));
1761
1762
1763 s_sacklen -= le32_to_cpu(sgt[old_entry].addr) & 3;
1764
1765
1766
1767
1768
1769 sentlen = 0;
1770 for (new_entry = old_entry; new_entry < sg_num; new_entry++) {
1771 sentlen += (le32_to_cpu(sgt[new_entry].len) & ~SGTEND);
1772 if (sentlen > s_sacklen) {
1773 break;
1774 }
1775 }
1776
1777
1778 if (new_entry == sg_num) {
1779 goto last;
1780 }
1781
1782 if (sentlen == s_sacklen) {
1783
1784
1785
1786 }
1787
1788
1789 restlen = sentlen - s_sacklen;
1790
1791
1792 len = le32_to_cpu(sgt[new_entry].len);
1793 addr = le32_to_cpu(sgt[new_entry].addr);
1794 addr += (len - restlen);
1795 sgt[new_entry].addr = cpu_to_le32(addr);
1796 sgt[new_entry].len = cpu_to_le32(restlen);
1797
1798
1799 data->cur_entry = new_entry;
1800
1801 return;
1802
1803 last:
1804 if (scsi_get_resid(SCpnt) < sentlen) {
1805 nsp32_msg(KERN_ERR, "resid underflow");
1806 }
1807
1808 scsi_set_resid(SCpnt, scsi_get_resid(SCpnt) - sentlen);
1809 nsp32_dbg(NSP32_DEBUG_SGLIST, "new resid=0x%x", scsi_get_resid(SCpnt));
1810
1811
1812
1813 return;
1814}
1815
1816
1817
1818
1819
1820
1821
1822
1823static void nsp32_msgout_occur(struct scsi_cmnd *SCpnt)
1824{
1825 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1826 unsigned int base = SCpnt->device->host->io_port;
1827
1828 long new_sgtp;
1829 int i;
1830
1831 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1832 "enter: msgout_len: 0x%x", data->msgout_len);
1833
1834
1835
1836
1837
1838 if (data->msgout_len == 0) {
1839 nsp32_build_nop(SCpnt);
1840 }
1841
1842
1843
1844
1845
1846
1847 new_sgtp = data->cur_lunt->sglun_paddr +
1848 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
1849
1850
1851
1852
1853 for (i = 0; i < data->msgout_len; i++) {
1854 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR,
1855 "%d : 0x%x", i, data->msgoutbuf[i]);
1856
1857
1858
1859
1860 nsp32_wait_req(data, ASSERT);
1861
1862 if (i == (data->msgout_len - 1)) {
1863
1864
1865
1866
1867
1868
1869
1870 nsp32_write2(base, COMMAND_CONTROL,
1871 (CLEAR_CDB_FIFO_POINTER |
1872 AUTO_COMMAND_PHASE |
1873 AUTOSCSI_RESTART |
1874 AUTO_MSGIN_00_OR_04 |
1875 AUTO_MSGIN_02 ));
1876 }
1877
1878
1879
1880
1881 nsp32_write1(base, SCSI_DATA_WITH_ACK, data->msgoutbuf[i]);
1882 nsp32_wait_sack(data, NEGATE);
1883
1884 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "bus: 0x%x\n",
1885 nsp32_read1(base, SCSI_BUS_MONITOR));
1886 };
1887
1888 data->msgout_len = 0;
1889
1890 nsp32_dbg(NSP32_DEBUG_MSGOUTOCCUR, "exit");
1891}
1892
1893
1894
1895
1896
1897
1898
1899static void nsp32_restart_autoscsi(struct scsi_cmnd *SCpnt, unsigned short command)
1900{
1901 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1902 unsigned int base = data->BaseAddress;
1903 unsigned short transfer = 0;
1904
1905 nsp32_dbg(NSP32_DEBUG_RESTART, "enter");
1906
1907 if (data->cur_target == NULL || data->cur_lunt == NULL) {
1908 nsp32_msg(KERN_ERR, "Target or Lun is invalid");
1909 }
1910
1911
1912
1913
1914
1915 nsp32_write1(base, SYNC_REG, data->cur_target->syncreg);
1916
1917
1918
1919
1920 nsp32_write1(base, ACK_WIDTH, data->cur_target->ackwidth);
1921
1922
1923
1924
1925 nsp32_write1(base, SREQ_SMPL_RATE, data->cur_target->sample_reg);
1926
1927
1928
1929
1930 nsp32_write4(base, SGT_ADR, data->cur_lunt->sglun_paddr);
1931
1932
1933
1934
1935 transfer = 0;
1936 transfer |= (TRANSFER_GO | ALL_COUNTER_CLR);
1937 if (data->trans_method & NSP32_TRANSFER_BUSMASTER) {
1938 if (scsi_bufflen(SCpnt) > 0) {
1939 transfer |= BM_START;
1940 }
1941 } else if (data->trans_method & NSP32_TRANSFER_MMIO) {
1942 transfer |= CB_MMIO_MODE;
1943 } else if (data->trans_method & NSP32_TRANSFER_PIO) {
1944 transfer |= CB_IO_MODE;
1945 }
1946 nsp32_write2(base, TRANSFER_CONTROL, transfer);
1947
1948
1949
1950
1951
1952
1953 command |= (CLEAR_CDB_FIFO_POINTER |
1954 AUTO_COMMAND_PHASE |
1955 AUTOSCSI_RESTART );
1956 nsp32_write2(base, COMMAND_CONTROL, command);
1957
1958 nsp32_dbg(NSP32_DEBUG_RESTART, "exit");
1959}
1960
1961
1962
1963
1964
1965static void nsp32_msgin_occur(struct scsi_cmnd *SCpnt,
1966 unsigned long irq_status,
1967 unsigned short execph)
1968{
1969 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
1970 unsigned int base = SCpnt->device->host->io_port;
1971 unsigned char msg;
1972 unsigned char msgtype;
1973 unsigned char newlun;
1974 unsigned short command = 0;
1975 int msgclear = TRUE;
1976 long new_sgtp;
1977 int ret;
1978
1979
1980
1981
1982
1983
1984 msg = nsp32_read1(base, SCSI_DATA_IN);
1985 data->msginbuf[(unsigned char)data->msgin_len] = msg;
1986 msgtype = data->msginbuf[0];
1987 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR,
1988 "enter: msglen: 0x%x msgin: 0x%x msgtype: 0x%x",
1989 data->msgin_len, msg, msgtype);
1990
1991
1992
1993
1994
1995
1996
1997
1998 nsp32_sack_assert(data);
1999
2000
2001
2002
2003 if (msgtype & 0x80) {
2004 if (!(irq_status & IRQSTATUS_RESELECT_OCCUER)) {
2005
2006 goto reject;
2007 }
2008
2009 newlun = msgtype & 0x1f;
2010 ret = nsp32_reselection(SCpnt, newlun);
2011 if (ret == TRUE) {
2012 goto restart;
2013 } else {
2014 goto reject;
2015 }
2016 }
2017
2018
2019
2020
2021
2022
2023 switch (msgtype) {
2024
2025
2026
2027 case COMMAND_COMPLETE:
2028 case DISCONNECT:
2029
2030
2031
2032
2033 nsp32_msg(KERN_WARNING,
2034 "unexpected message of AutoSCSI MsgIn: 0x%x", msg);
2035 break;
2036
2037 case RESTORE_POINTERS:
2038
2039
2040
2041
2042 if ((execph & DATA_IN_PHASE) || (execph & DATA_OUT_PHASE)) {
2043 unsigned int s_sacklen;
2044
2045 s_sacklen = nsp32_read4(base, SAVED_SACK_CNT);
2046 if ((execph & MSGIN_02_VALID) && (s_sacklen > 0)) {
2047 nsp32_adjust_busfree(SCpnt, s_sacklen);
2048 } else {
2049
2050 }
2051 }
2052 data->cur_lunt->msgin03 = FALSE;
2053
2054
2055
2056
2057 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2058
2059
2060
2061
2062 new_sgtp = data->cur_lunt->sglun_paddr +
2063 (data->cur_lunt->cur_entry * sizeof(nsp32_sgtable));
2064 nsp32_write4(base, SGT_ADR, new_sgtp);
2065
2066 break;
2067
2068 case SAVE_POINTERS:
2069
2070
2071
2072
2073 nsp32_msg (KERN_WARNING,
2074 "unexpected message of AutoSCSI MsgIn: SAVE_POINTERS");
2075
2076 break;
2077
2078 case MESSAGE_REJECT:
2079
2080
2081 if (data->cur_target->sync_flag &
2082 (SDTR_INITIATOR | SDTR_TARGET)) {
2083
2084
2085
2086
2087
2088 nsp32_set_async(data, data->cur_target);
2089 data->cur_target->sync_flag &= ~SDTR_INITIATOR;
2090 data->cur_target->sync_flag |= SDTR_DONE;
2091
2092 }
2093 break;
2094
2095 case LINKED_CMD_COMPLETE:
2096 case LINKED_FLG_CMD_COMPLETE:
2097
2098 nsp32_msg (KERN_WARNING,
2099 "unsupported message: 0x%x", msgtype);
2100 break;
2101
2102 case INITIATE_RECOVERY:
2103
2104
2105
2106 goto reject;
2107
2108
2109
2110
2111 case SIMPLE_QUEUE_TAG:
2112 case 0x23:
2113
2114
2115
2116
2117 if (data->msgin_len >= 1) {
2118 goto reject;
2119 }
2120
2121
2122 msgclear = FALSE;
2123
2124 break;
2125
2126
2127
2128
2129 case EXTENDED_MESSAGE:
2130 if (data->msgin_len < 1) {
2131
2132
2133
2134
2135 msgclear = FALSE;
2136 break;
2137 }
2138
2139 if ((data->msginbuf[1] + 1) > data->msgin_len) {
2140
2141
2142
2143
2144
2145
2146 msgclear = FALSE;
2147 break;
2148 }
2149
2150
2151
2152
2153
2154 switch (data->msginbuf[2]) {
2155 case EXTENDED_MODIFY_DATA_POINTER:
2156
2157 goto reject;
2158 break;
2159
2160 case EXTENDED_SDTR:
2161
2162
2163
2164 if (data->msgin_len != EXTENDED_SDTR_LEN + 1) {
2165
2166
2167
2168 goto reject;
2169 break;
2170 }
2171
2172 nsp32_analyze_sdtr(SCpnt);
2173
2174 break;
2175
2176 case EXTENDED_EXTENDED_IDENTIFY:
2177
2178 goto reject;
2179
2180 break;
2181
2182 case EXTENDED_WDTR:
2183 goto reject;
2184
2185 break;
2186
2187 default:
2188 goto reject;
2189 }
2190 break;
2191
2192 default:
2193 goto reject;
2194 }
2195
2196 restart:
2197 if (msgclear == TRUE) {
2198 data->msgin_len = 0;
2199
2200
2201
2202
2203
2204
2205
2206
2207 if (data->msgout_len > 0) {
2208 nsp32_write4(base, SCSI_MSG_OUT, 0);
2209 command |= AUTO_ATN;
2210 }
2211
2212
2213
2214
2215
2216 command |= (AUTO_MSGIN_00_OR_04 | AUTO_MSGIN_02);
2217
2218
2219
2220
2221 if (data->cur_lunt->msgin03 == TRUE) {
2222 command |= AUTO_MSGIN_03;
2223 }
2224 data->cur_lunt->msgin03 = FALSE;
2225 } else {
2226 data->msgin_len++;
2227 }
2228
2229
2230
2231
2232 nsp32_restart_autoscsi(SCpnt, command);
2233
2234
2235
2236
2237 nsp32_wait_req(data, NEGATE);
2238
2239
2240
2241
2242 nsp32_sack_negate(data);
2243
2244 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2245
2246 return;
2247
2248 reject:
2249 nsp32_msg(KERN_WARNING,
2250 "invalid or unsupported MessageIn, rejected. "
2251 "current msg: 0x%x (len: 0x%x), processing msg: 0x%x",
2252 msg, data->msgin_len, msgtype);
2253 nsp32_build_reject(SCpnt);
2254 data->msgin_len = 0;
2255
2256 goto restart;
2257}
2258
2259
2260
2261
2262static void nsp32_analyze_sdtr(struct scsi_cmnd *SCpnt)
2263{
2264 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2265 nsp32_target *target = data->cur_target;
2266 nsp32_sync_table *synct;
2267 unsigned char get_period = data->msginbuf[3];
2268 unsigned char get_offset = data->msginbuf[4];
2269 int entry;
2270 int syncnum;
2271
2272 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "enter");
2273
2274 synct = data->synct;
2275 syncnum = data->syncnum;
2276
2277
2278
2279
2280
2281
2282
2283
2284 if (target->sync_flag & SDTR_INITIATOR) {
2285
2286
2287
2288
2289 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target responds SDTR");
2290
2291 target->sync_flag &= ~SDTR_INITIATOR;
2292 target->sync_flag |= SDTR_DONE;
2293
2294
2295
2296
2297 if (get_offset > SYNC_OFFSET) {
2298
2299
2300
2301
2302 goto reject;
2303 }
2304
2305 if (get_offset == ASYNC_OFFSET) {
2306
2307
2308
2309
2310 goto async;
2311 }
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323 if (get_period < data->synct[0].period_num) {
2324
2325
2326
2327
2328 goto reject;
2329 }
2330
2331 entry = nsp32_search_period_entry(data, target, get_period);
2332
2333 if (entry < 0) {
2334
2335
2336
2337
2338 goto reject;
2339 }
2340
2341
2342
2343
2344 nsp32_set_sync_entry(data, target, entry, get_offset);
2345 } else {
2346
2347 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "target send SDTR");
2348
2349 target->sync_flag |= SDTR_INITIATOR;
2350
2351
2352 if (get_offset > SYNC_OFFSET) {
2353
2354 get_offset = SYNC_OFFSET;
2355 }
2356
2357
2358 if (get_period < data->synct[0].period_num) {
2359 get_period = data->synct[0].period_num;
2360 }
2361
2362 entry = nsp32_search_period_entry(data, target, get_period);
2363
2364 if (get_offset == ASYNC_OFFSET || entry < 0) {
2365 nsp32_set_async(data, target);
2366 nsp32_build_sdtr(SCpnt, 0, ASYNC_OFFSET);
2367 } else {
2368 nsp32_set_sync_entry(data, target, entry, get_offset);
2369 nsp32_build_sdtr(SCpnt, get_period, get_offset);
2370 }
2371 }
2372
2373 target->period = get_period;
2374 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit");
2375 return;
2376
2377 reject:
2378
2379
2380
2381
2382 nsp32_build_reject(SCpnt);
2383
2384 async:
2385 nsp32_set_async(data, target);
2386
2387 target->period = 0;
2388 nsp32_dbg(NSP32_DEBUG_MSGINOCCUR, "exit: set async");
2389 return;
2390}
2391
2392
2393
2394
2395
2396
2397static int nsp32_search_period_entry(nsp32_hw_data *data,
2398 nsp32_target *target,
2399 unsigned char period)
2400{
2401 int i;
2402
2403 if (target->limit_entry >= data->syncnum) {
2404 nsp32_msg(KERN_ERR, "limit_entry exceeds syncnum!");
2405 target->limit_entry = 0;
2406 }
2407
2408 for (i = target->limit_entry; i < data->syncnum; i++) {
2409 if (period >= data->synct[i].start_period &&
2410 period <= data->synct[i].end_period) {
2411 break;
2412 }
2413 }
2414
2415
2416
2417
2418
2419 if (i == data->syncnum) {
2420 i = -1;
2421 }
2422
2423 return i;
2424}
2425
2426
2427
2428
2429
2430static void nsp32_set_async(nsp32_hw_data *data, nsp32_target *target)
2431{
2432 unsigned char period = data->synct[target->limit_entry].period_num;
2433
2434 target->offset = ASYNC_OFFSET;
2435 target->period = 0;
2436 target->syncreg = TO_SYNCREG(period, ASYNC_OFFSET);
2437 target->ackwidth = 0;
2438 target->sample_reg = 0;
2439
2440 nsp32_dbg(NSP32_DEBUG_SYNC, "set async");
2441}
2442
2443
2444
2445
2446
2447static void nsp32_set_max_sync(nsp32_hw_data *data,
2448 nsp32_target *target,
2449 unsigned char *period,
2450 unsigned char *offset)
2451{
2452 unsigned char period_num, ackwidth;
2453
2454 period_num = data->synct[target->limit_entry].period_num;
2455 *period = data->synct[target->limit_entry].start_period;
2456 ackwidth = data->synct[target->limit_entry].ackwidth;
2457 *offset = SYNC_OFFSET;
2458
2459 target->syncreg = TO_SYNCREG(period_num, *offset);
2460 target->ackwidth = ackwidth;
2461 target->offset = *offset;
2462 target->sample_reg = 0;
2463}
2464
2465
2466
2467
2468
2469static void nsp32_set_sync_entry(nsp32_hw_data *data,
2470 nsp32_target *target,
2471 int entry,
2472 unsigned char offset)
2473{
2474 unsigned char period, ackwidth, sample_rate;
2475
2476 period = data->synct[entry].period_num;
2477 ackwidth = data->synct[entry].ackwidth;
2478 offset = offset;
2479 sample_rate = data->synct[entry].sample_rate;
2480
2481 target->syncreg = TO_SYNCREG(period, offset);
2482 target->ackwidth = ackwidth;
2483 target->offset = offset;
2484 target->sample_reg = sample_rate | SAMPLING_ENABLE;
2485
2486 nsp32_dbg(NSP32_DEBUG_SYNC, "set sync");
2487}
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498static void nsp32_wait_req(nsp32_hw_data *data, int state)
2499{
2500 unsigned int base = data->BaseAddress;
2501 int wait_time = 0;
2502 unsigned char bus, req_bit;
2503
2504 if (!((state == ASSERT) || (state == NEGATE))) {
2505 nsp32_msg(KERN_ERR, "unknown state designation");
2506 }
2507
2508 req_bit = (state == ASSERT ? BUSMON_REQ : 0);
2509
2510 do {
2511 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2512 if ((bus & BUSMON_REQ) == req_bit) {
2513 nsp32_dbg(NSP32_DEBUG_WAIT,
2514 "wait_time: %d", wait_time);
2515 return;
2516 }
2517 udelay(1);
2518 wait_time++;
2519 } while (wait_time < REQSACK_TIMEOUT_TIME);
2520
2521 nsp32_msg(KERN_WARNING, "wait REQ timeout, req_bit: 0x%x", req_bit);
2522}
2523
2524
2525
2526
2527static void nsp32_wait_sack(nsp32_hw_data *data, int state)
2528{
2529 unsigned int base = data->BaseAddress;
2530 int wait_time = 0;
2531 unsigned char bus, ack_bit;
2532
2533 if (!((state == ASSERT) || (state == NEGATE))) {
2534 nsp32_msg(KERN_ERR, "unknown state designation");
2535 }
2536
2537 ack_bit = (state == ASSERT ? BUSMON_ACK : 0);
2538
2539 do {
2540 bus = nsp32_read1(base, SCSI_BUS_MONITOR);
2541 if ((bus & BUSMON_ACK) == ack_bit) {
2542 nsp32_dbg(NSP32_DEBUG_WAIT,
2543 "wait_time: %d", wait_time);
2544 return;
2545 }
2546 udelay(1);
2547 wait_time++;
2548 } while (wait_time < REQSACK_TIMEOUT_TIME);
2549
2550 nsp32_msg(KERN_WARNING, "wait SACK timeout, ack_bit: 0x%x", ack_bit);
2551}
2552
2553
2554
2555
2556
2557
2558static void nsp32_sack_assert(nsp32_hw_data *data)
2559{
2560 unsigned int base = data->BaseAddress;
2561 unsigned char busctrl;
2562
2563 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2564 busctrl |= (BUSCTL_ACK | AUTODIRECTION | ACKENB);
2565 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2566}
2567
2568
2569
2570
2571static void nsp32_sack_negate(nsp32_hw_data *data)
2572{
2573 unsigned int base = data->BaseAddress;
2574 unsigned char busctrl;
2575
2576 busctrl = nsp32_read1(base, SCSI_BUS_CONTROL);
2577 busctrl &= ~BUSCTL_ACK;
2578 nsp32_write1(base, SCSI_BUS_CONTROL, busctrl);
2579}
2580
2581
2582
2583
2584
2585
2586
2587
2588
2589
2590static int nsp32_detect(struct pci_dev *pdev)
2591{
2592 struct Scsi_Host *host;
2593 struct resource *res;
2594 nsp32_hw_data *data;
2595 int ret;
2596 int i, j;
2597
2598 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
2599
2600
2601
2602
2603 host = scsi_host_alloc(&nsp32_template, sizeof(nsp32_hw_data));
2604 if (host == NULL) {
2605 nsp32_msg (KERN_ERR, "failed to scsi register");
2606 goto err;
2607 }
2608
2609
2610
2611
2612 data = (nsp32_hw_data *)host->hostdata;
2613
2614 memcpy(data, &nsp32_data_base, sizeof(nsp32_hw_data));
2615
2616 host->irq = data->IrqNumber;
2617 host->io_port = data->BaseAddress;
2618 host->unique_id = data->BaseAddress;
2619 host->n_io_port = data->NumAddress;
2620 host->base = (unsigned long)data->MmioAddress;
2621
2622 data->Host = host;
2623 spin_lock_init(&(data->Lock));
2624
2625 data->cur_lunt = NULL;
2626 data->cur_target = NULL;
2627
2628
2629
2630
2631 data->trans_method = NSP32_TRANSFER_BUSMASTER;
2632
2633
2634
2635
2636
2637
2638 data->clock = CLOCK_4;
2639
2640
2641
2642
2643 switch (data->clock) {
2644 case CLOCK_4:
2645
2646 data->synct = nsp32_sync_table_40M;
2647 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2648 break;
2649 case CLOCK_2:
2650
2651 data->synct = nsp32_sync_table_20M;
2652 data->syncnum = ARRAY_SIZE(nsp32_sync_table_20M);
2653 break;
2654 case PCICLK:
2655
2656 data->synct = nsp32_sync_table_pci;
2657 data->syncnum = ARRAY_SIZE(nsp32_sync_table_pci);
2658 break;
2659 default:
2660 nsp32_msg(KERN_WARNING,
2661 "Invalid clock div is selected, set CLOCK_4.");
2662
2663 data->clock = CLOCK_4;
2664 data->synct = nsp32_sync_table_40M;
2665 data->syncnum = ARRAY_SIZE(nsp32_sync_table_40M);
2666 }
2667
2668
2669
2670
2671
2672
2673
2674
2675 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
2676 nsp32_msg (KERN_ERR, "failed to set PCI DMA mask");
2677 goto scsi_unregister;
2678 }
2679
2680
2681
2682
2683 data->autoparam = pci_alloc_consistent(pdev, sizeof(nsp32_autoparam), &(data->auto_paddr));
2684 if (data->autoparam == NULL) {
2685 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2686 goto scsi_unregister;
2687 }
2688
2689
2690
2691
2692 data->sg_list = pci_alloc_consistent(pdev, NSP32_SG_TABLE_SIZE,
2693 &(data->sg_paddr));
2694 if (data->sg_list == NULL) {
2695 nsp32_msg(KERN_ERR, "failed to allocate DMA memory");
2696 goto free_autoparam;
2697 }
2698
2699 for (i = 0; i < ARRAY_SIZE(data->lunt); i++) {
2700 for (j = 0; j < ARRAY_SIZE(data->lunt[0]); j++) {
2701 int offset = i * ARRAY_SIZE(data->lunt[0]) + j;
2702 nsp32_lunt tmp = {
2703 .SCpnt = NULL,
2704 .save_datp = 0,
2705 .msgin03 = FALSE,
2706 .sg_num = 0,
2707 .cur_entry = 0,
2708 .sglun = &(data->sg_list[offset]),
2709 .sglun_paddr = data->sg_paddr + (offset * sizeof(nsp32_sglun)),
2710 };
2711
2712 data->lunt[i][j] = tmp;
2713 }
2714 }
2715
2716
2717
2718
2719 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2720 nsp32_target *target = &(data->target[i]);
2721
2722 target->limit_entry = 0;
2723 target->sync_flag = 0;
2724 nsp32_set_async(data, target);
2725 }
2726
2727
2728
2729
2730 ret = nsp32_getprom_param(data);
2731 if (ret == FALSE) {
2732 data->resettime = 3;
2733 }
2734
2735
2736
2737
2738 nsp32hw_init(data);
2739
2740 snprintf(data->info_str, sizeof(data->info_str),
2741 "NinjaSCSI-32Bi/UDE: irq %d, io 0x%lx+0x%x",
2742 host->irq, host->io_port, host->n_io_port);
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762 nsp32_do_bus_reset(data);
2763
2764 ret = request_irq(host->irq, do_nsp32_isr, IRQF_SHARED, "nsp32", data);
2765 if (ret < 0) {
2766 nsp32_msg(KERN_ERR, "Unable to allocate IRQ for NinjaSCSI32 "
2767 "SCSI PCI controller. Interrupt: %d", host->irq);
2768 goto free_sg_list;
2769 }
2770
2771
2772
2773
2774 res = request_region(host->io_port, host->n_io_port, "nsp32");
2775 if (res == NULL) {
2776 nsp32_msg(KERN_ERR,
2777 "I/O region 0x%lx+0x%lx is already used",
2778 data->BaseAddress, data->NumAddress);
2779 goto free_irq;
2780 }
2781
2782 ret = scsi_add_host(host, &pdev->dev);
2783 if (ret) {
2784 nsp32_msg(KERN_ERR, "failed to add scsi host");
2785 goto free_region;
2786 }
2787 scsi_scan_host(host);
2788 pci_set_drvdata(pdev, host);
2789 return 0;
2790
2791 free_region:
2792 release_region(host->io_port, host->n_io_port);
2793
2794 free_irq:
2795 free_irq(host->irq, data);
2796
2797 free_sg_list:
2798 pci_free_consistent(pdev, NSP32_SG_TABLE_SIZE,
2799 data->sg_list, data->sg_paddr);
2800
2801 free_autoparam:
2802 pci_free_consistent(pdev, sizeof(nsp32_autoparam),
2803 data->autoparam, data->auto_paddr);
2804
2805 scsi_unregister:
2806 scsi_host_put(host);
2807
2808 err:
2809 return 1;
2810}
2811
2812static int nsp32_release(struct Scsi_Host *host)
2813{
2814 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2815
2816 if (data->autoparam) {
2817 pci_free_consistent(data->Pci, sizeof(nsp32_autoparam),
2818 data->autoparam, data->auto_paddr);
2819 }
2820
2821 if (data->sg_list) {
2822 pci_free_consistent(data->Pci, NSP32_SG_TABLE_SIZE,
2823 data->sg_list, data->sg_paddr);
2824 }
2825
2826 if (host->irq) {
2827 free_irq(host->irq, data);
2828 }
2829
2830 if (host->io_port && host->n_io_port) {
2831 release_region(host->io_port, host->n_io_port);
2832 }
2833
2834 if (data->MmioAddress) {
2835 iounmap(data->MmioAddress);
2836 }
2837
2838 return 0;
2839}
2840
2841static const char *nsp32_info(struct Scsi_Host *shpnt)
2842{
2843 nsp32_hw_data *data = (nsp32_hw_data *)shpnt->hostdata;
2844
2845 return data->info_str;
2846}
2847
2848
2849
2850
2851
2852static int nsp32_eh_abort(struct scsi_cmnd *SCpnt)
2853{
2854 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2855 unsigned int base = SCpnt->device->host->io_port;
2856
2857 nsp32_msg(KERN_WARNING, "abort");
2858
2859 if (data->cur_lunt->SCpnt == NULL) {
2860 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort failed");
2861 return FAILED;
2862 }
2863
2864 if (data->cur_target->sync_flag & (SDTR_INITIATOR | SDTR_TARGET)) {
2865
2866 data->cur_target->sync_flag = 0;
2867 nsp32_set_async(data, data->cur_target);
2868 }
2869
2870 nsp32_write2(base, TRANSFER_CONTROL, 0);
2871 nsp32_write2(base, BM_CNT, 0);
2872
2873 SCpnt->result = DID_ABORT << 16;
2874 nsp32_scsi_done(SCpnt);
2875
2876 nsp32_dbg(NSP32_DEBUG_BUSRESET, "abort success");
2877 return SUCCESS;
2878}
2879
2880static int nsp32_eh_bus_reset(struct scsi_cmnd *SCpnt)
2881{
2882 nsp32_hw_data *data = (nsp32_hw_data *)SCpnt->device->host->hostdata;
2883 unsigned int base = SCpnt->device->host->io_port;
2884
2885 spin_lock_irq(SCpnt->device->host->host_lock);
2886
2887 nsp32_msg(KERN_INFO, "Bus Reset");
2888 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2889
2890 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2891 nsp32_do_bus_reset(data);
2892 nsp32_write2(base, IRQ_CONTROL, 0);
2893
2894 spin_unlock_irq(SCpnt->device->host->host_lock);
2895 return SUCCESS;
2896}
2897
2898static void nsp32_do_bus_reset(nsp32_hw_data *data)
2899{
2900 unsigned int base = data->BaseAddress;
2901 unsigned short intrdat;
2902 int i;
2903
2904 nsp32_dbg(NSP32_DEBUG_BUSRESET, "in");
2905
2906
2907
2908
2909
2910
2911 nsp32_write2(base, TRANSFER_CONTROL, 0);
2912 nsp32_write4(base, BM_CNT, 0);
2913 nsp32_write4(base, CLR_COUNTER, CLRCOUNTER_ALLMASK);
2914
2915
2916
2917
2918
2919 for (i = 0; i < ARRAY_SIZE(data->target); i++) {
2920 nsp32_target *target = &data->target[i];
2921
2922 target->sync_flag = 0;
2923 nsp32_set_async(data, target);
2924 }
2925
2926
2927
2928
2929 nsp32_write1(base, SCSI_BUS_CONTROL, BUSCTL_RST);
2930 udelay(RESET_HOLD_TIME);
2931 nsp32_write1(base, SCSI_BUS_CONTROL, 0);
2932 for(i = 0; i < 5; i++) {
2933 intrdat = nsp32_read2(base, IRQ_STATUS);
2934 nsp32_dbg(NSP32_DEBUG_BUSRESET, "irq:1: 0x%x", intrdat);
2935 }
2936
2937 data->CurrentSC = NULL;
2938}
2939
2940static int nsp32_eh_host_reset(struct scsi_cmnd *SCpnt)
2941{
2942 struct Scsi_Host *host = SCpnt->device->host;
2943 unsigned int base = SCpnt->device->host->io_port;
2944 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
2945
2946 nsp32_msg(KERN_INFO, "Host Reset");
2947 nsp32_dbg(NSP32_DEBUG_BUSRESET, "SCpnt=0x%x", SCpnt);
2948
2949 spin_lock_irq(SCpnt->device->host->host_lock);
2950
2951 nsp32hw_init(data);
2952 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK);
2953 nsp32_do_bus_reset(data);
2954 nsp32_write2(base, IRQ_CONTROL, 0);
2955
2956 spin_unlock_irq(SCpnt->device->host->host_lock);
2957 return SUCCESS;
2958}
2959
2960
2961
2962
2963
2964
2965
2966
2967
2968static int nsp32_getprom_param(nsp32_hw_data *data)
2969{
2970 int vendor = data->pci_devid->vendor;
2971 int device = data->pci_devid->device;
2972 int ret, val, i;
2973
2974
2975
2976
2977 ret = nsp32_prom_read(data, 0x7e);
2978 if (ret != 0x55) {
2979 nsp32_msg(KERN_INFO, "No EEPROM detected: 0x%x", ret);
2980 return FALSE;
2981 }
2982 ret = nsp32_prom_read(data, 0x7f);
2983 if (ret != 0xaa) {
2984 nsp32_msg(KERN_INFO, "Invalid number: 0x%x", ret);
2985 return FALSE;
2986 }
2987
2988
2989
2990
2991 if (vendor == PCI_VENDOR_ID_WORKBIT &&
2992 device == PCI_DEVICE_ID_WORKBIT_STANDARD) {
2993 ret = nsp32_getprom_c16(data);
2994 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2995 device == PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC) {
2996 ret = nsp32_getprom_at24(data);
2997 } else if (vendor == PCI_VENDOR_ID_WORKBIT &&
2998 device == PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO ) {
2999 ret = nsp32_getprom_at24(data);
3000 } else {
3001 nsp32_msg(KERN_WARNING, "Unknown EEPROM");
3002 ret = FALSE;
3003 }
3004
3005
3006 for (i = 0; i <= 0x1f; i++) {
3007 val = nsp32_prom_read(data, i);
3008 nsp32_dbg(NSP32_DEBUG_EEPROM,
3009 "rom address 0x%x : 0x%x", i, val);
3010 }
3011
3012 return ret;
3013}
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043static int nsp32_getprom_at24(nsp32_hw_data *data)
3044{
3045 int ret, i;
3046 int auto_sync;
3047 nsp32_target *target;
3048 int entry;
3049
3050
3051
3052
3053
3054
3055 data->resettime = nsp32_prom_read(data, 0x12);
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070 ret = nsp32_prom_read(data, 0x07);
3071 switch (ret) {
3072 case 0:
3073 auto_sync = TRUE;
3074 break;
3075 case 1:
3076 auto_sync = FALSE;
3077 break;
3078 default:
3079 nsp32_msg(KERN_WARNING,
3080 "Unsupported Auto Sync mode. Fall back to manual mode.");
3081 auto_sync = TRUE;
3082 }
3083
3084 if (trans_mode == ULTRA20M_MODE) {
3085 auto_sync = TRUE;
3086 }
3087
3088
3089
3090
3091 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3092 target = &data->target[i];
3093 if (auto_sync == TRUE) {
3094 target->limit_entry = 0;
3095 } else {
3096 ret = nsp32_prom_read(data, i);
3097 entry = nsp32_search_period_entry(data, target, ret);
3098 if (entry < 0) {
3099
3100 entry = 0;
3101 }
3102 target->limit_entry = entry;
3103 }
3104 }
3105
3106 return TRUE;
3107}
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130static int nsp32_getprom_c16(nsp32_hw_data *data)
3131{
3132 int ret, i;
3133 nsp32_target *target;
3134 int entry, val;
3135
3136
3137
3138
3139
3140
3141 data->resettime = nsp32_prom_read(data, 0x11);
3142
3143
3144
3145
3146 for (i = 0; i < NSP32_HOST_SCSIID; i++) {
3147 target = &data->target[i];
3148 ret = nsp32_prom_read(data, i);
3149 switch (ret) {
3150 case 0:
3151 val = 0x0c;
3152 break;
3153 case 1:
3154 val = 0x19;
3155 break;
3156 case 2:
3157 val = 0x32;
3158 break;
3159 case 3:
3160 val = 0x00;
3161 break;
3162 default:
3163 val = 0x0c;
3164 break;
3165 }
3166 entry = nsp32_search_period_entry(data, target, val);
3167 if (entry < 0 || trans_mode == ULTRA20M_MODE) {
3168
3169 entry = 0;
3170 }
3171 target->limit_entry = entry;
3172 }
3173
3174 return TRUE;
3175}
3176
3177
3178
3179
3180
3181static int nsp32_prom_read(nsp32_hw_data *data, int romaddr)
3182{
3183 int i, val;
3184
3185
3186 nsp32_prom_start(data);
3187
3188
3189 nsp32_prom_write_bit(data, 1);
3190 nsp32_prom_write_bit(data, 0);
3191 nsp32_prom_write_bit(data, 1);
3192 nsp32_prom_write_bit(data, 0);
3193 nsp32_prom_write_bit(data, 0);
3194 nsp32_prom_write_bit(data, 0);
3195 nsp32_prom_write_bit(data, 0);
3196
3197
3198 nsp32_prom_write_bit(data, 0);
3199
3200
3201 nsp32_prom_write_bit(data, 0);
3202
3203
3204 for (i = 7; i >= 0; i--) {
3205 nsp32_prom_write_bit(data, ((romaddr >> i) & 1));
3206 }
3207
3208
3209 nsp32_prom_write_bit(data, 0);
3210
3211
3212 nsp32_prom_start(data);
3213
3214
3215 nsp32_prom_write_bit(data, 1);
3216 nsp32_prom_write_bit(data, 0);
3217 nsp32_prom_write_bit(data, 1);
3218 nsp32_prom_write_bit(data, 0);
3219 nsp32_prom_write_bit(data, 0);
3220 nsp32_prom_write_bit(data, 0);
3221 nsp32_prom_write_bit(data, 0);
3222
3223
3224 nsp32_prom_write_bit(data, 1);
3225
3226
3227 nsp32_prom_write_bit(data, 0);
3228
3229
3230 val = 0;
3231 for (i = 7; i >= 0; i--) {
3232 val += (nsp32_prom_read_bit(data) << i);
3233 }
3234
3235
3236 nsp32_prom_write_bit(data, 1);
3237
3238
3239 nsp32_prom_stop(data);
3240
3241 return val;
3242}
3243
3244static void nsp32_prom_set(nsp32_hw_data *data, int bit, int val)
3245{
3246 int base = data->BaseAddress;
3247 int tmp;
3248
3249 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL);
3250
3251 if (val == 0) {
3252 tmp &= ~bit;
3253 } else {
3254 tmp |= bit;
3255 }
3256
3257 nsp32_index_write1(base, SERIAL_ROM_CTL, tmp);
3258
3259 udelay(10);
3260}
3261
3262static int nsp32_prom_get(nsp32_hw_data *data, int bit)
3263{
3264 int base = data->BaseAddress;
3265 int tmp, ret;
3266
3267 if (bit != SDA) {
3268 nsp32_msg(KERN_ERR, "return value is not appropriate");
3269 return 0;
3270 }
3271
3272
3273 tmp = nsp32_index_read1(base, SERIAL_ROM_CTL) & bit;
3274
3275 if (tmp == 0) {
3276 ret = 0;
3277 } else {
3278 ret = 1;
3279 }
3280
3281 udelay(10);
3282
3283 return ret;
3284}
3285
3286static void nsp32_prom_start (nsp32_hw_data *data)
3287{
3288
3289 nsp32_prom_set(data, SCL, 1);
3290 nsp32_prom_set(data, SDA, 1);
3291 nsp32_prom_set(data, ENA, 1);
3292 nsp32_prom_set(data, SDA, 0);
3293
3294 nsp32_prom_set(data, SCL, 0);
3295}
3296
3297static void nsp32_prom_stop (nsp32_hw_data *data)
3298{
3299
3300 nsp32_prom_set(data, SCL, 1);
3301 nsp32_prom_set(data, SDA, 0);
3302 nsp32_prom_set(data, ENA, 1);
3303 nsp32_prom_set(data, SDA, 1);
3304 nsp32_prom_set(data, SCL, 0);
3305}
3306
3307static void nsp32_prom_write_bit(nsp32_hw_data *data, int val)
3308{
3309
3310 nsp32_prom_set(data, SDA, val);
3311 nsp32_prom_set(data, SCL, 1 );
3312 nsp32_prom_set(data, SCL, 0 );
3313}
3314
3315static int nsp32_prom_read_bit(nsp32_hw_data *data)
3316{
3317 int val;
3318
3319
3320 nsp32_prom_set(data, ENA, 0);
3321 nsp32_prom_set(data, SCL, 1);
3322
3323 val = nsp32_prom_get(data, SDA);
3324
3325 nsp32_prom_set(data, SCL, 0);
3326 nsp32_prom_set(data, ENA, 1);
3327
3328 return val;
3329}
3330
3331
3332
3333
3334
3335#ifdef CONFIG_PM
3336
3337
3338static int nsp32_suspend(struct pci_dev *pdev, pm_message_t state)
3339{
3340 struct Scsi_Host *host = pci_get_drvdata(pdev);
3341
3342 nsp32_msg(KERN_INFO, "pci-suspend: pdev=0x%p, state=%ld, slot=%s, host=0x%p", pdev, state, pci_name(pdev), host);
3343
3344 pci_save_state (pdev);
3345 pci_disable_device (pdev);
3346 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3347
3348 return 0;
3349}
3350
3351
3352static int nsp32_resume(struct pci_dev *pdev)
3353{
3354 struct Scsi_Host *host = pci_get_drvdata(pdev);
3355 nsp32_hw_data *data = (nsp32_hw_data *)host->hostdata;
3356 unsigned short reg;
3357
3358 nsp32_msg(KERN_INFO, "pci-resume: pdev=0x%p, slot=%s, host=0x%p", pdev, pci_name(pdev), host);
3359
3360 pci_set_power_state(pdev, PCI_D0);
3361 pci_enable_wake (pdev, PCI_D0, 0);
3362 pci_restore_state (pdev);
3363
3364 reg = nsp32_read2(data->BaseAddress, INDEX_REG);
3365
3366 nsp32_msg(KERN_INFO, "io=0x%x reg=0x%x", data->BaseAddress, reg);
3367
3368 if (reg == 0xffff) {
3369 nsp32_msg(KERN_INFO, "missing device. abort resume.");
3370 return 0;
3371 }
3372
3373 nsp32hw_init (data);
3374 nsp32_do_bus_reset(data);
3375
3376 nsp32_msg(KERN_INFO, "resume success");
3377
3378 return 0;
3379}
3380
3381#endif
3382
3383
3384
3385
3386static int __devinit nsp32_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3387{
3388 int ret;
3389 nsp32_hw_data *data = &nsp32_data_base;
3390
3391 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3392
3393 ret = pci_enable_device(pdev);
3394 if (ret) {
3395 nsp32_msg(KERN_ERR, "failed to enable pci device");
3396 return ret;
3397 }
3398
3399 data->Pci = pdev;
3400 data->pci_devid = id;
3401 data->IrqNumber = pdev->irq;
3402 data->BaseAddress = pci_resource_start(pdev, 0);
3403 data->NumAddress = pci_resource_len (pdev, 0);
3404 data->MmioAddress = pci_ioremap_bar(pdev, 1);
3405 data->MmioLength = pci_resource_len (pdev, 1);
3406
3407 pci_set_master(pdev);
3408
3409 ret = nsp32_detect(pdev);
3410
3411 nsp32_msg(KERN_INFO, "irq: %i mmio: %p+0x%lx slot: %s model: %s",
3412 pdev->irq,
3413 data->MmioAddress, data->MmioLength,
3414 pci_name(pdev),
3415 nsp32_model[id->driver_data]);
3416
3417 nsp32_dbg(NSP32_DEBUG_REGISTER, "exit %d", ret);
3418
3419 return ret;
3420}
3421
3422static void __devexit nsp32_remove(struct pci_dev *pdev)
3423{
3424 struct Scsi_Host *host = pci_get_drvdata(pdev);
3425
3426 nsp32_dbg(NSP32_DEBUG_REGISTER, "enter");
3427
3428 scsi_remove_host(host);
3429
3430 nsp32_release(host);
3431
3432 scsi_host_put(host);
3433}
3434
3435static struct pci_driver nsp32_driver = {
3436 .name = "nsp32",
3437 .id_table = nsp32_pci_table,
3438 .probe = nsp32_probe,
3439 .remove = __devexit_p(nsp32_remove),
3440#ifdef CONFIG_PM
3441 .suspend = nsp32_suspend,
3442 .resume = nsp32_resume,
3443#endif
3444};
3445
3446
3447
3448
3449static int __init init_nsp32(void) {
3450 nsp32_msg(KERN_INFO, "loading...");
3451 return pci_register_driver(&nsp32_driver);
3452}
3453
3454static void __exit exit_nsp32(void) {
3455 nsp32_msg(KERN_INFO, "unloading...");
3456 pci_unregister_driver(&nsp32_driver);
3457}
3458
3459module_init(init_nsp32);
3460module_exit(exit_nsp32);
3461
3462
3463