1/* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2008 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8#include "qla_def.h" 9 10/* 11 * Driver debug definitions. 12 */ 13/* #define QL_DEBUG_LEVEL_1 */ /* Output register accesses to COM1 */ 14/* #define QL_DEBUG_LEVEL_2 */ /* Output error msgs to COM1 */ 15/* #define QL_DEBUG_LEVEL_3 */ /* Output function trace msgs to COM1 */ 16/* #define QL_DEBUG_LEVEL_4 */ /* Output NVRAM trace msgs to COM1 */ 17/* #define QL_DEBUG_LEVEL_5 */ /* Output ring trace msgs to COM1 */ 18/* #define QL_DEBUG_LEVEL_6 */ /* Output WATCHDOG timer trace to COM1 */ 19/* #define QL_DEBUG_LEVEL_7 */ /* Output RISC load trace msgs to COM1 */ 20/* #define QL_DEBUG_LEVEL_8 */ /* Output ring saturation msgs to COM1 */ 21/* #define QL_DEBUG_LEVEL_9 */ /* Output IOCTL trace msgs */ 22/* #define QL_DEBUG_LEVEL_10 */ /* Output IOCTL error msgs */ 23/* #define QL_DEBUG_LEVEL_11 */ /* Output Mbx Cmd trace msgs */ 24/* #define QL_DEBUG_LEVEL_12 */ /* Output IP trace msgs */ 25/* #define QL_DEBUG_LEVEL_13 */ /* Output fdmi function trace msgs */ 26/* #define QL_DEBUG_LEVEL_14 */ /* Output RSCN trace msgs */ 27/* #define QL_DEBUG_LEVEL_15 */ /* Output NPIV trace msgs */ 28/* #define QL_DEBUG_LEVEL_16 */ /* Output ISP84XX trace msgs */ 29/* #define QL_DEBUG_LEVEL_17 */ /* Output MULTI-Q trace messages */ 30 31/* 32* Macros use for debugging the driver. 33*/ 34 35#define DEBUG(x) do { if (ql2xextended_error_logging) { x; } } while (0) 36 37#if defined(QL_DEBUG_LEVEL_1) 38#define DEBUG1(x) do {x;} while (0) 39#else 40#define DEBUG1(x) do {} while (0) 41#endif 42 43#define DEBUG2(x) do { if (ql2xextended_error_logging) { x; } } while (0) 44#define DEBUG2_3(x) do { if (ql2xextended_error_logging) { x; } } while (0) 45#define DEBUG2_3_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) 46#define DEBUG2_9_10(x) do { if (ql2xextended_error_logging) { x; } } while (0) 47#define DEBUG2_11(x) do { if (ql2xextended_error_logging) { x; } } while (0) 48#define DEBUG2_13(x) do { if (ql2xextended_error_logging) { x; } } while (0) 49#define DEBUG2_16(x) do { if (ql2xextended_error_logging) { x; } } while (0) 50#define DEBUG2_17(x) do { if (ql2xextended_error_logging) { x; } } while (0) 51 52#if defined(QL_DEBUG_LEVEL_3) 53#define DEBUG3(x) do {x;} while (0) 54#define DEBUG3_11(x) do {x;} while (0) 55#else 56#define DEBUG3(x) do {} while (0) 57#endif 58 59#if defined(QL_DEBUG_LEVEL_4) 60#define DEBUG4(x) do {x;} while (0) 61#else 62#define DEBUG4(x) do {} while (0) 63#endif 64 65#if defined(QL_DEBUG_LEVEL_5) 66#define DEBUG5(x) do {x;} while (0) 67#else 68#define DEBUG5(x) do {} while (0) 69#endif 70 71#if defined(QL_DEBUG_LEVEL_7) 72#define DEBUG7(x) do {x;} while (0) 73#else 74#define DEBUG7(x) do {} while (0) 75#endif 76 77#if defined(QL_DEBUG_LEVEL_9) 78#define DEBUG9(x) do {x;} while (0) 79#define DEBUG9_10(x) do {x;} while (0) 80#else 81#define DEBUG9(x) do {} while (0) 82#endif 83 84#if defined(QL_DEBUG_LEVEL_10) 85#define DEBUG10(x) do {x;} while (0) 86#define DEBUG9_10(x) do {x;} while (0) 87#else 88#define DEBUG10(x) do {} while (0) 89 #if !defined(DEBUG9_10) 90 #define DEBUG9_10(x) do {} while (0) 91 #endif 92#endif 93 94#if defined(QL_DEBUG_LEVEL_11) 95#define DEBUG11(x) do{x;} while(0) 96#if !defined(DEBUG3_11) 97#define DEBUG3_11(x) do{x;} while(0) 98#endif 99#else 100#define DEBUG11(x) do{} while(0) 101 #if !defined(QL_DEBUG_LEVEL_3) 102 #define DEBUG3_11(x) do{} while(0) 103 #endif 104#endif 105 106#if defined(QL_DEBUG_LEVEL_12) 107#define DEBUG12(x) do {x;} while (0) 108#else 109#define DEBUG12(x) do {} while (0) 110#endif 111 112#if defined(QL_DEBUG_LEVEL_13) 113#define DEBUG13(x) do {x;} while (0) 114#else 115#define DEBUG13(x) do {} while (0) 116#endif 117 118#if defined(QL_DEBUG_LEVEL_14) 119#define DEBUG14(x) do {x;} while (0) 120#else 121#define DEBUG14(x) do {} while (0) 122#endif 123 124#if defined(QL_DEBUG_LEVEL_15) 125#define DEBUG15(x) do {x;} while (0) 126#else 127#define DEBUG15(x) do {} while (0) 128#endif 129 130#if defined(QL_DEBUG_LEVEL_16) 131#define DEBUG16(x) do {x;} while (0) 132#else 133#define DEBUG16(x) do {} while (0) 134#endif 135/* 136 * Firmware Dump structure definition 137 */ 138 139struct qla2300_fw_dump { 140 uint16_t hccr; 141 uint16_t pbiu_reg[8]; 142 uint16_t risc_host_reg[8]; 143 uint16_t mailbox_reg[32]; 144 uint16_t resp_dma_reg[32]; 145 uint16_t dma_reg[48]; 146 uint16_t risc_hdw_reg[16]; 147 uint16_t risc_gp0_reg[16]; 148 uint16_t risc_gp1_reg[16]; 149 uint16_t risc_gp2_reg[16]; 150 uint16_t risc_gp3_reg[16]; 151 uint16_t risc_gp4_reg[16]; 152 uint16_t risc_gp5_reg[16]; 153 uint16_t risc_gp6_reg[16]; 154 uint16_t risc_gp7_reg[16]; 155 uint16_t frame_buf_hdw_reg[64]; 156 uint16_t fpm_b0_reg[64]; 157 uint16_t fpm_b1_reg[64]; 158 uint16_t risc_ram[0xf800]; 159 uint16_t stack_ram[0x1000]; 160 uint16_t data_ram[1]; 161}; 162 163struct qla2100_fw_dump { 164 uint16_t hccr; 165 uint16_t pbiu_reg[8]; 166 uint16_t mailbox_reg[32]; 167 uint16_t dma_reg[48]; 168 uint16_t risc_hdw_reg[16]; 169 uint16_t risc_gp0_reg[16]; 170 uint16_t risc_gp1_reg[16]; 171 uint16_t risc_gp2_reg[16]; 172 uint16_t risc_gp3_reg[16]; 173 uint16_t risc_gp4_reg[16]; 174 uint16_t risc_gp5_reg[16]; 175 uint16_t risc_gp6_reg[16]; 176 uint16_t risc_gp7_reg[16]; 177 uint16_t frame_buf_hdw_reg[16]; 178 uint16_t fpm_b0_reg[64]; 179 uint16_t fpm_b1_reg[64]; 180 uint16_t risc_ram[0xf000]; 181}; 182 183struct qla24xx_fw_dump { 184 uint32_t host_status; 185 uint32_t host_reg[32]; 186 uint32_t shadow_reg[7]; 187 uint16_t mailbox_reg[32]; 188 uint32_t xseq_gp_reg[128]; 189 uint32_t xseq_0_reg[16]; 190 uint32_t xseq_1_reg[16]; 191 uint32_t rseq_gp_reg[128]; 192 uint32_t rseq_0_reg[16]; 193 uint32_t rseq_1_reg[16]; 194 uint32_t rseq_2_reg[16]; 195 uint32_t cmd_dma_reg[16]; 196 uint32_t req0_dma_reg[15]; 197 uint32_t resp0_dma_reg[15]; 198 uint32_t req1_dma_reg[15]; 199 uint32_t xmt0_dma_reg[32]; 200 uint32_t xmt1_dma_reg[32]; 201 uint32_t xmt2_dma_reg[32]; 202 uint32_t xmt3_dma_reg[32]; 203 uint32_t xmt4_dma_reg[32]; 204 uint32_t xmt_data_dma_reg[16]; 205 uint32_t rcvt0_data_dma_reg[32]; 206 uint32_t rcvt1_data_dma_reg[32]; 207 uint32_t risc_gp_reg[128]; 208 uint32_t lmc_reg[112]; 209 uint32_t fpm_hdw_reg[192]; 210 uint32_t fb_hdw_reg[176]; 211 uint32_t code_ram[0x2000]; 212 uint32_t ext_mem[1]; 213}; 214 215struct qla25xx_fw_dump { 216 uint32_t host_status; 217 uint32_t host_risc_reg[32]; 218 uint32_t pcie_regs[4]; 219 uint32_t host_reg[32]; 220 uint32_t shadow_reg[11]; 221 uint32_t risc_io_reg; 222 uint16_t mailbox_reg[32]; 223 uint32_t xseq_gp_reg[128]; 224 uint32_t xseq_0_reg[48]; 225 uint32_t xseq_1_reg[16]; 226 uint32_t rseq_gp_reg[128]; 227 uint32_t rseq_0_reg[32]; 228 uint32_t rseq_1_reg[16]; 229 uint32_t rseq_2_reg[16]; 230 uint32_t aseq_gp_reg[128]; 231 uint32_t aseq_0_reg[32]; 232 uint32_t aseq_1_reg[16]; 233 uint32_t aseq_2_reg[16]; 234 uint32_t cmd_dma_reg[16]; 235 uint32_t req0_dma_reg[15]; 236 uint32_t resp0_dma_reg[15]; 237 uint32_t req1_dma_reg[15]; 238 uint32_t xmt0_dma_reg[32]; 239 uint32_t xmt1_dma_reg[32]; 240 uint32_t xmt2_dma_reg[32]; 241 uint32_t xmt3_dma_reg[32]; 242 uint32_t xmt4_dma_reg[32]; 243 uint32_t xmt_data_dma_reg[16]; 244 uint32_t rcvt0_data_dma_reg[32]; 245 uint32_t rcvt1_data_dma_reg[32]; 246 uint32_t risc_gp_reg[128]; 247 uint32_t lmc_reg[128]; 248 uint32_t fpm_hdw_reg[192]; 249 uint32_t fb_hdw_reg[192]; 250 uint32_t code_ram[0x2000]; 251 uint32_t ext_mem[1]; 252}; 253 254struct qla81xx_fw_dump { 255 uint32_t host_status; 256 uint32_t host_risc_reg[32]; 257 uint32_t pcie_regs[4]; 258 uint32_t host_reg[32]; 259 uint32_t shadow_reg[11]; 260 uint32_t risc_io_reg; 261 uint16_t mailbox_reg[32]; 262 uint32_t xseq_gp_reg[128]; 263 uint32_t xseq_0_reg[48]; 264 uint32_t xseq_1_reg[16]; 265 uint32_t rseq_gp_reg[128]; 266 uint32_t rseq_0_reg[32]; 267 uint32_t rseq_1_reg[16]; 268 uint32_t rseq_2_reg[16]; 269 uint32_t aseq_gp_reg[128]; 270 uint32_t aseq_0_reg[32]; 271 uint32_t aseq_1_reg[16]; 272 uint32_t aseq_2_reg[16]; 273 uint32_t cmd_dma_reg[16]; 274 uint32_t req0_dma_reg[15]; 275 uint32_t resp0_dma_reg[15]; 276 uint32_t req1_dma_reg[15]; 277 uint32_t xmt0_dma_reg[32]; 278 uint32_t xmt1_dma_reg[32]; 279 uint32_t xmt2_dma_reg[32]; 280 uint32_t xmt3_dma_reg[32]; 281 uint32_t xmt4_dma_reg[32]; 282 uint32_t xmt_data_dma_reg[16]; 283 uint32_t rcvt0_data_dma_reg[32]; 284 uint32_t rcvt1_data_dma_reg[32]; 285 uint32_t risc_gp_reg[128]; 286 uint32_t lmc_reg[128]; 287 uint32_t fpm_hdw_reg[224]; 288 uint32_t fb_hdw_reg[208]; 289 uint32_t code_ram[0x2000]; 290 uint32_t ext_mem[1]; 291}; 292 293#define EFT_NUM_BUFFERS 4 294#define EFT_BYTES_PER_BUFFER 0x4000 295#define EFT_SIZE ((EFT_BYTES_PER_BUFFER) * (EFT_NUM_BUFFERS)) 296 297#define FCE_NUM_BUFFERS 64 298#define FCE_BYTES_PER_BUFFER 0x400 299#define FCE_SIZE ((FCE_BYTES_PER_BUFFER) * (FCE_NUM_BUFFERS)) 300#define fce_calc_size(b) ((FCE_BYTES_PER_BUFFER) * (b)) 301 302struct qla2xxx_fce_chain { 303 uint32_t type; 304 uint32_t chain_size; 305 306 uint32_t size; 307 uint32_t addr_l; 308 uint32_t addr_h; 309 uint32_t eregs[8]; 310}; 311 312struct qla2xxx_mq_chain { 313 uint32_t type; 314 uint32_t chain_size; 315 316 uint32_t count; 317 uint32_t qregs[4 * QLA_MQ_SIZE]; 318}; 319 320#define DUMP_CHAIN_VARIANT 0x80000000 321#define DUMP_CHAIN_FCE 0x7FFFFAF0 322#define DUMP_CHAIN_MQ 0x7FFFFAF1 323#define DUMP_CHAIN_LAST 0x80000000 324 325struct qla2xxx_fw_dump { 326 uint8_t signature[4]; 327 uint32_t version; 328 329 uint32_t fw_major_version; 330 uint32_t fw_minor_version; 331 uint32_t fw_subminor_version; 332 uint32_t fw_attributes; 333 334 uint32_t vendor; 335 uint32_t device; 336 uint32_t subsystem_vendor; 337 uint32_t subsystem_device; 338 339 uint32_t fixed_size; 340 uint32_t mem_size; 341 uint32_t req_q_size; 342 uint32_t rsp_q_size; 343 344 uint32_t eft_size; 345 uint32_t eft_addr_l; 346 uint32_t eft_addr_h; 347 348 uint32_t header_size; 349 350 union { 351 struct qla2100_fw_dump isp21; 352 struct qla2300_fw_dump isp23; 353 struct qla24xx_fw_dump isp24; 354 struct qla25xx_fw_dump isp25; 355 struct qla81xx_fw_dump isp81; 356 } isp; 357}; 358