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6
7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
23#include <linux/interrupt.h>
24#include <linux/workqueue.h>
25#include <linux/firmware.h>
26#include <linux/aer.h>
27#include <linux/mutex.h>
28
29#include <scsi/scsi.h>
30#include <scsi/scsi_host.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_transport_fc.h>
34
35#define QLA2XXX_DRIVER_NAME "qla2xxx"
36
37
38
39
40
41
42#define MAILBOX_REGISTER_COUNT_2100 8
43#define MAILBOX_REGISTER_COUNT 32
44
45#define QLA2200A_RISC_ROM_VER 4
46#define FPM_2300 6
47#define FPM_2310 7
48
49#include "qla_settings.h"
50
51
52
53
54#define BIT_0 0x1
55#define BIT_1 0x2
56#define BIT_2 0x4
57#define BIT_3 0x8
58#define BIT_4 0x10
59#define BIT_5 0x20
60#define BIT_6 0x40
61#define BIT_7 0x80
62#define BIT_8 0x100
63#define BIT_9 0x200
64#define BIT_10 0x400
65#define BIT_11 0x800
66#define BIT_12 0x1000
67#define BIT_13 0x2000
68#define BIT_14 0x4000
69#define BIT_15 0x8000
70#define BIT_16 0x10000
71#define BIT_17 0x20000
72#define BIT_18 0x40000
73#define BIT_19 0x80000
74#define BIT_20 0x100000
75#define BIT_21 0x200000
76#define BIT_22 0x400000
77#define BIT_23 0x800000
78#define BIT_24 0x1000000
79#define BIT_25 0x2000000
80#define BIT_26 0x4000000
81#define BIT_27 0x8000000
82#define BIT_28 0x10000000
83#define BIT_29 0x20000000
84#define BIT_30 0x40000000
85#define BIT_31 0x80000000
86
87#define LSB(x) ((uint8_t)(x))
88#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
89
90#define LSW(x) ((uint16_t)(x))
91#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
92
93#define LSD(x) ((uint32_t)((uint64_t)(x)))
94#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
95
96#define MAKE_HANDLE(x, y) ((uint32_t)((((uint32_t)(x)) << 16) | (uint32_t)(y)))
97
98
99
100
101
102#define RD_REG_BYTE(addr) readb(addr)
103#define RD_REG_WORD(addr) readw(addr)
104#define RD_REG_DWORD(addr) readl(addr)
105#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
106#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
107#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
108#define WRT_REG_BYTE(addr, data) writeb(data,addr)
109#define WRT_REG_WORD(addr, data) writew(data,addr)
110#define WRT_REG_DWORD(addr, data) writel(data,addr)
111
112
113
114
115
116#define RD_REG_WORD_PIO(addr) (inw((unsigned long)addr))
117#define WRT_REG_WORD_PIO(addr, data) (outw(data,(unsigned long)addr))
118
119
120
121
122#define WWN_SIZE 8
123#define MAX_FIBRE_DEVICES 512
124#define MAX_FIBRE_LUNS 0xFFFF
125#define MAX_RSCN_COUNT 32
126#define MAX_HOST_COUNT 16
127
128
129
130
131#define MAX_BUSES 1
132#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
133#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
134#define MIN_LUNS 8
135#define MAX_LUNS MAX_FIBRE_LUNS
136#define MAX_CMDS_PER_LUN 255
137
138
139
140
141#define SNS_LAST_LOOP_ID_2100 0xfe
142#define SNS_LAST_LOOP_ID_2300 0x7ff
143
144#define LAST_LOCAL_LOOP_ID 0x7d
145#define SNS_FL_PORT 0x7e
146#define FABRIC_CONTROLLER 0x7f
147#define SIMPLE_NAME_SERVER 0x80
148#define SNS_FIRST_LOOP_ID 0x81
149#define MANAGEMENT_SERVER 0xfe
150#define BROADCAST 0xff
151
152
153
154
155
156#define NPH_LAST_HANDLE 0x7ef
157#define NPH_MGMT_SERVER 0x7fa
158#define NPH_SNS 0x7fc
159#define NPH_FABRIC_CONTROLLER 0x7fd
160#define NPH_F_PORT 0x7fe
161#define NPH_IP_BROADCAST 0x7ff
162
163#define MAX_CMDSZ 16
164#include "qla_fw.h"
165
166
167
168
169#define PORT_RETRY_TIME 1
170#define LOOP_DOWN_TIMEOUT 60
171#define LOOP_DOWN_TIME 255
172#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
173
174
175#define MAX_OUTSTANDING_COMMANDS 1024
176
177
178#define REQUEST_ENTRY_CNT_2100 128
179#define REQUEST_ENTRY_CNT_2200 2048
180#define REQUEST_ENTRY_CNT_24XX 2048
181#define RESPONSE_ENTRY_CNT_2100 64
182#define RESPONSE_ENTRY_CNT_2300 512
183#define RESPONSE_ENTRY_CNT_MQ 128
184
185struct req_que;
186
187
188
189
190typedef struct srb {
191 struct fc_port *fcport;
192 uint32_t handle;
193
194 struct scsi_cmnd *cmd;
195
196 uint16_t flags;
197
198 uint32_t request_sense_length;
199 uint8_t *request_sense_ptr;
200
201 void *ctx;
202} srb_t;
203
204
205
206
207#define SRB_DMA_VALID BIT_0
208
209
210
211
212struct srb_ctx {
213#define SRB_LOGIN_CMD 1
214#define SRB_LOGOUT_CMD 2
215 uint16_t type;
216 struct timer_list timer;
217
218 void (*free)(srb_t *sp);
219 void (*timeout)(srb_t *sp);
220};
221
222struct srb_logio {
223 struct srb_ctx ctx;
224
225#define SRB_LOGIN_RETRIED BIT_0
226#define SRB_LOGIN_COND_PLOGI BIT_1
227#define SRB_LOGIN_SKIP_PRLI BIT_2
228 uint16_t flags;
229};
230
231
232
233
234struct device_reg_2xxx {
235 uint16_t flash_address;
236 uint16_t flash_data;
237 uint16_t unused_1[1];
238 uint16_t ctrl_status;
239#define CSR_FLASH_64K_BANK BIT_3
240#define CSR_FLASH_ENABLE BIT_1
241#define CSR_ISP_SOFT_RESET BIT_0
242
243 uint16_t ictrl;
244#define ICR_EN_INT BIT_15
245#define ICR_EN_RISC BIT_3
246
247 uint16_t istatus;
248#define ISR_RISC_INT BIT_3
249
250 uint16_t semaphore;
251 uint16_t nvram;
252#define NVR_DESELECT 0
253#define NVR_BUSY BIT_15
254#define NVR_WRT_ENABLE BIT_14
255#define NVR_PR_ENABLE BIT_13
256#define NVR_DATA_IN BIT_3
257#define NVR_DATA_OUT BIT_2
258#define NVR_SELECT BIT_1
259#define NVR_CLOCK BIT_0
260
261#define NVR_WAIT_CNT 20000
262
263 union {
264 struct {
265 uint16_t mailbox0;
266 uint16_t mailbox1;
267 uint16_t mailbox2;
268 uint16_t mailbox3;
269 uint16_t mailbox4;
270 uint16_t mailbox5;
271 uint16_t mailbox6;
272 uint16_t mailbox7;
273 uint16_t unused_2[59];
274 } __attribute__((packed)) isp2100;
275 struct {
276
277 uint16_t req_q_in;
278 uint16_t req_q_out;
279
280 uint16_t rsp_q_in;
281 uint16_t rsp_q_out;
282
283
284 uint32_t host_status;
285#define HSR_RISC_INT BIT_15
286#define HSR_RISC_PAUSED BIT_8
287
288
289 uint16_t host_semaphore;
290 uint16_t unused_3[17];
291 uint16_t mailbox0;
292 uint16_t mailbox1;
293 uint16_t mailbox2;
294 uint16_t mailbox3;
295 uint16_t mailbox4;
296 uint16_t mailbox5;
297 uint16_t mailbox6;
298 uint16_t mailbox7;
299 uint16_t mailbox8;
300 uint16_t mailbox9;
301 uint16_t mailbox10;
302 uint16_t mailbox11;
303 uint16_t mailbox12;
304 uint16_t mailbox13;
305 uint16_t mailbox14;
306 uint16_t mailbox15;
307 uint16_t mailbox16;
308 uint16_t mailbox17;
309 uint16_t mailbox18;
310 uint16_t mailbox19;
311 uint16_t mailbox20;
312 uint16_t mailbox21;
313 uint16_t mailbox22;
314 uint16_t mailbox23;
315 uint16_t mailbox24;
316 uint16_t mailbox25;
317 uint16_t mailbox26;
318 uint16_t mailbox27;
319 uint16_t mailbox28;
320 uint16_t mailbox29;
321 uint16_t mailbox30;
322 uint16_t mailbox31;
323 uint16_t fb_cmd;
324 uint16_t unused_4[10];
325 } __attribute__((packed)) isp2300;
326 } u;
327
328 uint16_t fpm_diag_config;
329 uint16_t unused_5[0x4];
330 uint16_t risc_hw;
331 uint16_t unused_5_1;
332 uint16_t pcr;
333 uint16_t unused_6[0x5];
334 uint16_t mctr;
335 uint16_t unused_7[0x3];
336 uint16_t fb_cmd_2100;
337 uint16_t unused_8[0x3];
338 uint16_t hccr;
339#define HCCR_HOST_INT BIT_7
340#define HCCR_RISC_PAUSE BIT_5
341
342#define HCCR_RESET_RISC 0x1000
343#define HCCR_PAUSE_RISC 0x2000
344#define HCCR_RELEASE_RISC 0x3000
345#define HCCR_SET_HOST_INT 0x5000
346#define HCCR_CLR_HOST_INT 0x6000
347#define HCCR_CLR_RISC_INT 0x7000
348#define HCCR_DISABLE_PARITY_PAUSE 0x4001
349#define HCCR_ENABLE_PARITY 0xA000
350
351 uint16_t unused_9[5];
352 uint16_t gpiod;
353 uint16_t gpioe;
354#define GPIO_LED_MASK 0x00C0
355#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
356#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
357#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
358#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
359#define GPIO_LED_ALL_OFF 0x0000
360#define GPIO_LED_RED_ON_OTHER_OFF 0x0001
361#define GPIO_LED_RGA_ON 0x00C1
362
363 union {
364 struct {
365 uint16_t unused_10[8];
366 uint16_t mailbox8;
367 uint16_t mailbox9;
368 uint16_t mailbox10;
369 uint16_t mailbox11;
370 uint16_t mailbox12;
371 uint16_t mailbox13;
372 uint16_t mailbox14;
373 uint16_t mailbox15;
374 uint16_t mailbox16;
375 uint16_t mailbox17;
376 uint16_t mailbox18;
377 uint16_t mailbox19;
378 uint16_t mailbox20;
379 uint16_t mailbox21;
380 uint16_t mailbox22;
381 uint16_t mailbox23;
382 } __attribute__((packed)) isp2200;
383 } u_end;
384};
385
386struct device_reg_25xxmq {
387 uint32_t req_q_in;
388 uint32_t req_q_out;
389 uint32_t rsp_q_in;
390 uint32_t rsp_q_out;
391};
392
393typedef union {
394 struct device_reg_2xxx isp;
395 struct device_reg_24xx isp24;
396 struct device_reg_25xxmq isp25mq;
397} device_reg_t;
398
399#define ISP_REQ_Q_IN(ha, reg) \
400 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
401 &(reg)->u.isp2100.mailbox4 : \
402 &(reg)->u.isp2300.req_q_in)
403#define ISP_REQ_Q_OUT(ha, reg) \
404 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
405 &(reg)->u.isp2100.mailbox4 : \
406 &(reg)->u.isp2300.req_q_out)
407#define ISP_RSP_Q_IN(ha, reg) \
408 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
409 &(reg)->u.isp2100.mailbox5 : \
410 &(reg)->u.isp2300.rsp_q_in)
411#define ISP_RSP_Q_OUT(ha, reg) \
412 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
413 &(reg)->u.isp2100.mailbox5 : \
414 &(reg)->u.isp2300.rsp_q_out)
415
416#define MAILBOX_REG(ha, reg, num) \
417 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
418 (num < 8 ? \
419 &(reg)->u.isp2100.mailbox0 + (num) : \
420 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
421 &(reg)->u.isp2300.mailbox0 + (num))
422#define RD_MAILBOX_REG(ha, reg, num) \
423 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
424#define WRT_MAILBOX_REG(ha, reg, num, data) \
425 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
426
427#define FB_CMD_REG(ha, reg) \
428 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
429 &(reg)->fb_cmd_2100 : \
430 &(reg)->u.isp2300.fb_cmd)
431#define RD_FB_CMD_REG(ha, reg) \
432 RD_REG_WORD(FB_CMD_REG(ha, reg))
433#define WRT_FB_CMD_REG(ha, reg, data) \
434 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
435
436typedef struct {
437 uint32_t out_mb;
438 uint32_t in_mb;
439 uint16_t mb[MAILBOX_REGISTER_COUNT];
440 long buf_size;
441 void *bufp;
442 uint32_t tov;
443 uint8_t flags;
444#define MBX_DMA_IN BIT_0
445#define MBX_DMA_OUT BIT_1
446#define IOCTL_CMD BIT_2
447} mbx_cmd_t;
448
449#define MBX_TOV_SECONDS 30
450
451
452
453
454#define PROD_ID_1 0x4953
455#define PROD_ID_2 0x0000
456#define PROD_ID_2a 0x5020
457#define PROD_ID_3 0x2020
458
459
460
461
462#define MBS_FRM_ALIVE 0
463#define MBS_CHKSUM_ERR 1
464#define MBS_BUSY 4
465
466
467
468
469#define MBS_COMMAND_COMPLETE 0x4000
470#define MBS_INVALID_COMMAND 0x4001
471#define MBS_HOST_INTERFACE_ERROR 0x4002
472#define MBS_TEST_FAILED 0x4003
473#define MBS_COMMAND_ERROR 0x4005
474#define MBS_COMMAND_PARAMETER_ERROR 0x4006
475#define MBS_PORT_ID_USED 0x4007
476#define MBS_LOOP_ID_USED 0x4008
477#define MBS_ALL_IDS_IN_USE 0x4009
478#define MBS_NOT_LOGGED_IN 0x400A
479#define MBS_LINK_DOWN_ERROR 0x400B
480#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
481
482
483
484
485#define MBA_ASYNC_EVENT 0x8000
486#define MBA_RESET 0x8001
487#define MBA_SYSTEM_ERR 0x8002
488#define MBA_REQ_TRANSFER_ERR 0x8003
489#define MBA_RSP_TRANSFER_ERR 0x8004
490#define MBA_WAKEUP_THRES 0x8005
491#define MBA_LIP_OCCURRED 0x8010
492
493#define MBA_LOOP_UP 0x8011
494#define MBA_LOOP_DOWN 0x8012
495#define MBA_LIP_RESET 0x8013
496#define MBA_PORT_UPDATE 0x8014
497#define MBA_RSCN_UPDATE 0x8015
498#define MBA_LIP_F8 0x8016
499#define MBA_LOOP_INIT_ERR 0x8017
500#define MBA_FABRIC_AUTH_REQ 0x801b
501#define MBA_SCSI_COMPLETION 0x8020
502#define MBA_CTIO_COMPLETION 0x8021
503#define MBA_IP_COMPLETION 0x8022
504#define MBA_IP_RECEIVE 0x8023
505#define MBA_IP_BROADCAST 0x8024
506#define MBA_IP_LOW_WATER_MARK 0x8025
507#define MBA_IP_RCV_BUFFER_EMPTY 0x8026
508#define MBA_IP_HDR_DATA_SPLIT 0x8027
509
510#define MBA_TRACE_NOTIFICATION 0x8028
511#define MBA_POINT_TO_POINT 0x8030
512#define MBA_CMPLT_1_16BIT 0x8031
513#define MBA_CMPLT_2_16BIT 0x8032
514#define MBA_CMPLT_3_16BIT 0x8033
515#define MBA_CMPLT_4_16BIT 0x8034
516#define MBA_CMPLT_5_16BIT 0x8035
517#define MBA_CHG_IN_CONNECTION 0x8036
518#define MBA_RIO_RESPONSE 0x8040
519#define MBA_ZIO_RESPONSE 0x8040
520#define MBA_CMPLT_2_32BIT 0x8042
521#define MBA_BYPASS_NOTIFICATION 0x8043
522#define MBA_DISCARD_RND_FRAME 0x8048
523#define MBA_REJECTED_FCP_CMD 0x8049
524
525
526
527
528#define FO1_AE_ON_LIPF8 BIT_0
529#define FO1_AE_ALL_LIP_RESET BIT_1
530#define FO1_CTIO_RETRY BIT_3
531#define FO1_DISABLE_LIP_F7_SW BIT_4
532#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
533#define FO1_DISABLE_GPIO6_7 BIT_6
534#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
535#define FO1_SET_EMPHASIS_SWING BIT_8
536#define FO1_AE_AUTO_BYPASS BIT_9
537#define FO1_ENABLE_PURE_IOCB BIT_10
538#define FO1_AE_PLOGI_RJT BIT_11
539#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
540#define FO1_AE_QUEUE_FULL BIT_13
541
542#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
543#define FO2_REV_LOOPBACK BIT_1
544
545#define FO3_ENABLE_EMERG_IOCB BIT_0
546#define FO3_AE_RND_ERROR BIT_1
547
548
549#define ADD_FO_COUNT 3
550#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6
551#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
552
553#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
554
555#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
556
557
558
559
560#define MBC_LOAD_RAM 1
561#define MBC_EXECUTE_FIRMWARE 2
562#define MBC_WRITE_RAM_WORD 4
563#define MBC_READ_RAM_WORD 5
564#define MBC_MAILBOX_REGISTER_TEST 6
565#define MBC_VERIFY_CHECKSUM 7
566#define MBC_GET_FIRMWARE_VERSION 8
567#define MBC_LOAD_RISC_RAM 9
568#define MBC_DUMP_RISC_RAM 0xa
569#define MBC_LOAD_RISC_RAM_EXTENDED 0xb
570#define MBC_DUMP_RISC_RAM_EXTENDED 0xc
571#define MBC_WRITE_RAM_WORD_EXTENDED 0xd
572#define MBC_READ_RAM_EXTENDED 0xf
573#define MBC_IOCB_COMMAND 0x12
574#define MBC_STOP_FIRMWARE 0x14
575#define MBC_ABORT_COMMAND 0x15
576#define MBC_ABORT_DEVICE 0x16
577#define MBC_ABORT_TARGET 0x17
578#define MBC_RESET 0x18
579#define MBC_GET_ADAPTER_LOOP_ID 0x20
580#define MBC_GET_RETRY_COUNT 0x22
581#define MBC_DISABLE_VI 0x24
582#define MBC_ENABLE_VI 0x25
583#define MBC_GET_FIRMWARE_OPTION 0x28
584#define MBC_SET_FIRMWARE_OPTION 0x38
585#define MBC_LOOP_PORT_BYPASS 0x40
586#define MBC_LOOP_PORT_ENABLE 0x41
587#define MBC_GET_RESOURCE_COUNTS 0x42
588#define MBC_NON_PARTICIPATE 0x43
589#define MBC_DIAGNOSTIC_ECHO 0x44
590#define MBC_DIAGNOSTIC_LOOP_BACK 0x45
591#define MBC_ONLINE_SELF_TEST 0x46
592#define MBC_ENHANCED_GET_PORT_DATABASE 0x47
593#define MBC_RESET_LINK_STATUS 0x52
594#define MBC_IOCB_COMMAND_A64 0x54
595#define MBC_SEND_RNID_ELS 0x57
596#define MBC_SET_RNID_PARAMS 0x59
597#define MBC_GET_RNID_PARAMS 0x5a
598#define MBC_DATA_RATE 0x5d
599#define MBC_INITIALIZE_FIRMWARE 0x60
600#define MBC_INITIATE_LIP 0x62
601
602#define MBC_GET_FC_AL_POSITION_MAP 0x63
603#define MBC_GET_PORT_DATABASE 0x64
604#define MBC_CLEAR_ACA 0x65
605#define MBC_TARGET_RESET 0x66
606#define MBC_CLEAR_TASK_SET 0x67
607#define MBC_ABORT_TASK_SET 0x68
608#define MBC_GET_FIRMWARE_STATE 0x69
609#define MBC_GET_PORT_NAME 0x6a
610#define MBC_GET_LINK_STATUS 0x6b
611#define MBC_LIP_RESET 0x6c
612#define MBC_SEND_SNS_COMMAND 0x6e
613
614#define MBC_LOGIN_FABRIC_PORT 0x6f
615#define MBC_SEND_CHANGE_REQUEST 0x70
616#define MBC_LOGOUT_FABRIC_PORT 0x71
617#define MBC_LIP_FULL_LOGIN 0x72
618#define MBC_LOGIN_LOOP_PORT 0x74
619#define MBC_PORT_NODE_NAME_LIST 0x75
620#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77
621#define MBC_UNLOAD_IP 0x79
622#define MBC_GET_ID_LIST 0x7C
623#define MBC_SEND_LFA_COMMAND 0x7D
624#define MBC_LUN_RESET 0x7E
625
626
627
628
629#define MBC_SERDES_PARAMS 0x10
630#define MBC_GET_IOCB_STATUS 0x12
631#define MBC_PORT_PARAMS 0x1A
632#define MBC_GET_TIMEOUT_PARAMS 0x22
633#define MBC_TRACE_CONTROL 0x27
634#define MBC_GEN_SYSTEM_ERROR 0x2a
635#define MBC_WRITE_SFP 0x30
636#define MBC_READ_SFP 0x31
637#define MBC_SET_TIMEOUT_PARAMS 0x32
638#define MBC_MID_INITIALIZE_FIRMWARE 0x48
639#define MBC_MID_GET_VP_DATABASE 0x49
640#define MBC_MID_GET_VP_ENTRY 0x4a
641#define MBC_HOST_MEMORY_COPY 0x53
642#define MBC_SEND_RNFT_ELS 0x5e
643#define MBC_GET_LINK_PRIV_STATS 0x6d
644#define MBC_SET_VENDOR_ID 0x76
645
646
647#define FCAL_MAP_SIZE 128
648
649
650#define MBX_31 BIT_31
651#define MBX_30 BIT_30
652#define MBX_29 BIT_29
653#define MBX_28 BIT_28
654#define MBX_27 BIT_27
655#define MBX_26 BIT_26
656#define MBX_25 BIT_25
657#define MBX_24 BIT_24
658#define MBX_23 BIT_23
659#define MBX_22 BIT_22
660#define MBX_21 BIT_21
661#define MBX_20 BIT_20
662#define MBX_19 BIT_19
663#define MBX_18 BIT_18
664#define MBX_17 BIT_17
665#define MBX_16 BIT_16
666#define MBX_15 BIT_15
667#define MBX_14 BIT_14
668#define MBX_13 BIT_13
669#define MBX_12 BIT_12
670#define MBX_11 BIT_11
671#define MBX_10 BIT_10
672#define MBX_9 BIT_9
673#define MBX_8 BIT_8
674#define MBX_7 BIT_7
675#define MBX_6 BIT_6
676#define MBX_5 BIT_5
677#define MBX_4 BIT_4
678#define MBX_3 BIT_3
679#define MBX_2 BIT_2
680#define MBX_1 BIT_1
681#define MBX_0 BIT_0
682
683
684
685
686#define FSTATE_CONFIG_WAIT 0
687#define FSTATE_WAIT_AL_PA 1
688#define FSTATE_WAIT_LOGIN 2
689#define FSTATE_READY 3
690#define FSTATE_LOSS_OF_SYNC 4
691#define FSTATE_ERROR 5
692#define FSTATE_REINIT 6
693#define FSTATE_NON_PART 7
694
695#define FSTATE_CONFIG_CORRECT 0
696#define FSTATE_P2P_RCV_LIP 1
697#define FSTATE_P2P_CHOOSE_LOOP 2
698#define FSTATE_P2P_RCV_UNIDEN_LIP 3
699#define FSTATE_FATAL_ERROR 4
700#define FSTATE_LOOP_BACK_CONN 5
701
702
703
704
705
706#define PORT_DATABASE_SIZE 128
707typedef struct {
708 uint8_t options;
709 uint8_t control;
710 uint8_t master_state;
711 uint8_t slave_state;
712 uint8_t reserved[2];
713 uint8_t hard_address;
714 uint8_t reserved_1;
715 uint8_t port_id[4];
716 uint8_t node_name[WWN_SIZE];
717 uint8_t port_name[WWN_SIZE];
718 uint16_t execution_throttle;
719 uint16_t execution_count;
720 uint8_t reset_count;
721 uint8_t reserved_2;
722 uint16_t resource_allocation;
723 uint16_t current_allocation;
724 uint16_t queue_head;
725 uint16_t queue_tail;
726 uint16_t transmit_execution_list_next;
727 uint16_t transmit_execution_list_previous;
728 uint16_t common_features;
729 uint16_t total_concurrent_sequences;
730 uint16_t RO_by_information_category;
731 uint8_t recipient;
732 uint8_t initiator;
733 uint16_t receive_data_size;
734 uint16_t concurrent_sequences;
735 uint16_t open_sequences_per_exchange;
736 uint16_t lun_abort_flags;
737 uint16_t lun_stop_flags;
738 uint16_t stop_queue_head;
739 uint16_t stop_queue_tail;
740 uint16_t port_retry_timer;
741 uint16_t next_sequence_id;
742 uint16_t frame_count;
743 uint16_t PRLI_payload_length;
744 uint8_t prli_svc_param_word_0[2];
745
746 uint8_t prli_svc_param_word_3[2];
747
748 uint16_t loop_id;
749 uint16_t extended_lun_info_list_pointer;
750 uint16_t extended_lun_stop_list_pointer;
751} port_database_t;
752
753
754
755
756#define PD_STATE_DISCOVERY 0
757#define PD_STATE_WAIT_DISCOVERY_ACK 1
758#define PD_STATE_PORT_LOGIN 2
759#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
760#define PD_STATE_PROCESS_LOGIN 4
761#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
762#define PD_STATE_PORT_LOGGED_IN 6
763#define PD_STATE_PORT_UNAVAILABLE 7
764#define PD_STATE_PROCESS_LOGOUT 8
765#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
766#define PD_STATE_PORT_LOGOUT 10
767#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
768
769
770#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
771#define QLA_ZIO_DISABLED 0
772#define QLA_ZIO_DEFAULT_TIMER 2
773
774
775
776
777
778#define ICB_VERSION 1
779typedef struct {
780 uint8_t version;
781 uint8_t reserved_1;
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802 uint8_t firmware_options[2];
803
804 uint16_t frame_payload_size;
805 uint16_t max_iocb_allocation;
806 uint16_t execution_throttle;
807 uint8_t retry_count;
808 uint8_t retry_delay;
809 uint8_t port_name[WWN_SIZE];
810 uint16_t hard_address;
811 uint8_t inquiry_data;
812 uint8_t login_timeout;
813 uint8_t node_name[WWN_SIZE];
814
815 uint16_t request_q_outpointer;
816 uint16_t response_q_inpointer;
817 uint16_t request_q_length;
818 uint16_t response_q_length;
819 uint32_t request_q_address[2];
820 uint32_t response_q_address[2];
821
822 uint16_t lun_enables;
823 uint8_t command_resource_count;
824 uint8_t immediate_notify_resource_count;
825 uint16_t timeout;
826 uint8_t reserved_2[2];
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847 uint8_t add_firmware_options[2];
848
849 uint8_t response_accumulation_timer;
850 uint8_t interrupt_delay_timer;
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871 uint8_t special_options[2];
872
873 uint8_t reserved_3[26];
874} init_cb_t;
875
876
877
878
879#define GLSO_SEND_RPS BIT_0
880#define GLSO_USE_DID BIT_3
881
882struct link_statistics {
883 uint32_t link_fail_cnt;
884 uint32_t loss_sync_cnt;
885 uint32_t loss_sig_cnt;
886 uint32_t prim_seq_err_cnt;
887 uint32_t inval_xmit_word_cnt;
888 uint32_t inval_crc_cnt;
889 uint32_t lip_cnt;
890 uint32_t unused1[0x1a];
891 uint32_t tx_frames;
892 uint32_t rx_frames;
893 uint32_t dumped_frames;
894 uint32_t unused2[2];
895 uint32_t nos_rcvd;
896};
897
898
899
900
901#define NV_START_BIT BIT_2
902#define NV_WRITE_OP (BIT_26+BIT_24)
903#define NV_READ_OP (BIT_26+BIT_25)
904#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
905#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
906#define NV_DELAY_COUNT 10
907
908
909
910
911typedef struct {
912
913
914
915 uint8_t id[4];
916 uint8_t nvram_version;
917 uint8_t reserved_0;
918
919
920
921
922 uint8_t parameter_block_version;
923 uint8_t reserved_1;
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944 uint8_t firmware_options[2];
945
946 uint16_t frame_payload_size;
947 uint16_t max_iocb_allocation;
948 uint16_t execution_throttle;
949 uint8_t retry_count;
950 uint8_t retry_delay;
951 uint8_t port_name[WWN_SIZE];
952 uint16_t hard_address;
953 uint8_t inquiry_data;
954 uint8_t login_timeout;
955 uint8_t node_name[WWN_SIZE];
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976 uint8_t add_firmware_options[2];
977
978 uint8_t response_accumulation_timer;
979 uint8_t interrupt_delay_timer;
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000 uint8_t special_options[2];
1001
1002
1003 uint8_t reserved_2[22];
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042 uint8_t seriallink_options[4];
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065 uint8_t host_p[2];
1066
1067 uint8_t boot_node_name[WWN_SIZE];
1068 uint8_t boot_lun_number;
1069 uint8_t reset_delay;
1070 uint8_t port_down_retry_count;
1071 uint8_t boot_id_number;
1072 uint16_t max_luns_per_target;
1073 uint8_t fcode_boot_port_name[WWN_SIZE];
1074 uint8_t alternate_port_name[WWN_SIZE];
1075 uint8_t alternate_node_name[WWN_SIZE];
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087 uint8_t efi_parameters;
1088
1089 uint8_t link_down_timeout;
1090
1091 uint8_t adapter_id[16];
1092
1093 uint8_t alt1_boot_node_name[WWN_SIZE];
1094 uint16_t alt1_boot_lun_number;
1095 uint8_t alt2_boot_node_name[WWN_SIZE];
1096 uint16_t alt2_boot_lun_number;
1097 uint8_t alt3_boot_node_name[WWN_SIZE];
1098 uint16_t alt3_boot_lun_number;
1099 uint8_t alt4_boot_node_name[WWN_SIZE];
1100 uint16_t alt4_boot_lun_number;
1101 uint8_t alt5_boot_node_name[WWN_SIZE];
1102 uint16_t alt5_boot_lun_number;
1103 uint8_t alt6_boot_node_name[WWN_SIZE];
1104 uint16_t alt6_boot_lun_number;
1105 uint8_t alt7_boot_node_name[WWN_SIZE];
1106 uint16_t alt7_boot_lun_number;
1107
1108 uint8_t reserved_3[2];
1109
1110
1111 uint8_t model_number[16];
1112
1113
1114 uint8_t oem_specific[16];
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137 uint8_t adapter_features[2];
1138
1139 uint8_t reserved_4[16];
1140
1141
1142 uint16_t subsystem_vendor_id_2200;
1143
1144
1145 uint16_t subsystem_device_id_2200;
1146
1147 uint8_t reserved_5;
1148 uint8_t checksum;
1149} nvram_t;
1150
1151
1152
1153
1154typedef struct {
1155 uint8_t data[60];
1156 uint32_t signature;
1157#define RESPONSE_PROCESSED 0xDEADDEAD
1158} response_t;
1159
1160typedef union {
1161 uint16_t extended;
1162 struct {
1163 uint8_t reserved;
1164 uint8_t standard;
1165 } id;
1166} target_id_t;
1167
1168#define SET_TARGET_ID(ha, to, from) \
1169do { \
1170 if (HAS_EXTENDED_IDS(ha)) \
1171 to.extended = cpu_to_le16(from); \
1172 else \
1173 to.id.standard = (uint8_t)from; \
1174} while (0)
1175
1176
1177
1178
1179#define COMMAND_TYPE 0x11
1180typedef struct {
1181 uint8_t entry_type;
1182 uint8_t entry_count;
1183 uint8_t sys_define;
1184 uint8_t entry_status;
1185 uint32_t handle;
1186 target_id_t target;
1187 uint16_t lun;
1188 uint16_t control_flags;
1189#define CF_WRITE BIT_6
1190#define CF_READ BIT_5
1191#define CF_SIMPLE_TAG BIT_3
1192#define CF_ORDERED_TAG BIT_2
1193#define CF_HEAD_TAG BIT_1
1194 uint16_t reserved_1;
1195 uint16_t timeout;
1196 uint16_t dseg_count;
1197 uint8_t scsi_cdb[MAX_CMDSZ];
1198 uint32_t byte_count;
1199 uint32_t dseg_0_address;
1200 uint32_t dseg_0_length;
1201 uint32_t dseg_1_address;
1202 uint32_t dseg_1_length;
1203 uint32_t dseg_2_address;
1204 uint32_t dseg_2_length;
1205} cmd_entry_t;
1206
1207
1208
1209
1210#define COMMAND_A64_TYPE 0x19
1211typedef struct {
1212 uint8_t entry_type;
1213 uint8_t entry_count;
1214 uint8_t sys_define;
1215 uint8_t entry_status;
1216 uint32_t handle;
1217 target_id_t target;
1218 uint16_t lun;
1219 uint16_t control_flags;
1220 uint16_t reserved_1;
1221 uint16_t timeout;
1222 uint16_t dseg_count;
1223 uint8_t scsi_cdb[MAX_CMDSZ];
1224 uint32_t byte_count;
1225 uint32_t dseg_0_address[2];
1226 uint32_t dseg_0_length;
1227 uint32_t dseg_1_address[2];
1228 uint32_t dseg_1_length;
1229} cmd_a64_entry_t, request_t;
1230
1231
1232
1233
1234#define CONTINUE_TYPE 0x02
1235typedef struct {
1236 uint8_t entry_type;
1237 uint8_t entry_count;
1238 uint8_t sys_define;
1239 uint8_t entry_status;
1240 uint32_t reserved;
1241 uint32_t dseg_0_address;
1242 uint32_t dseg_0_length;
1243 uint32_t dseg_1_address;
1244 uint32_t dseg_1_length;
1245 uint32_t dseg_2_address;
1246 uint32_t dseg_2_length;
1247 uint32_t dseg_3_address;
1248 uint32_t dseg_3_length;
1249 uint32_t dseg_4_address;
1250 uint32_t dseg_4_length;
1251 uint32_t dseg_5_address;
1252 uint32_t dseg_5_length;
1253 uint32_t dseg_6_address;
1254 uint32_t dseg_6_length;
1255} cont_entry_t;
1256
1257
1258
1259
1260#define CONTINUE_A64_TYPE 0x0A
1261typedef struct {
1262 uint8_t entry_type;
1263 uint8_t entry_count;
1264 uint8_t sys_define;
1265 uint8_t entry_status;
1266 uint32_t dseg_0_address[2];
1267 uint32_t dseg_0_length;
1268 uint32_t dseg_1_address[2];
1269 uint32_t dseg_1_length;
1270 uint32_t dseg_2_address [2];
1271 uint32_t dseg_2_length;
1272 uint32_t dseg_3_address[2];
1273 uint32_t dseg_3_length;
1274 uint32_t dseg_4_address[2];
1275 uint32_t dseg_4_length;
1276} cont_a64_entry_t;
1277
1278
1279
1280
1281#define STATUS_TYPE 0x03
1282typedef struct {
1283 uint8_t entry_type;
1284 uint8_t entry_count;
1285 uint8_t sys_define;
1286 uint8_t entry_status;
1287 uint32_t handle;
1288 uint16_t scsi_status;
1289 uint16_t comp_status;
1290 uint16_t state_flags;
1291 uint16_t status_flags;
1292 uint16_t rsp_info_len;
1293 uint16_t req_sense_length;
1294 uint32_t residual_length;
1295 uint8_t rsp_info[8];
1296 uint8_t req_sense_data[32];
1297} sts_entry_t;
1298
1299
1300
1301
1302#define RF_RQ_DMA_ERROR BIT_6
1303#define RF_INV_E_ORDER BIT_5
1304#define RF_INV_E_COUNT BIT_4
1305#define RF_INV_E_PARAM BIT_3
1306#define RF_INV_E_TYPE BIT_2
1307#define RF_BUSY BIT_1
1308#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1309 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1310#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1311 RF_INV_E_TYPE)
1312
1313
1314
1315
1316#define SS_MASK 0xfff
1317#define SS_RESIDUAL_UNDER BIT_11
1318#define SS_RESIDUAL_OVER BIT_10
1319#define SS_SENSE_LEN_VALID BIT_9
1320#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1321
1322#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1323#define SS_BUSY_CONDITION BIT_3
1324#define SS_CONDITION_MET BIT_2
1325#define SS_CHECK_CONDITION BIT_1
1326
1327
1328
1329
1330#define CS_COMPLETE 0x0
1331#define CS_INCOMPLETE 0x1
1332#define CS_DMA 0x2
1333#define CS_TRANSPORT 0x3
1334#define CS_RESET 0x4
1335#define CS_ABORTED 0x5
1336#define CS_TIMEOUT 0x6
1337#define CS_DATA_OVERRUN 0x7
1338
1339#define CS_DATA_UNDERRUN 0x15
1340#define CS_QUEUE_FULL 0x1C
1341#define CS_PORT_UNAVAILABLE 0x28
1342
1343#define CS_PORT_LOGGED_OUT 0x29
1344#define CS_PORT_CONFIG_CHG 0x2A
1345#define CS_PORT_BUSY 0x2B
1346#define CS_COMPLETE_CHKCOND 0x30
1347#define CS_BAD_PAYLOAD 0x80
1348#define CS_UNKNOWN 0x81
1349#define CS_RETRY 0x82
1350#define CS_LOOP_DOWN_ABORT 0x83
1351
1352
1353
1354
1355#define SF_ABTS_TERMINATED BIT_10
1356#define SF_LOGOUT_SENT BIT_13
1357
1358
1359
1360
1361#define STATUS_CONT_TYPE 0x10
1362typedef struct {
1363 uint8_t entry_type;
1364 uint8_t entry_count;
1365 uint8_t sys_define;
1366 uint8_t entry_status;
1367 uint8_t data[60];
1368} sts_cont_entry_t;
1369
1370
1371
1372
1373
1374#define STATUS_TYPE_21 0x21
1375typedef struct {
1376 uint8_t entry_type;
1377 uint8_t entry_count;
1378 uint8_t handle_count;
1379 uint8_t entry_status;
1380 uint32_t handle[15];
1381} sts21_entry_t;
1382
1383
1384
1385
1386
1387#define STATUS_TYPE_22 0x22
1388typedef struct {
1389 uint8_t entry_type;
1390 uint8_t entry_count;
1391 uint8_t handle_count;
1392 uint8_t entry_status;
1393 uint16_t handle[30];
1394} sts22_entry_t;
1395
1396
1397
1398
1399#define MARKER_TYPE 0x04
1400typedef struct {
1401 uint8_t entry_type;
1402 uint8_t entry_count;
1403 uint8_t handle_count;
1404 uint8_t entry_status;
1405 uint32_t sys_define_2;
1406 target_id_t target;
1407 uint8_t modifier;
1408#define MK_SYNC_ID_LUN 0
1409#define MK_SYNC_ID 1
1410#define MK_SYNC_ALL 2
1411#define MK_SYNC_LIP 3
1412
1413
1414 uint8_t reserved_1;
1415 uint16_t sequence_number;
1416 uint16_t lun;
1417 uint8_t reserved_2[48];
1418} mrk_entry_t;
1419
1420
1421
1422
1423#define MS_IOCB_TYPE 0x29
1424typedef struct {
1425 uint8_t entry_type;
1426 uint8_t entry_count;
1427 uint8_t handle_count;
1428 uint8_t entry_status;
1429 uint32_t handle1;
1430 target_id_t loop_id;
1431 uint16_t status;
1432 uint16_t control_flags;
1433 uint16_t reserved2;
1434 uint16_t timeout;
1435 uint16_t cmd_dsd_count;
1436 uint16_t total_dsd_count;
1437 uint8_t type;
1438 uint8_t r_ctl;
1439 uint16_t rx_id;
1440 uint16_t reserved3;
1441 uint32_t handle2;
1442 uint32_t rsp_bytecount;
1443 uint32_t req_bytecount;
1444 uint32_t dseg_req_address[2];
1445 uint32_t dseg_req_length;
1446 uint32_t dseg_rsp_address[2];
1447 uint32_t dseg_rsp_length;
1448} ms_iocb_entry_t;
1449
1450
1451
1452
1453
1454#define MBX_IOCB_TYPE 0x39
1455struct mbx_entry {
1456 uint8_t entry_type;
1457 uint8_t entry_count;
1458 uint8_t sys_define1;
1459
1460#define SOURCE_SCSI 0x00
1461#define SOURCE_IP 0x01
1462#define SOURCE_VI 0x02
1463#define SOURCE_SCTP 0x03
1464#define SOURCE_MP 0x04
1465#define SOURCE_MPIOCTL 0x05
1466#define SOURCE_ASYNC_IOCB 0x07
1467
1468 uint8_t entry_status;
1469
1470 uint32_t handle;
1471 target_id_t loop_id;
1472
1473 uint16_t status;
1474 uint16_t state_flags;
1475 uint16_t status_flags;
1476
1477 uint32_t sys_define2[2];
1478
1479 uint16_t mb0;
1480 uint16_t mb1;
1481 uint16_t mb2;
1482 uint16_t mb3;
1483 uint16_t mb6;
1484 uint16_t mb7;
1485 uint16_t mb9;
1486 uint16_t mb10;
1487 uint32_t reserved_2[2];
1488 uint8_t node_name[WWN_SIZE];
1489 uint8_t port_name[WWN_SIZE];
1490};
1491
1492
1493
1494
1495#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1496#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1497
1498
1499
1500
1501
1502typedef union {
1503 uint32_t b24 : 24;
1504
1505 struct {
1506#ifdef __BIG_ENDIAN
1507 uint8_t domain;
1508 uint8_t area;
1509 uint8_t al_pa;
1510#elif defined(__LITTLE_ENDIAN)
1511 uint8_t al_pa;
1512 uint8_t area;
1513 uint8_t domain;
1514#else
1515#error "__BIG_ENDIAN or __LITTLE_ENDIAN must be defined!"
1516#endif
1517 uint8_t rsvd_1;
1518 } b;
1519} port_id_t;
1520#define INVALID_PORT_ID 0xFFFFFF
1521
1522
1523
1524
1525typedef struct {
1526 port_id_t d_id;
1527 uint8_t node_name[WWN_SIZE];
1528 uint8_t port_name[WWN_SIZE];
1529 uint8_t fabric_port_name[WWN_SIZE];
1530 uint16_t fp_speed;
1531} sw_info_t;
1532
1533
1534
1535
1536 typedef enum {
1537 FCT_UNKNOWN,
1538 FCT_RSCN,
1539 FCT_SWITCH,
1540 FCT_BROADCAST,
1541 FCT_INITIATOR,
1542 FCT_TARGET
1543} fc_port_type_t;
1544
1545
1546
1547
1548typedef struct fc_port {
1549 struct list_head list;
1550 struct scsi_qla_host *vha;
1551
1552 uint8_t node_name[WWN_SIZE];
1553 uint8_t port_name[WWN_SIZE];
1554 port_id_t d_id;
1555 uint16_t loop_id;
1556 uint16_t old_loop_id;
1557
1558 uint8_t fabric_port_name[WWN_SIZE];
1559 uint16_t fp_speed;
1560
1561 fc_port_type_t port_type;
1562
1563 atomic_t state;
1564 uint32_t flags;
1565
1566 int port_login_retry_count;
1567 int login_retry;
1568 atomic_t port_down_timer;
1569
1570 struct fc_rport *rport, *drport;
1571 u32 supported_classes;
1572
1573 unsigned long last_queue_full;
1574 unsigned long last_ramp_up;
1575
1576 uint16_t vp_idx;
1577} fc_port_t;
1578
1579
1580
1581
1582#define FCS_UNCONFIGURED 1
1583#define FCS_DEVICE_DEAD 2
1584#define FCS_DEVICE_LOST 3
1585#define FCS_ONLINE 4
1586
1587
1588
1589
1590#define FCF_FABRIC_DEVICE BIT_0
1591#define FCF_LOGIN_NEEDED BIT_1
1592#define FCF_TAPE_PRESENT BIT_2
1593#define FCF_FCP2_DEVICE BIT_3
1594
1595
1596#define FC_NO_LOOP_ID 0x1000
1597
1598
1599
1600
1601
1602
1603
1604#define CT_REJECT_RESPONSE 0x8001
1605#define CT_ACCEPT_RESPONSE 0x8002
1606#define CT_REASON_INVALID_COMMAND_CODE 0x01
1607#define CT_REASON_CANNOT_PERFORM 0x09
1608#define CT_REASON_COMMAND_UNSUPPORTED 0x0b
1609#define CT_EXPL_ALREADY_REGISTERED 0x10
1610
1611#define NS_N_PORT_TYPE 0x01
1612#define NS_NL_PORT_TYPE 0x02
1613#define NS_NX_PORT_TYPE 0x7F
1614
1615#define GA_NXT_CMD 0x100
1616#define GA_NXT_REQ_SIZE (16 + 4)
1617#define GA_NXT_RSP_SIZE (16 + 620)
1618
1619#define GID_PT_CMD 0x1A1
1620#define GID_PT_REQ_SIZE (16 + 4)
1621#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1622
1623#define GPN_ID_CMD 0x112
1624#define GPN_ID_REQ_SIZE (16 + 4)
1625#define GPN_ID_RSP_SIZE (16 + 8)
1626
1627#define GNN_ID_CMD 0x113
1628#define GNN_ID_REQ_SIZE (16 + 4)
1629#define GNN_ID_RSP_SIZE (16 + 8)
1630
1631#define GFT_ID_CMD 0x117
1632#define GFT_ID_REQ_SIZE (16 + 4)
1633#define GFT_ID_RSP_SIZE (16 + 32)
1634
1635#define RFT_ID_CMD 0x217
1636#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1637#define RFT_ID_RSP_SIZE 16
1638
1639#define RFF_ID_CMD 0x21F
1640#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1641#define RFF_ID_RSP_SIZE 16
1642
1643#define RNN_ID_CMD 0x213
1644#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1645#define RNN_ID_RSP_SIZE 16
1646
1647#define RSNN_NN_CMD 0x239
1648#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1649#define RSNN_NN_RSP_SIZE 16
1650
1651#define GFPN_ID_CMD 0x11C
1652#define GFPN_ID_REQ_SIZE (16 + 4)
1653#define GFPN_ID_RSP_SIZE (16 + 8)
1654
1655#define GPSC_CMD 0x127
1656#define GPSC_REQ_SIZE (16 + 8)
1657#define GPSC_RSP_SIZE (16 + 2 + 2)
1658
1659
1660
1661
1662
1663#define FDMI_HBA_ATTR_COUNT 9
1664#define FDMI_HBA_NODE_NAME 1
1665#define FDMI_HBA_MANUFACTURER 2
1666#define FDMI_HBA_SERIAL_NUMBER 3
1667#define FDMI_HBA_MODEL 4
1668#define FDMI_HBA_MODEL_DESCRIPTION 5
1669#define FDMI_HBA_HARDWARE_VERSION 6
1670#define FDMI_HBA_DRIVER_VERSION 7
1671#define FDMI_HBA_OPTION_ROM_VERSION 8
1672#define FDMI_HBA_FIRMWARE_VERSION 9
1673#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1674#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1675
1676struct ct_fdmi_hba_attr {
1677 uint16_t type;
1678 uint16_t len;
1679 union {
1680 uint8_t node_name[WWN_SIZE];
1681 uint8_t manufacturer[32];
1682 uint8_t serial_num[8];
1683 uint8_t model[16];
1684 uint8_t model_desc[80];
1685 uint8_t hw_version[16];
1686 uint8_t driver_version[32];
1687 uint8_t orom_version[16];
1688 uint8_t fw_version[16];
1689 uint8_t os_version[128];
1690 uint8_t max_ct_len[4];
1691 } a;
1692};
1693
1694struct ct_fdmi_hba_attributes {
1695 uint32_t count;
1696 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1697};
1698
1699
1700
1701
1702#define FDMI_PORT_ATTR_COUNT 6
1703#define FDMI_PORT_FC4_TYPES 1
1704#define FDMI_PORT_SUPPORT_SPEED 2
1705#define FDMI_PORT_CURRENT_SPEED 3
1706#define FDMI_PORT_MAX_FRAME_SIZE 4
1707#define FDMI_PORT_OS_DEVICE_NAME 5
1708#define FDMI_PORT_HOST_NAME 6
1709
1710#define FDMI_PORT_SPEED_1GB 0x1
1711#define FDMI_PORT_SPEED_2GB 0x2
1712#define FDMI_PORT_SPEED_10GB 0x4
1713#define FDMI_PORT_SPEED_4GB 0x8
1714#define FDMI_PORT_SPEED_8GB 0x10
1715#define FDMI_PORT_SPEED_16GB 0x20
1716#define FDMI_PORT_SPEED_UNKNOWN 0x8000
1717
1718struct ct_fdmi_port_attr {
1719 uint16_t type;
1720 uint16_t len;
1721 union {
1722 uint8_t fc4_types[32];
1723 uint32_t sup_speed;
1724 uint32_t cur_speed;
1725 uint32_t max_frame_size;
1726 uint8_t os_dev_name[32];
1727 uint8_t host_name[32];
1728 } a;
1729};
1730
1731
1732
1733
1734struct ct_fdmi_port_attributes {
1735 uint32_t count;
1736 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1737};
1738
1739
1740#define GRHL_CMD 0x100
1741#define GHAT_CMD 0x101
1742#define GRPL_CMD 0x102
1743#define GPAT_CMD 0x110
1744
1745#define RHBA_CMD 0x200
1746#define RHBA_RSP_SIZE 16
1747
1748#define RHAT_CMD 0x201
1749#define RPRT_CMD 0x210
1750
1751#define RPA_CMD 0x211
1752#define RPA_RSP_SIZE 16
1753
1754#define DHBA_CMD 0x300
1755#define DHBA_REQ_SIZE (16 + 8)
1756#define DHBA_RSP_SIZE 16
1757
1758#define DHAT_CMD 0x301
1759#define DPRT_CMD 0x310
1760#define DPA_CMD 0x311
1761
1762
1763struct ct_cmd_hdr {
1764 uint8_t revision;
1765 uint8_t in_id[3];
1766 uint8_t gs_type;
1767 uint8_t gs_subtype;
1768 uint8_t options;
1769 uint8_t reserved;
1770};
1771
1772
1773struct ct_sns_req {
1774 struct ct_cmd_hdr header;
1775 uint16_t command;
1776 uint16_t max_rsp_size;
1777 uint8_t fragment_id;
1778 uint8_t reserved[3];
1779
1780 union {
1781
1782 struct {
1783 uint8_t reserved;
1784 uint8_t port_id[3];
1785 } port_id;
1786
1787 struct {
1788 uint8_t port_type;
1789 uint8_t domain;
1790 uint8_t area;
1791 uint8_t reserved;
1792 } gid_pt;
1793
1794 struct {
1795 uint8_t reserved;
1796 uint8_t port_id[3];
1797 uint8_t fc4_types[32];
1798 } rft_id;
1799
1800 struct {
1801 uint8_t reserved;
1802 uint8_t port_id[3];
1803 uint16_t reserved2;
1804 uint8_t fc4_feature;
1805 uint8_t fc4_type;
1806 } rff_id;
1807
1808 struct {
1809 uint8_t reserved;
1810 uint8_t port_id[3];
1811 uint8_t node_name[8];
1812 } rnn_id;
1813
1814 struct {
1815 uint8_t node_name[8];
1816 uint8_t name_len;
1817 uint8_t sym_node_name[255];
1818 } rsnn_nn;
1819
1820 struct {
1821 uint8_t hba_indentifier[8];
1822 } ghat;
1823
1824 struct {
1825 uint8_t hba_identifier[8];
1826 uint32_t entry_count;
1827 uint8_t port_name[8];
1828 struct ct_fdmi_hba_attributes attrs;
1829 } rhba;
1830
1831 struct {
1832 uint8_t hba_identifier[8];
1833 struct ct_fdmi_hba_attributes attrs;
1834 } rhat;
1835
1836 struct {
1837 uint8_t port_name[8];
1838 struct ct_fdmi_port_attributes attrs;
1839 } rpa;
1840
1841 struct {
1842 uint8_t port_name[8];
1843 } dhba;
1844
1845 struct {
1846 uint8_t port_name[8];
1847 } dhat;
1848
1849 struct {
1850 uint8_t port_name[8];
1851 } dprt;
1852
1853 struct {
1854 uint8_t port_name[8];
1855 } dpa;
1856
1857 struct {
1858 uint8_t port_name[8];
1859 } gpsc;
1860 } req;
1861};
1862
1863
1864struct ct_rsp_hdr {
1865 struct ct_cmd_hdr header;
1866 uint16_t response;
1867 uint16_t residual;
1868 uint8_t fragment_id;
1869 uint8_t reason_code;
1870 uint8_t explanation_code;
1871 uint8_t vendor_unique;
1872};
1873
1874struct ct_sns_gid_pt_data {
1875 uint8_t control_byte;
1876 uint8_t port_id[3];
1877};
1878
1879struct ct_sns_rsp {
1880 struct ct_rsp_hdr header;
1881
1882 union {
1883 struct {
1884 uint8_t port_type;
1885 uint8_t port_id[3];
1886 uint8_t port_name[8];
1887 uint8_t sym_port_name_len;
1888 uint8_t sym_port_name[255];
1889 uint8_t node_name[8];
1890 uint8_t sym_node_name_len;
1891 uint8_t sym_node_name[255];
1892 uint8_t init_proc_assoc[8];
1893 uint8_t node_ip_addr[16];
1894 uint8_t class_of_service[4];
1895 uint8_t fc4_types[32];
1896 uint8_t ip_address[16];
1897 uint8_t fabric_port_name[8];
1898 uint8_t reserved;
1899 uint8_t hard_address[3];
1900 } ga_nxt;
1901
1902 struct {
1903 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
1904 } gid_pt;
1905
1906 struct {
1907 uint8_t port_name[8];
1908 } gpn_id;
1909
1910 struct {
1911 uint8_t node_name[8];
1912 } gnn_id;
1913
1914 struct {
1915 uint8_t fc4_types[32];
1916 } gft_id;
1917
1918 struct {
1919 uint32_t entry_count;
1920 uint8_t port_name[8];
1921 struct ct_fdmi_hba_attributes attrs;
1922 } ghat;
1923
1924 struct {
1925 uint8_t port_name[8];
1926 } gfpn_id;
1927
1928 struct {
1929 uint16_t speeds;
1930 uint16_t speed;
1931 } gpsc;
1932 } rsp;
1933};
1934
1935struct ct_sns_pkt {
1936 union {
1937 struct ct_sns_req req;
1938 struct ct_sns_rsp rsp;
1939 } p;
1940};
1941
1942
1943
1944
1945#define RFT_ID_SNS_SCMD_LEN 22
1946#define RFT_ID_SNS_CMD_SIZE 60
1947#define RFT_ID_SNS_DATA_SIZE 16
1948
1949#define RNN_ID_SNS_SCMD_LEN 10
1950#define RNN_ID_SNS_CMD_SIZE 36
1951#define RNN_ID_SNS_DATA_SIZE 16
1952
1953#define GA_NXT_SNS_SCMD_LEN 6
1954#define GA_NXT_SNS_CMD_SIZE 28
1955#define GA_NXT_SNS_DATA_SIZE (620 + 16)
1956
1957#define GID_PT_SNS_SCMD_LEN 6
1958#define GID_PT_SNS_CMD_SIZE 28
1959#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
1960
1961#define GPN_ID_SNS_SCMD_LEN 6
1962#define GPN_ID_SNS_CMD_SIZE 28
1963#define GPN_ID_SNS_DATA_SIZE (8 + 16)
1964
1965#define GNN_ID_SNS_SCMD_LEN 6
1966#define GNN_ID_SNS_CMD_SIZE 28
1967#define GNN_ID_SNS_DATA_SIZE (8 + 16)
1968
1969struct sns_cmd_pkt {
1970 union {
1971 struct {
1972 uint16_t buffer_length;
1973 uint16_t reserved_1;
1974 uint32_t buffer_address[2];
1975 uint16_t subcommand_length;
1976 uint16_t reserved_2;
1977 uint16_t subcommand;
1978 uint16_t size;
1979 uint32_t reserved_3;
1980 uint8_t param[36];
1981 } cmd;
1982
1983 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
1984 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
1985 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
1986 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
1987 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
1988 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
1989 } p;
1990};
1991
1992struct fw_blob {
1993 char *name;
1994 uint32_t segs[4];
1995 const struct firmware *fw;
1996};
1997
1998
1999struct gid_list_info {
2000 uint8_t al_pa;
2001 uint8_t area;
2002 uint8_t domain;
2003 uint8_t loop_id_2100;
2004 uint16_t loop_id;
2005 uint16_t reserved_1;
2006};
2007#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2008
2009
2010typedef struct vport_info {
2011 uint8_t port_name[WWN_SIZE];
2012 uint8_t node_name[WWN_SIZE];
2013 int vp_id;
2014 uint16_t loop_id;
2015 unsigned long host_no;
2016 uint8_t port_id[3];
2017 int loop_state;
2018} vport_info_t;
2019
2020typedef struct vport_params {
2021 uint8_t port_name[WWN_SIZE];
2022 uint8_t node_name[WWN_SIZE];
2023 uint32_t options;
2024#define VP_OPTS_RETRY_ENABLE BIT_0
2025#define VP_OPTS_VP_DISABLE BIT_1
2026} vport_params_t;
2027
2028
2029#define VP_RET_CODE_OK 0
2030#define VP_RET_CODE_FATAL 1
2031#define VP_RET_CODE_WRONG_ID 2
2032#define VP_RET_CODE_WWPN 3
2033#define VP_RET_CODE_RESOURCES 4
2034#define VP_RET_CODE_NO_MEM 5
2035#define VP_RET_CODE_NOT_FOUND 6
2036
2037struct qla_hw_data;
2038struct rsp_que;
2039
2040
2041
2042struct isp_operations {
2043
2044 int (*pci_config) (struct scsi_qla_host *);
2045 void (*reset_chip) (struct scsi_qla_host *);
2046 int (*chip_diag) (struct scsi_qla_host *);
2047 void (*config_rings) (struct scsi_qla_host *);
2048 void (*reset_adapter) (struct scsi_qla_host *);
2049 int (*nvram_config) (struct scsi_qla_host *);
2050 void (*update_fw_options) (struct scsi_qla_host *);
2051 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2052
2053 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2054 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2055
2056 irq_handler_t intr_handler;
2057 void (*enable_intrs) (struct qla_hw_data *);
2058 void (*disable_intrs) (struct qla_hw_data *);
2059
2060 int (*abort_command) (srb_t *);
2061 int (*target_reset) (struct fc_port *, unsigned int, int);
2062 int (*lun_reset) (struct fc_port *, unsigned int, int);
2063 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2064 uint8_t, uint8_t, uint16_t *, uint8_t);
2065 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2066 uint8_t, uint8_t);
2067
2068 uint16_t (*calc_req_entries) (uint16_t);
2069 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2070 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2071 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2072 uint32_t);
2073
2074 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2075 uint32_t, uint32_t);
2076 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2077 uint32_t);
2078
2079 void (*fw_dump) (struct scsi_qla_host *, int);
2080
2081 int (*beacon_on) (struct scsi_qla_host *);
2082 int (*beacon_off) (struct scsi_qla_host *);
2083 void (*beacon_blink) (struct scsi_qla_host *);
2084
2085 uint8_t * (*read_optrom) (struct scsi_qla_host *, uint8_t *,
2086 uint32_t, uint32_t);
2087 int (*write_optrom) (struct scsi_qla_host *, uint8_t *, uint32_t,
2088 uint32_t);
2089
2090 int (*get_flash_version) (struct scsi_qla_host *, void *);
2091 int (*start_scsi) (srb_t *);
2092};
2093
2094
2095
2096#define QLA_MSIX_CHIP_REV_24XX 3
2097#define QLA_MSIX_FW_MODE(m) (((m) & (BIT_7|BIT_8|BIT_9)) >> 7)
2098#define QLA_MSIX_FW_MODE_1(m) (QLA_MSIX_FW_MODE(m) == 1)
2099
2100#define QLA_MSIX_DEFAULT 0x00
2101#define QLA_MSIX_RSP_Q 0x01
2102
2103#define QLA_MIDX_DEFAULT 0
2104#define QLA_MIDX_RSP_Q 1
2105#define QLA_PCI_MSIX_CONTROL 0xa2
2106
2107struct scsi_qla_host;
2108
2109struct qla_msix_entry {
2110 int have_irq;
2111 uint32_t vector;
2112 uint16_t entry;
2113 struct rsp_que *rsp;
2114};
2115
2116#define WATCH_INTERVAL 1
2117
2118
2119enum qla_work_type {
2120 QLA_EVT_AEN,
2121 QLA_EVT_IDC_ACK,
2122 QLA_EVT_ASYNC_LOGIN,
2123 QLA_EVT_ASYNC_LOGIN_DONE,
2124 QLA_EVT_ASYNC_LOGOUT,
2125 QLA_EVT_ASYNC_LOGOUT_DONE,
2126};
2127
2128
2129struct qla_work_evt {
2130 struct list_head list;
2131 enum qla_work_type type;
2132 u32 flags;
2133#define QLA_EVT_FLAG_FREE 0x1
2134
2135 union {
2136 struct {
2137 enum fc_host_event_code code;
2138 u32 data;
2139 } aen;
2140 struct {
2141#define QLA_IDC_ACK_REGS 7
2142 uint16_t mb[QLA_IDC_ACK_REGS];
2143 } idc_ack;
2144 struct {
2145 struct fc_port *fcport;
2146#define QLA_LOGIO_LOGIN_RETRIED BIT_0
2147 u16 data[2];
2148 } logio;
2149 } u;
2150};
2151
2152struct qla_chip_state_84xx {
2153 struct list_head list;
2154 struct kref kref;
2155
2156 void *bus;
2157 spinlock_t access_lock;
2158 struct mutex fw_update_mutex;
2159 uint32_t fw_update;
2160 uint32_t op_fw_version;
2161 uint32_t op_fw_size;
2162 uint32_t op_fw_seq_size;
2163 uint32_t diag_fw_version;
2164 uint32_t gold_fw_version;
2165};
2166
2167struct qla_statistics {
2168 uint32_t total_isp_aborts;
2169 uint64_t input_bytes;
2170 uint64_t output_bytes;
2171};
2172
2173
2174#define MBC_INITIALIZE_MULTIQ 0x1f
2175#define QLA_QUE_PAGE 0X1000
2176#define QLA_MQ_SIZE 32
2177#define QLA_MAX_QUEUES 256
2178#define ISP_QUE_REG(ha, id) \
2179 ((ha->mqenable) ? \
2180 ((void *)(ha->mqiobase) +\
2181 (QLA_QUE_PAGE * id)) :\
2182 ((void *)(ha->iobase)))
2183#define QLA_REQ_QUE_ID(tag) \
2184 ((tag < QLA_MAX_QUEUES && tag > 0) ? tag : 0)
2185#define QLA_DEFAULT_QUE_QOS 5
2186#define QLA_PRECONFIG_VPORTS 32
2187#define QLA_MAX_VPORTS_QLA24XX 128
2188#define QLA_MAX_VPORTS_QLA25XX 256
2189
2190struct rsp_que {
2191 dma_addr_t dma;
2192 response_t *ring;
2193 response_t *ring_ptr;
2194 uint32_t __iomem *rsp_q_in;
2195 uint32_t __iomem *rsp_q_out;
2196 uint16_t ring_index;
2197 uint16_t out_ptr;
2198 uint16_t length;
2199 uint16_t options;
2200 uint16_t rid;
2201 uint16_t id;
2202 uint16_t vp_idx;
2203 struct qla_hw_data *hw;
2204 struct qla_msix_entry *msix;
2205 struct req_que *req;
2206 srb_t *status_srb;
2207 struct work_struct q_work;
2208};
2209
2210
2211struct req_que {
2212 dma_addr_t dma;
2213 request_t *ring;
2214 request_t *ring_ptr;
2215 uint32_t __iomem *req_q_in;
2216 uint32_t __iomem *req_q_out;
2217 uint16_t ring_index;
2218 uint16_t in_ptr;
2219 uint16_t cnt;
2220 uint16_t length;
2221 uint16_t options;
2222 uint16_t rid;
2223 uint16_t id;
2224 uint16_t qos;
2225 uint16_t vp_idx;
2226 struct rsp_que *rsp;
2227 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2228 uint32_t current_outstanding_cmd;
2229 int max_q_depth;
2230};
2231
2232
2233
2234
2235struct qla_hw_data {
2236 struct pci_dev *pdev;
2237
2238#define SRB_MIN_REQ 128
2239 mempool_t *srb_mempool;
2240
2241 volatile struct {
2242 uint32_t mbox_int :1;
2243 uint32_t mbox_busy :1;
2244
2245 uint32_t disable_risc_code_load :1;
2246 uint32_t enable_64bit_addressing :1;
2247 uint32_t enable_lip_reset :1;
2248 uint32_t enable_target_reset :1;
2249 uint32_t enable_lip_full_login :1;
2250 uint32_t enable_led_scheme :1;
2251 uint32_t inta_enabled :1;
2252 uint32_t msi_enabled :1;
2253 uint32_t msix_enabled :1;
2254 uint32_t disable_serdes :1;
2255 uint32_t gpsc_supported :1;
2256 uint32_t npiv_supported :1;
2257 uint32_t fce_enabled :1;
2258 uint32_t fac_supported :1;
2259 uint32_t chip_reset_done :1;
2260 uint32_t port0 :1;
2261 uint32_t running_gold_fw :1;
2262 uint32_t cpu_affinity_enabled :1;
2263 } flags;
2264
2265
2266
2267
2268
2269
2270
2271
2272 spinlock_t hardware_lock ____cacheline_aligned;
2273 int bars;
2274 int mem_only;
2275 device_reg_t __iomem *iobase;
2276 resource_size_t pio_address;
2277
2278#define MIN_IOBASE_LEN 0x100
2279
2280 device_reg_t __iomem *mqiobase;
2281 uint16_t msix_count;
2282 uint8_t mqenable;
2283 struct req_que **req_q_map;
2284 struct rsp_que **rsp_q_map;
2285 unsigned long req_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2286 unsigned long rsp_qid_map[(QLA_MAX_QUEUES / 8) / sizeof(unsigned long)];
2287 uint8_t max_req_queues;
2288 uint8_t max_rsp_queues;
2289 struct qla_npiv_entry *npiv_info;
2290 uint16_t nvram_npiv_size;
2291
2292 uint16_t switch_cap;
2293#define FLOGI_SEQ_DEL BIT_8
2294#define FLOGI_MID_SUPPORT BIT_10
2295#define FLOGI_VSAN_SUPPORT BIT_12
2296#define FLOGI_SP_SUPPORT BIT_13
2297
2298 uint8_t port_no;
2299
2300
2301 uint8_t loop_down_abort_time;
2302 atomic_t loop_down_timer;
2303 uint8_t link_down_timeout;
2304 uint16_t max_loop_id;
2305
2306 uint16_t fb_rev;
2307 uint16_t min_external_loopid;
2308
2309#define PORT_SPEED_UNKNOWN 0xFFFF
2310#define PORT_SPEED_1GB 0x00
2311#define PORT_SPEED_2GB 0x01
2312#define PORT_SPEED_4GB 0x03
2313#define PORT_SPEED_8GB 0x04
2314#define PORT_SPEED_10GB 0x13
2315 uint16_t link_data_rate;
2316
2317 uint8_t current_topology;
2318 uint8_t prev_topology;
2319#define ISP_CFG_NL 1
2320#define ISP_CFG_N 2
2321#define ISP_CFG_FL 4
2322#define ISP_CFG_F 8
2323
2324 uint8_t operating_mode;
2325#define LOOP 0
2326#define P2P 1
2327#define LOOP_P2P 2
2328#define P2P_LOOP 3
2329 uint8_t interrupts_on;
2330 uint32_t isp_abort_cnt;
2331
2332#define PCI_DEVICE_ID_QLOGIC_ISP2532 0x2532
2333#define PCI_DEVICE_ID_QLOGIC_ISP8432 0x8432
2334#define PCI_DEVICE_ID_QLOGIC_ISP8001 0x8001
2335 uint32_t device_type;
2336#define DT_ISP2100 BIT_0
2337#define DT_ISP2200 BIT_1
2338#define DT_ISP2300 BIT_2
2339#define DT_ISP2312 BIT_3
2340#define DT_ISP2322 BIT_4
2341#define DT_ISP6312 BIT_5
2342#define DT_ISP6322 BIT_6
2343#define DT_ISP2422 BIT_7
2344#define DT_ISP2432 BIT_8
2345#define DT_ISP5422 BIT_9
2346#define DT_ISP5432 BIT_10
2347#define DT_ISP2532 BIT_11
2348#define DT_ISP8432 BIT_12
2349#define DT_ISP8001 BIT_13
2350#define DT_ISP_LAST (DT_ISP8001 << 1)
2351
2352#define DT_IIDMA BIT_26
2353#define DT_FWI2 BIT_27
2354#define DT_ZIO_SUPPORTED BIT_28
2355#define DT_OEM_001 BIT_29
2356#define DT_ISP2200A BIT_30
2357#define DT_EXTENDED_IDS BIT_31
2358#define DT_MASK(ha) ((ha)->device_type & (DT_ISP_LAST - 1))
2359#define IS_QLA2100(ha) (DT_MASK(ha) & DT_ISP2100)
2360#define IS_QLA2200(ha) (DT_MASK(ha) & DT_ISP2200)
2361#define IS_QLA2300(ha) (DT_MASK(ha) & DT_ISP2300)
2362#define IS_QLA2312(ha) (DT_MASK(ha) & DT_ISP2312)
2363#define IS_QLA2322(ha) (DT_MASK(ha) & DT_ISP2322)
2364#define IS_QLA6312(ha) (DT_MASK(ha) & DT_ISP6312)
2365#define IS_QLA6322(ha) (DT_MASK(ha) & DT_ISP6322)
2366#define IS_QLA2422(ha) (DT_MASK(ha) & DT_ISP2422)
2367#define IS_QLA2432(ha) (DT_MASK(ha) & DT_ISP2432)
2368#define IS_QLA5422(ha) (DT_MASK(ha) & DT_ISP5422)
2369#define IS_QLA5432(ha) (DT_MASK(ha) & DT_ISP5432)
2370#define IS_QLA2532(ha) (DT_MASK(ha) & DT_ISP2532)
2371#define IS_QLA8432(ha) (DT_MASK(ha) & DT_ISP8432)
2372#define IS_QLA8001(ha) (DT_MASK(ha) & DT_ISP8001)
2373
2374#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
2375 IS_QLA6312(ha) || IS_QLA6322(ha))
2376#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
2377#define IS_QLA54XX(ha) (IS_QLA5422(ha) || IS_QLA5432(ha))
2378#define IS_QLA25XX(ha) (IS_QLA2532(ha))
2379#define IS_QLA84XX(ha) (IS_QLA8432(ha))
2380#define IS_QLA24XX_TYPE(ha) (IS_QLA24XX(ha) || IS_QLA54XX(ha) || \
2381 IS_QLA84XX(ha))
2382#define IS_QLA81XX(ha) (IS_QLA8001(ha))
2383#define IS_QLA2XXX_MIDTYPE(ha) (IS_QLA24XX(ha) || IS_QLA84XX(ha) || \
2384 IS_QLA25XX(ha) || IS_QLA81XX(ha))
2385#define IS_NOPOLLING_TYPE(ha) ((IS_QLA25XX(ha) || IS_QLA81XX(ha)) && \
2386 (ha)->flags.msix_enabled)
2387#define IS_FAC_REQUIRED(ha) (IS_QLA81XX(ha))
2388#define IS_NOCACHE_VPD_TYPE(ha) (IS_QLA81XX(ha))
2389#define IS_ALOGIO_CAPABLE(ha) (IS_QLA23XX(ha) || IS_FWI2_CAPABLE(ha))
2390
2391#define IS_IIDMA_CAPABLE(ha) ((ha)->device_type & DT_IIDMA)
2392#define IS_FWI2_CAPABLE(ha) ((ha)->device_type & DT_FWI2)
2393#define IS_ZIO_SUPPORTED(ha) ((ha)->device_type & DT_ZIO_SUPPORTED)
2394#define IS_OEM_001(ha) ((ha)->device_type & DT_OEM_001)
2395#define HAS_EXTENDED_IDS(ha) ((ha)->device_type & DT_EXTENDED_IDS)
2396
2397
2398 uint8_t serial0;
2399 uint8_t serial1;
2400 uint8_t serial2;
2401
2402
2403#define MAX_NVRAM_SIZE 4096
2404#define VPD_OFFSET MAX_NVRAM_SIZE / 2
2405 uint16_t nvram_size;
2406 uint16_t nvram_base;
2407 void *nvram;
2408 uint16_t vpd_size;
2409 uint16_t vpd_base;
2410 void *vpd;
2411
2412 uint16_t loop_reset_delay;
2413 uint8_t retry_count;
2414 uint8_t login_timeout;
2415 uint16_t r_a_tov;
2416 int port_down_retry_count;
2417 uint8_t mbx_count;
2418
2419 uint32_t login_retry_count;
2420
2421 ms_iocb_entry_t *ms_iocb;
2422 dma_addr_t ms_iocb_dma;
2423 struct ct_sns_pkt *ct_sns;
2424 dma_addr_t ct_sns_dma;
2425
2426 struct sns_cmd_pkt *sns_cmd;
2427 dma_addr_t sns_cmd_dma;
2428
2429#define SFP_DEV_SIZE 256
2430#define SFP_BLOCK_SIZE 64
2431 void *sfp_data;
2432 dma_addr_t sfp_data_dma;
2433
2434 uint8_t *edc_data;
2435 dma_addr_t edc_data_dma;
2436 uint16_t edc_data_len;
2437
2438#define XGMAC_DATA_SIZE PAGE_SIZE
2439 void *xgmac_data;
2440 dma_addr_t xgmac_data_dma;
2441
2442#define DCBX_TLV_DATA_SIZE PAGE_SIZE
2443 void *dcbx_tlv;
2444 dma_addr_t dcbx_tlv_dma;
2445
2446 struct task_struct *dpc_thread;
2447 uint8_t dpc_active;
2448
2449 dma_addr_t gid_list_dma;
2450 struct gid_list_info *gid_list;
2451 int gid_list_info_size;
2452
2453
2454#define DMA_POOL_SIZE 256
2455 struct dma_pool *s_dma_pool;
2456
2457 dma_addr_t init_cb_dma;
2458 init_cb_t *init_cb;
2459 int init_cb_size;
2460 dma_addr_t ex_init_cb_dma;
2461 struct ex_init_cb_81xx *ex_init_cb;
2462
2463
2464 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2465
2466 mbx_cmd_t *mcp;
2467 unsigned long mbx_cmd_flags;
2468#define MBX_INTERRUPT 1
2469#define MBX_INTR_WAIT 2
2470#define MBX_UPDATE_FLASH_ACTIVE 3
2471
2472 struct mutex vport_lock;
2473 struct completion mbx_cmd_comp;
2474 struct completion mbx_intr_comp;
2475
2476
2477 uint16_t fw_major_version;
2478 uint16_t fw_minor_version;
2479 uint16_t fw_subminor_version;
2480 uint16_t fw_attributes;
2481 uint32_t fw_memory_size;
2482 uint32_t fw_transfer_size;
2483 uint32_t fw_srisc_address;
2484#define RISC_START_ADDRESS_2100 0x1000
2485#define RISC_START_ADDRESS_2300 0x800
2486#define RISC_START_ADDRESS_2400 0x100000
2487 uint16_t fw_xcb_count;
2488
2489 uint16_t fw_options[16];
2490 uint8_t fw_seriallink_options[4];
2491 uint16_t fw_seriallink_options24[4];
2492
2493 uint8_t mpi_version[3];
2494 uint32_t mpi_capabilities;
2495 uint8_t phy_version[3];
2496
2497
2498 struct qla2xxx_fw_dump *fw_dump;
2499 uint32_t fw_dump_len;
2500 int fw_dumped;
2501 int fw_dump_reading;
2502 dma_addr_t eft_dma;
2503 void *eft;
2504
2505 uint32_t chain_offset;
2506 struct dentry *dfs_dir;
2507 struct dentry *dfs_fce;
2508 dma_addr_t fce_dma;
2509 void *fce;
2510 uint32_t fce_bufs;
2511 uint16_t fce_mb[8];
2512 uint64_t fce_wr, fce_rd;
2513 struct mutex fce_mutex;
2514
2515 uint32_t pci_attr;
2516 uint16_t chip_revision;
2517
2518 uint16_t product_id[4];
2519
2520 uint8_t model_number[16+1];
2521#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2522 char model_desc[80];
2523 uint8_t adapter_id[16+1];
2524
2525
2526 char *optrom_buffer;
2527 uint32_t optrom_size;
2528 int optrom_state;
2529#define QLA_SWAITING 0
2530#define QLA_SREADING 1
2531#define QLA_SWRITING 2
2532 uint32_t optrom_region_start;
2533 uint32_t optrom_region_size;
2534
2535
2536#define ROM_CODE_TYPE_BIOS 0
2537#define ROM_CODE_TYPE_FCODE 1
2538#define ROM_CODE_TYPE_EFI 3
2539 uint8_t bios_revision[2];
2540 uint8_t efi_revision[2];
2541 uint8_t fcode_revision[16];
2542 uint32_t fw_revision[4];
2543
2544
2545 uint32_t flash_conf_off;
2546 uint32_t flash_data_off;
2547 uint32_t nvram_conf_off;
2548 uint32_t nvram_data_off;
2549
2550 uint32_t fdt_wrt_disable;
2551 uint32_t fdt_erase_cmd;
2552 uint32_t fdt_block_size;
2553 uint32_t fdt_unprotect_sec_cmd;
2554 uint32_t fdt_protect_sec_cmd;
2555
2556 uint32_t flt_region_flt;
2557 uint32_t flt_region_fdt;
2558 uint32_t flt_region_boot;
2559 uint32_t flt_region_fw;
2560 uint32_t flt_region_vpd_nvram;
2561 uint32_t flt_region_vpd;
2562 uint32_t flt_region_nvram;
2563 uint32_t flt_region_npiv_conf;
2564 uint32_t flt_region_gold_fw;
2565
2566
2567 uint16_t beacon_blink_led;
2568 uint8_t beacon_color_state;
2569#define QLA_LED_GRN_ON 0x01
2570#define QLA_LED_YLW_ON 0x02
2571#define QLA_LED_ABR_ON 0x04
2572#define QLA_LED_ALL_ON 0x07
2573
2574 uint16_t zio_mode;
2575 uint16_t zio_timer;
2576 struct fc_host_statistics fc_host_stat;
2577
2578 struct qla_msix_entry *msix_entries;
2579
2580 struct list_head vp_list;
2581 unsigned long vp_idx_map[(MAX_MULTI_ID_FABRIC / 8) /
2582 sizeof(unsigned long)];
2583 uint16_t num_vhosts;
2584 uint16_t num_vsans;
2585 uint16_t max_npiv_vports;
2586 int cur_vport_count;
2587
2588 struct qla_chip_state_84xx *cs84xx;
2589 struct qla_statistics qla_stats;
2590 struct isp_operations *isp_ops;
2591 struct workqueue_struct *wq;
2592};
2593
2594
2595
2596
2597typedef struct scsi_qla_host {
2598 struct list_head list;
2599 struct list_head vp_fcports;
2600 struct list_head work_list;
2601 spinlock_t work_lock;
2602
2603
2604 struct Scsi_Host *host;
2605 unsigned long host_no;
2606 uint8_t host_str[16];
2607
2608 volatile struct {
2609 uint32_t init_done :1;
2610 uint32_t online :1;
2611 uint32_t rscn_queue_overflow :1;
2612 uint32_t reset_active :1;
2613
2614 uint32_t management_server_logged_in :1;
2615 uint32_t process_response_queue :1;
2616 } flags;
2617
2618 atomic_t loop_state;
2619#define LOOP_TIMEOUT 1
2620#define LOOP_DOWN 2
2621#define LOOP_UP 3
2622#define LOOP_UPDATE 4
2623#define LOOP_READY 5
2624#define LOOP_DEAD 6
2625
2626 unsigned long dpc_flags;
2627#define RESET_MARKER_NEEDED 0
2628#define RESET_ACTIVE 1
2629#define ISP_ABORT_NEEDED 2
2630#define ABORT_ISP_ACTIVE 3
2631#define LOOP_RESYNC_NEEDED 4
2632#define LOOP_RESYNC_ACTIVE 5
2633#define LOCAL_LOOP_UPDATE 6
2634#define RSCN_UPDATE 7
2635#define RELOGIN_NEEDED 8
2636#define REGISTER_FC4_NEEDED 9
2637#define ISP_ABORT_RETRY 10
2638#define BEACON_BLINK_NEEDED 11
2639#define REGISTER_FDMI_NEEDED 12
2640#define FCPORT_UPDATE_NEEDED 13
2641#define VP_DPC_NEEDED 14
2642#define UNLOADING 15
2643#define NPIV_CONFIG_NEEDED 16
2644
2645 uint32_t device_flags;
2646#define SWITCH_FOUND BIT_0
2647#define DFLG_NO_CABLE BIT_1
2648
2649
2650 uint16_t loop_id;
2651
2652 port_id_t d_id;
2653 uint8_t marker_needed;
2654 uint16_t mgmt_svr_loop_id;
2655
2656
2657
2658
2659 uint32_t rscn_queue[MAX_RSCN_COUNT];
2660 uint8_t rscn_in_ptr;
2661 uint8_t rscn_out_ptr;
2662
2663
2664 uint8_t loop_down_abort_time;
2665 atomic_t loop_down_timer;
2666 uint8_t link_down_timeout;
2667
2668 uint32_t timer_active;
2669 struct timer_list timer;
2670
2671 uint8_t node_name[WWN_SIZE];
2672 uint8_t port_name[WWN_SIZE];
2673 uint8_t fabric_node_name[WWN_SIZE];
2674
2675 uint16_t fcoe_vlan_id;
2676 uint16_t fcoe_fcf_idx;
2677 uint8_t fcoe_vn_port_mac[6];
2678
2679 uint32_t vp_abort_cnt;
2680
2681 struct fc_vport *fc_vport;
2682 uint16_t vp_idx;
2683
2684 unsigned long vp_flags;
2685#define VP_IDX_ACQUIRED 0
2686#define VP_CREATE_NEEDED 1
2687#define VP_BIND_NEEDED 2
2688#define VP_DELETE_NEEDED 3
2689#define VP_SCR_NEEDED 4
2690 atomic_t vp_state;
2691#define VP_OFFLINE 0
2692#define VP_ACTIVE 1
2693#define VP_FAILED 2
2694
2695 uint16_t vp_err_state;
2696 uint16_t vp_prev_err_state;
2697#define VP_ERR_UNKWN 0
2698#define VP_ERR_PORTDWN 1
2699#define VP_ERR_FAB_UNSUPPORTED 2
2700#define VP_ERR_FAB_NORESOURCES 3
2701#define VP_ERR_FAB_LOGOUT 4
2702#define VP_ERR_ADAP_NORESOURCES 5
2703 struct qla_hw_data *hw;
2704 struct req_que *req;
2705} scsi_qla_host_t;
2706
2707
2708
2709
2710#define LOOP_TRANSITION(ha) \
2711 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2712 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2713 atomic_read(&ha->loop_state) == LOOP_DOWN)
2714
2715#define qla_printk(level, ha, format, arg...) \
2716 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2717
2718
2719
2720
2721#define MBS_MASK 0x3fff
2722
2723#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2724#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2725#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2726#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2727#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2728#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2729#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2730#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2731#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2732#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2733
2734#define QLA_FUNCTION_TIMEOUT 0x100
2735#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2736#define QLA_FUNCTION_FAILED 0x102
2737#define QLA_MEMORY_ALLOC_FAILED 0x103
2738#define QLA_LOCK_TIMEOUT 0x104
2739#define QLA_ABORTED 0x105
2740#define QLA_SUSPENDED 0x106
2741#define QLA_BUSY 0x107
2742#define QLA_RSCNS_HANDLED 0x108
2743#define QLA_ALREADY_REGISTERED 0x109
2744
2745#define NVRAM_DELAY() udelay(10)
2746
2747#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2748
2749
2750
2751
2752#define OPTROM_SIZE_2300 0x20000
2753#define OPTROM_SIZE_2322 0x100000
2754#define OPTROM_SIZE_24XX 0x100000
2755#define OPTROM_SIZE_25XX 0x200000
2756#define OPTROM_SIZE_81XX 0x400000
2757
2758#include "qla_gbl.h"
2759#include "qla_dbg.h"
2760#include "qla_inline.h"
2761
2762#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2763
2764#endif
2765