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27#include <linux/module.h>
28#include <linux/tty.h>
29#include <linux/ioport.h>
30#include <linux/slab.h>
31#include <linux/init.h>
32#include <linux/serial.h>
33#include <linux/clk.h>
34#include <linux/console.h>
35#include <linux/sysrq.h>
36#include <linux/tty_flip.h>
37#include <linux/platform_device.h>
38#include <linux/dma-mapping.h>
39#include <linux/atmel_pdc.h>
40#include <linux/atmel_serial.h>
41
42#include <asm/io.h>
43
44#include <asm/mach/serial_at91.h>
45#include <mach/board.h>
46
47#ifdef CONFIG_ARM
48#include <mach/cpu.h>
49#include <mach/gpio.h>
50#endif
51
52#define PDC_BUFFER_SIZE 512
53
54#define PDC_RX_TIMEOUT (3 * 10)
55
56#if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57#define SUPPORT_SYSRQ
58#endif
59
60#include <linux/serial_core.h>
61
62#ifdef CONFIG_SERIAL_ATMEL_TTYAT
63
64
65
66
67#define SERIAL_ATMEL_MAJOR 204
68#define MINOR_START 154
69#define ATMEL_DEVICENAME "ttyAT"
70
71#else
72
73
74
75#define SERIAL_ATMEL_MAJOR TTY_MAJOR
76#define MINOR_START 64
77#define ATMEL_DEVICENAME "ttyS"
78
79#endif
80
81#define ATMEL_ISR_PASS_LIMIT 256
82
83
84#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
85#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
86#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
87#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
88#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
89#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
90#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
91#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
92#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
93#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
94#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
95#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
96
97
98#define UART_PUT_PTCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_PTCR)
99#define UART_GET_PTSR(port) __raw_readl((port)->membase + ATMEL_PDC_PTSR)
100
101#define UART_PUT_RPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RPR)
102#define UART_GET_RPR(port) __raw_readl((port)->membase + ATMEL_PDC_RPR)
103#define UART_PUT_RCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RCR)
104#define UART_PUT_RNPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNPR)
105#define UART_PUT_RNCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_RNCR)
106
107#define UART_PUT_TPR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TPR)
108#define UART_PUT_TCR(port,v) __raw_writel(v, (port)->membase + ATMEL_PDC_TCR)
109#define UART_GET_TCR(port) __raw_readl((port)->membase + ATMEL_PDC_TCR)
110
111static int (*atmel_open_hook)(struct uart_port *);
112static void (*atmel_close_hook)(struct uart_port *);
113
114struct atmel_dma_buffer {
115 unsigned char *buf;
116 dma_addr_t dma_addr;
117 unsigned int dma_size;
118 unsigned int ofs;
119};
120
121struct atmel_uart_char {
122 u16 status;
123 u16 ch;
124};
125
126#define ATMEL_SERIAL_RINGSIZE 1024
127
128
129
130
131struct atmel_uart_port {
132 struct uart_port uart;
133 struct clk *clk;
134 int may_wakeup;
135 u32 backup_imr;
136 int break_active;
137
138 short use_dma_rx;
139 short pdc_rx_idx;
140 struct atmel_dma_buffer pdc_rx[2];
141
142 short use_dma_tx;
143 struct atmel_dma_buffer pdc_tx;
144
145 struct tasklet_struct tasklet;
146 unsigned int irq_status;
147 unsigned int irq_status_prev;
148
149 struct circ_buf rx_ring;
150};
151
152static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
153
154#ifdef SUPPORT_SYSRQ
155static struct console atmel_console;
156#endif
157
158static inline struct atmel_uart_port *
159to_atmel_uart_port(struct uart_port *uart)
160{
161 return container_of(uart, struct atmel_uart_port, uart);
162}
163
164#ifdef CONFIG_SERIAL_ATMEL_PDC
165static bool atmel_use_dma_rx(struct uart_port *port)
166{
167 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
168
169 return atmel_port->use_dma_rx;
170}
171
172static bool atmel_use_dma_tx(struct uart_port *port)
173{
174 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
175
176 return atmel_port->use_dma_tx;
177}
178#else
179static bool atmel_use_dma_rx(struct uart_port *port)
180{
181 return false;
182}
183
184static bool atmel_use_dma_tx(struct uart_port *port)
185{
186 return false;
187}
188#endif
189
190
191
192
193static u_int atmel_tx_empty(struct uart_port *port)
194{
195 return (UART_GET_CSR(port) & ATMEL_US_TXEMPTY) ? TIOCSER_TEMT : 0;
196}
197
198
199
200
201static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
202{
203 unsigned int control = 0;
204 unsigned int mode;
205
206#ifdef CONFIG_ARCH_AT91RM9200
207 if (cpu_is_at91rm9200()) {
208
209
210
211
212 if (port->mapbase == AT91RM9200_BASE_US0) {
213 if (mctrl & TIOCM_RTS)
214 at91_set_gpio_value(AT91_PIN_PA21, 0);
215 else
216 at91_set_gpio_value(AT91_PIN_PA21, 1);
217 }
218 }
219#endif
220
221 if (mctrl & TIOCM_RTS)
222 control |= ATMEL_US_RTSEN;
223 else
224 control |= ATMEL_US_RTSDIS;
225
226 if (mctrl & TIOCM_DTR)
227 control |= ATMEL_US_DTREN;
228 else
229 control |= ATMEL_US_DTRDIS;
230
231 UART_PUT_CR(port, control);
232
233
234 mode = UART_GET_MR(port) & ~ATMEL_US_CHMODE;
235 if (mctrl & TIOCM_LOOP)
236 mode |= ATMEL_US_CHMODE_LOC_LOOP;
237 else
238 mode |= ATMEL_US_CHMODE_NORMAL;
239 UART_PUT_MR(port, mode);
240}
241
242
243
244
245static u_int atmel_get_mctrl(struct uart_port *port)
246{
247 unsigned int status, ret = 0;
248
249 status = UART_GET_CSR(port);
250
251
252
253
254 if (!(status & ATMEL_US_DCD))
255 ret |= TIOCM_CD;
256 if (!(status & ATMEL_US_CTS))
257 ret |= TIOCM_CTS;
258 if (!(status & ATMEL_US_DSR))
259 ret |= TIOCM_DSR;
260 if (!(status & ATMEL_US_RI))
261 ret |= TIOCM_RI;
262
263 return ret;
264}
265
266
267
268
269static void atmel_stop_tx(struct uart_port *port)
270{
271 if (atmel_use_dma_tx(port)) {
272
273 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
274 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
275 } else
276 UART_PUT_IDR(port, ATMEL_US_TXRDY);
277}
278
279
280
281
282static void atmel_start_tx(struct uart_port *port)
283{
284 if (atmel_use_dma_tx(port)) {
285 if (UART_GET_PTSR(port) & ATMEL_PDC_TXTEN)
286
287
288 return;
289
290 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
291
292 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
293 } else
294 UART_PUT_IER(port, ATMEL_US_TXRDY);
295}
296
297
298
299
300static void atmel_stop_rx(struct uart_port *port)
301{
302 if (atmel_use_dma_rx(port)) {
303
304 UART_PUT_PTCR(port, ATMEL_PDC_RXTDIS);
305 UART_PUT_IDR(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
306 } else
307 UART_PUT_IDR(port, ATMEL_US_RXRDY);
308}
309
310
311
312
313static void atmel_enable_ms(struct uart_port *port)
314{
315 UART_PUT_IER(port, ATMEL_US_RIIC | ATMEL_US_DSRIC
316 | ATMEL_US_DCDIC | ATMEL_US_CTSIC);
317}
318
319
320
321
322static void atmel_break_ctl(struct uart_port *port, int break_state)
323{
324 if (break_state != 0)
325 UART_PUT_CR(port, ATMEL_US_STTBRK);
326 else
327 UART_PUT_CR(port, ATMEL_US_STPBRK);
328}
329
330
331
332
333static void
334atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
335 unsigned int ch)
336{
337 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
338 struct circ_buf *ring = &atmel_port->rx_ring;
339 struct atmel_uart_char *c;
340
341 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
342
343 return;
344
345 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
346 c->status = status;
347 c->ch = ch;
348
349
350 smp_wmb();
351
352 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
353}
354
355
356
357
358static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
359{
360
361 UART_PUT_CR(port, ATMEL_US_RSTSTA);
362
363 if (status & ATMEL_US_RXBRK) {
364
365 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
366 port->icount.brk++;
367 }
368 if (status & ATMEL_US_PARE)
369 port->icount.parity++;
370 if (status & ATMEL_US_FRAME)
371 port->icount.frame++;
372 if (status & ATMEL_US_OVRE)
373 port->icount.overrun++;
374}
375
376
377
378
379static void atmel_rx_chars(struct uart_port *port)
380{
381 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
382 unsigned int status, ch;
383
384 status = UART_GET_CSR(port);
385 while (status & ATMEL_US_RXRDY) {
386 ch = UART_GET_CHAR(port);
387
388
389
390
391
392 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
393 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
394 || atmel_port->break_active)) {
395
396
397 UART_PUT_CR(port, ATMEL_US_RSTSTA);
398
399 if (status & ATMEL_US_RXBRK
400 && !atmel_port->break_active) {
401 atmel_port->break_active = 1;
402 UART_PUT_IER(port, ATMEL_US_RXBRK);
403 } else {
404
405
406
407
408
409
410
411 UART_PUT_IDR(port, ATMEL_US_RXBRK);
412 status &= ~ATMEL_US_RXBRK;
413 atmel_port->break_active = 0;
414 }
415 }
416
417 atmel_buffer_rx_char(port, status, ch);
418 status = UART_GET_CSR(port);
419 }
420
421 tasklet_schedule(&atmel_port->tasklet);
422}
423
424
425
426
427
428static void atmel_tx_chars(struct uart_port *port)
429{
430 struct circ_buf *xmit = &port->state->xmit;
431
432 if (port->x_char && UART_GET_CSR(port) & ATMEL_US_TXRDY) {
433 UART_PUT_CHAR(port, port->x_char);
434 port->icount.tx++;
435 port->x_char = 0;
436 }
437 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
438 return;
439
440 while (UART_GET_CSR(port) & ATMEL_US_TXRDY) {
441 UART_PUT_CHAR(port, xmit->buf[xmit->tail]);
442 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
443 port->icount.tx++;
444 if (uart_circ_empty(xmit))
445 break;
446 }
447
448 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
449 uart_write_wakeup(port);
450
451 if (!uart_circ_empty(xmit))
452 UART_PUT_IER(port, ATMEL_US_TXRDY);
453}
454
455
456
457
458static void
459atmel_handle_receive(struct uart_port *port, unsigned int pending)
460{
461 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
462
463 if (atmel_use_dma_rx(port)) {
464
465
466
467
468
469
470
471 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
472 UART_PUT_IDR(port, (ATMEL_US_ENDRX
473 | ATMEL_US_TIMEOUT));
474 tasklet_schedule(&atmel_port->tasklet);
475 }
476
477 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
478 ATMEL_US_FRAME | ATMEL_US_PARE))
479 atmel_pdc_rxerr(port, pending);
480 }
481
482
483 if (pending & ATMEL_US_RXRDY)
484 atmel_rx_chars(port);
485 else if (pending & ATMEL_US_RXBRK) {
486
487
488
489
490 UART_PUT_CR(port, ATMEL_US_RSTSTA);
491 UART_PUT_IDR(port, ATMEL_US_RXBRK);
492 atmel_port->break_active = 0;
493 }
494}
495
496
497
498
499static void
500atmel_handle_transmit(struct uart_port *port, unsigned int pending)
501{
502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
503
504 if (atmel_use_dma_tx(port)) {
505
506 if (pending & (ATMEL_US_ENDTX | ATMEL_US_TXBUFE)) {
507 UART_PUT_IDR(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
508 tasklet_schedule(&atmel_port->tasklet);
509 }
510 } else {
511
512 if (pending & ATMEL_US_TXRDY) {
513 UART_PUT_IDR(port, ATMEL_US_TXRDY);
514 tasklet_schedule(&atmel_port->tasklet);
515 }
516 }
517}
518
519
520
521
522static void
523atmel_handle_status(struct uart_port *port, unsigned int pending,
524 unsigned int status)
525{
526 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
527
528 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
529 | ATMEL_US_CTSIC)) {
530 atmel_port->irq_status = status;
531 tasklet_schedule(&atmel_port->tasklet);
532 }
533}
534
535
536
537
538static irqreturn_t atmel_interrupt(int irq, void *dev_id)
539{
540 struct uart_port *port = dev_id;
541 unsigned int status, pending, pass_counter = 0;
542
543 do {
544 status = UART_GET_CSR(port);
545 pending = status & UART_GET_IMR(port);
546 if (!pending)
547 break;
548
549 atmel_handle_receive(port, pending);
550 atmel_handle_status(port, pending, status);
551 atmel_handle_transmit(port, pending);
552 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
553
554 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
555}
556
557
558
559
560static void atmel_tx_dma(struct uart_port *port)
561{
562 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
563 struct circ_buf *xmit = &port->state->xmit;
564 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
565 int count;
566
567
568 if (UART_GET_TCR(port))
569 return;
570
571 xmit->tail += pdc->ofs;
572 xmit->tail &= UART_XMIT_SIZE - 1;
573
574 port->icount.tx += pdc->ofs;
575 pdc->ofs = 0;
576
577
578
579
580 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
581
582 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
583 dma_sync_single_for_device(port->dev,
584 pdc->dma_addr,
585 pdc->dma_size,
586 DMA_TO_DEVICE);
587
588 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
589 pdc->ofs = count;
590
591 UART_PUT_TPR(port, pdc->dma_addr + xmit->tail);
592 UART_PUT_TCR(port, count);
593
594 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
595 UART_PUT_IER(port, ATMEL_US_ENDTX | ATMEL_US_TXBUFE);
596 }
597
598 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
599 uart_write_wakeup(port);
600}
601
602static void atmel_rx_from_ring(struct uart_port *port)
603{
604 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
605 struct circ_buf *ring = &atmel_port->rx_ring;
606 unsigned int flg;
607 unsigned int status;
608
609 while (ring->head != ring->tail) {
610 struct atmel_uart_char c;
611
612
613 smp_rmb();
614
615 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
616
617 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
618
619 port->icount.rx++;
620 status = c.status;
621 flg = TTY_NORMAL;
622
623
624
625
626
627 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
628 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
629 if (status & ATMEL_US_RXBRK) {
630
631 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
632
633 port->icount.brk++;
634 if (uart_handle_break(port))
635 continue;
636 }
637 if (status & ATMEL_US_PARE)
638 port->icount.parity++;
639 if (status & ATMEL_US_FRAME)
640 port->icount.frame++;
641 if (status & ATMEL_US_OVRE)
642 port->icount.overrun++;
643
644 status &= port->read_status_mask;
645
646 if (status & ATMEL_US_RXBRK)
647 flg = TTY_BREAK;
648 else if (status & ATMEL_US_PARE)
649 flg = TTY_PARITY;
650 else if (status & ATMEL_US_FRAME)
651 flg = TTY_FRAME;
652 }
653
654
655 if (uart_handle_sysrq_char(port, c.ch))
656 continue;
657
658 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
659 }
660
661
662
663
664
665 spin_unlock(&port->lock);
666 tty_flip_buffer_push(port->state->port.tty);
667 spin_lock(&port->lock);
668}
669
670static void atmel_rx_from_dma(struct uart_port *port)
671{
672 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
673 struct tty_struct *tty = port->state->port.tty;
674 struct atmel_dma_buffer *pdc;
675 int rx_idx = atmel_port->pdc_rx_idx;
676 unsigned int head;
677 unsigned int tail;
678 unsigned int count;
679
680 do {
681
682 UART_PUT_CR(port, ATMEL_US_STTTO);
683
684 pdc = &atmel_port->pdc_rx[rx_idx];
685 head = UART_GET_RPR(port) - pdc->dma_addr;
686 tail = pdc->ofs;
687
688
689
690
691
692
693
694
695
696
697
698 head = min(head, pdc->dma_size);
699
700 if (likely(head != tail)) {
701 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
702 pdc->dma_size, DMA_FROM_DEVICE);
703
704
705
706
707
708
709
710 count = head - tail;
711
712 tty_insert_flip_string(tty, pdc->buf + pdc->ofs, count);
713
714 dma_sync_single_for_device(port->dev, pdc->dma_addr,
715 pdc->dma_size, DMA_FROM_DEVICE);
716
717 port->icount.rx += count;
718 pdc->ofs = head;
719 }
720
721
722
723
724
725 if (head >= pdc->dma_size) {
726 pdc->ofs = 0;
727 UART_PUT_RNPR(port, pdc->dma_addr);
728 UART_PUT_RNCR(port, pdc->dma_size);
729
730 rx_idx = !rx_idx;
731 atmel_port->pdc_rx_idx = rx_idx;
732 }
733 } while (head >= pdc->dma_size);
734
735
736
737
738
739 spin_unlock(&port->lock);
740 tty_flip_buffer_push(tty);
741 spin_lock(&port->lock);
742
743 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
744}
745
746
747
748
749static void atmel_tasklet_func(unsigned long data)
750{
751 struct uart_port *port = (struct uart_port *)data;
752 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
753 unsigned int status;
754 unsigned int status_change;
755
756
757 spin_lock(&port->lock);
758
759 if (atmel_use_dma_tx(port))
760 atmel_tx_dma(port);
761 else
762 atmel_tx_chars(port);
763
764 status = atmel_port->irq_status;
765 status_change = status ^ atmel_port->irq_status_prev;
766
767 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
768 | ATMEL_US_DCD | ATMEL_US_CTS)) {
769
770 if (status_change & ATMEL_US_RI)
771 port->icount.rng++;
772 if (status_change & ATMEL_US_DSR)
773 port->icount.dsr++;
774 if (status_change & ATMEL_US_DCD)
775 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
776 if (status_change & ATMEL_US_CTS)
777 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
778
779 wake_up_interruptible(&port->state->port.delta_msr_wait);
780
781 atmel_port->irq_status_prev = status;
782 }
783
784 if (atmel_use_dma_rx(port))
785 atmel_rx_from_dma(port);
786 else
787 atmel_rx_from_ring(port);
788
789 spin_unlock(&port->lock);
790}
791
792
793
794
795static int atmel_startup(struct uart_port *port)
796{
797 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
798 struct tty_struct *tty = port->state->port.tty;
799 int retval;
800
801
802
803
804
805
806 UART_PUT_IDR(port, -1);
807
808
809
810
811 retval = request_irq(port->irq, atmel_interrupt, IRQF_SHARED,
812 tty ? tty->name : "atmel_serial", port);
813 if (retval) {
814 printk("atmel_serial: atmel_startup - Can't get irq\n");
815 return retval;
816 }
817
818
819
820
821 if (atmel_use_dma_rx(port)) {
822 int i;
823
824 for (i = 0; i < 2; i++) {
825 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
826
827 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
828 if (pdc->buf == NULL) {
829 if (i != 0) {
830 dma_unmap_single(port->dev,
831 atmel_port->pdc_rx[0].dma_addr,
832 PDC_BUFFER_SIZE,
833 DMA_FROM_DEVICE);
834 kfree(atmel_port->pdc_rx[0].buf);
835 }
836 free_irq(port->irq, port);
837 return -ENOMEM;
838 }
839 pdc->dma_addr = dma_map_single(port->dev,
840 pdc->buf,
841 PDC_BUFFER_SIZE,
842 DMA_FROM_DEVICE);
843 pdc->dma_size = PDC_BUFFER_SIZE;
844 pdc->ofs = 0;
845 }
846
847 atmel_port->pdc_rx_idx = 0;
848
849 UART_PUT_RPR(port, atmel_port->pdc_rx[0].dma_addr);
850 UART_PUT_RCR(port, PDC_BUFFER_SIZE);
851
852 UART_PUT_RNPR(port, atmel_port->pdc_rx[1].dma_addr);
853 UART_PUT_RNCR(port, PDC_BUFFER_SIZE);
854 }
855 if (atmel_use_dma_tx(port)) {
856 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
857 struct circ_buf *xmit = &port->state->xmit;
858
859 pdc->buf = xmit->buf;
860 pdc->dma_addr = dma_map_single(port->dev,
861 pdc->buf,
862 UART_XMIT_SIZE,
863 DMA_TO_DEVICE);
864 pdc->dma_size = UART_XMIT_SIZE;
865 pdc->ofs = 0;
866 }
867
868
869
870
871
872 if (atmel_open_hook) {
873 retval = atmel_open_hook(port);
874 if (retval) {
875 free_irq(port->irq, port);
876 return retval;
877 }
878 }
879
880
881 atmel_port->irq_status_prev = UART_GET_CSR(port);
882 atmel_port->irq_status = atmel_port->irq_status_prev;
883
884
885
886
887 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
888
889 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
890
891 if (atmel_use_dma_rx(port)) {
892
893 UART_PUT_RTOR(port, PDC_RX_TIMEOUT);
894 UART_PUT_CR(port, ATMEL_US_STTTO);
895
896 UART_PUT_IER(port, ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
897
898 UART_PUT_PTCR(port, ATMEL_PDC_RXTEN);
899 } else {
900
901 UART_PUT_IER(port, ATMEL_US_RXRDY);
902 }
903
904 return 0;
905}
906
907
908
909
910static void atmel_shutdown(struct uart_port *port)
911{
912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
913
914
915
916 atmel_stop_rx(port);
917 atmel_stop_tx(port);
918
919
920
921
922 if (atmel_use_dma_rx(port)) {
923 int i;
924
925 for (i = 0; i < 2; i++) {
926 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
927
928 dma_unmap_single(port->dev,
929 pdc->dma_addr,
930 pdc->dma_size,
931 DMA_FROM_DEVICE);
932 kfree(pdc->buf);
933 }
934 }
935 if (atmel_use_dma_tx(port)) {
936 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
937
938 dma_unmap_single(port->dev,
939 pdc->dma_addr,
940 pdc->dma_size,
941 DMA_TO_DEVICE);
942 }
943
944
945
946
947 UART_PUT_CR(port, ATMEL_US_RSTSTA);
948 UART_PUT_IDR(port, -1);
949
950
951
952
953 free_irq(port->irq, port);
954
955
956
957
958
959 if (atmel_close_hook)
960 atmel_close_hook(port);
961}
962
963
964
965
966
967static void atmel_flush_buffer(struct uart_port *port)
968{
969 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
970
971 if (atmel_use_dma_tx(port)) {
972 UART_PUT_TCR(port, 0);
973 atmel_port->pdc_tx.ofs = 0;
974 }
975}
976
977
978
979
980static void atmel_serial_pm(struct uart_port *port, unsigned int state,
981 unsigned int oldstate)
982{
983 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
984
985 switch (state) {
986 case 0:
987
988
989
990
991 clk_enable(atmel_port->clk);
992
993
994 UART_PUT_IER(port, atmel_port->backup_imr);
995 break;
996 case 3:
997
998 atmel_port->backup_imr = UART_GET_IMR(port);
999 UART_PUT_IDR(port, -1);
1000
1001
1002
1003
1004
1005 clk_disable(atmel_port->clk);
1006 break;
1007 default:
1008 printk(KERN_ERR "atmel_serial: unknown pm %d\n", state);
1009 }
1010}
1011
1012
1013
1014
1015static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
1016 struct ktermios *old)
1017{
1018 unsigned long flags;
1019 unsigned int mode, imr, quot, baud;
1020
1021
1022 mode = UART_GET_MR(port) & ~(ATMEL_US_USCLKS | ATMEL_US_CHRL
1023 | ATMEL_US_NBSTOP | ATMEL_US_PAR
1024 | ATMEL_US_USMODE);
1025
1026 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1027 quot = uart_get_divisor(port, baud);
1028
1029 if (quot > 65535) {
1030 quot /= 8;
1031 mode |= ATMEL_US_USCLKS_MCK_DIV8;
1032 }
1033
1034
1035 switch (termios->c_cflag & CSIZE) {
1036 case CS5:
1037 mode |= ATMEL_US_CHRL_5;
1038 break;
1039 case CS6:
1040 mode |= ATMEL_US_CHRL_6;
1041 break;
1042 case CS7:
1043 mode |= ATMEL_US_CHRL_7;
1044 break;
1045 default:
1046 mode |= ATMEL_US_CHRL_8;
1047 break;
1048 }
1049
1050
1051 if (termios->c_cflag & CSTOPB)
1052 mode |= ATMEL_US_NBSTOP_2;
1053
1054
1055 if (termios->c_cflag & PARENB) {
1056
1057 if (termios->c_cflag & CMSPAR) {
1058 if (termios->c_cflag & PARODD)
1059 mode |= ATMEL_US_PAR_MARK;
1060 else
1061 mode |= ATMEL_US_PAR_SPACE;
1062 } else if (termios->c_cflag & PARODD)
1063 mode |= ATMEL_US_PAR_ODD;
1064 else
1065 mode |= ATMEL_US_PAR_EVEN;
1066 } else
1067 mode |= ATMEL_US_PAR_NONE;
1068
1069
1070 if (termios->c_cflag & CRTSCTS)
1071 mode |= ATMEL_US_USMODE_HWHS;
1072 else
1073 mode |= ATMEL_US_USMODE_NORMAL;
1074
1075 spin_lock_irqsave(&port->lock, flags);
1076
1077 port->read_status_mask = ATMEL_US_OVRE;
1078 if (termios->c_iflag & INPCK)
1079 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1080 if (termios->c_iflag & (BRKINT | PARMRK))
1081 port->read_status_mask |= ATMEL_US_RXBRK;
1082
1083 if (atmel_use_dma_rx(port))
1084
1085 UART_PUT_IER(port, port->read_status_mask);
1086
1087
1088
1089
1090 port->ignore_status_mask = 0;
1091 if (termios->c_iflag & IGNPAR)
1092 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
1093 if (termios->c_iflag & IGNBRK) {
1094 port->ignore_status_mask |= ATMEL_US_RXBRK;
1095
1096
1097
1098
1099 if (termios->c_iflag & IGNPAR)
1100 port->ignore_status_mask |= ATMEL_US_OVRE;
1101 }
1102
1103
1104
1105 uart_update_timeout(port, termios->c_cflag, baud);
1106
1107
1108
1109
1110
1111
1112 imr = UART_GET_IMR(port);
1113 UART_PUT_IDR(port, -1);
1114
1115
1116 UART_PUT_CR(port, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
1117
1118
1119 UART_PUT_MR(port, mode);
1120
1121
1122 UART_PUT_BRGR(port, quot);
1123 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1124 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1125
1126
1127 UART_PUT_IER(port, imr);
1128
1129
1130 if (UART_ENABLE_MS(port, termios->c_cflag))
1131 port->ops->enable_ms(port);
1132
1133 spin_unlock_irqrestore(&port->lock, flags);
1134}
1135
1136
1137
1138
1139static const char *atmel_type(struct uart_port *port)
1140{
1141 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
1142}
1143
1144
1145
1146
1147static void atmel_release_port(struct uart_port *port)
1148{
1149 struct platform_device *pdev = to_platform_device(port->dev);
1150 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1151
1152 release_mem_region(port->mapbase, size);
1153
1154 if (port->flags & UPF_IOREMAP) {
1155 iounmap(port->membase);
1156 port->membase = NULL;
1157 }
1158}
1159
1160
1161
1162
1163static int atmel_request_port(struct uart_port *port)
1164{
1165 struct platform_device *pdev = to_platform_device(port->dev);
1166 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
1167
1168 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
1169 return -EBUSY;
1170
1171 if (port->flags & UPF_IOREMAP) {
1172 port->membase = ioremap(port->mapbase, size);
1173 if (port->membase == NULL) {
1174 release_mem_region(port->mapbase, size);
1175 return -ENOMEM;
1176 }
1177 }
1178
1179 return 0;
1180}
1181
1182
1183
1184
1185static void atmel_config_port(struct uart_port *port, int flags)
1186{
1187 if (flags & UART_CONFIG_TYPE) {
1188 port->type = PORT_ATMEL;
1189 atmel_request_port(port);
1190 }
1191}
1192
1193
1194
1195
1196static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
1197{
1198 int ret = 0;
1199 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
1200 ret = -EINVAL;
1201 if (port->irq != ser->irq)
1202 ret = -EINVAL;
1203 if (ser->io_type != SERIAL_IO_MEM)
1204 ret = -EINVAL;
1205 if (port->uartclk / 16 != ser->baud_base)
1206 ret = -EINVAL;
1207 if ((void *)port->mapbase != ser->iomem_base)
1208 ret = -EINVAL;
1209 if (port->iobase != ser->port)
1210 ret = -EINVAL;
1211 if (ser->hub6 != 0)
1212 ret = -EINVAL;
1213 return ret;
1214}
1215
1216static struct uart_ops atmel_pops = {
1217 .tx_empty = atmel_tx_empty,
1218 .set_mctrl = atmel_set_mctrl,
1219 .get_mctrl = atmel_get_mctrl,
1220 .stop_tx = atmel_stop_tx,
1221 .start_tx = atmel_start_tx,
1222 .stop_rx = atmel_stop_rx,
1223 .enable_ms = atmel_enable_ms,
1224 .break_ctl = atmel_break_ctl,
1225 .startup = atmel_startup,
1226 .shutdown = atmel_shutdown,
1227 .flush_buffer = atmel_flush_buffer,
1228 .set_termios = atmel_set_termios,
1229 .type = atmel_type,
1230 .release_port = atmel_release_port,
1231 .request_port = atmel_request_port,
1232 .config_port = atmel_config_port,
1233 .verify_port = atmel_verify_port,
1234 .pm = atmel_serial_pm,
1235};
1236
1237
1238
1239
1240static void __devinit atmel_init_port(struct atmel_uart_port *atmel_port,
1241 struct platform_device *pdev)
1242{
1243 struct uart_port *port = &atmel_port->uart;
1244 struct atmel_uart_data *data = pdev->dev.platform_data;
1245
1246 port->iotype = UPIO_MEM;
1247 port->flags = UPF_BOOT_AUTOCONF;
1248 port->ops = &atmel_pops;
1249 port->fifosize = 1;
1250 port->line = pdev->id;
1251 port->dev = &pdev->dev;
1252
1253 port->mapbase = pdev->resource[0].start;
1254 port->irq = pdev->resource[1].start;
1255
1256 tasklet_init(&atmel_port->tasklet, atmel_tasklet_func,
1257 (unsigned long)port);
1258
1259 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
1260
1261 if (data->regs)
1262
1263 port->membase = data->regs;
1264 else {
1265 port->flags |= UPF_IOREMAP;
1266 port->membase = NULL;
1267 }
1268
1269
1270 if (!atmel_port->clk) {
1271 atmel_port->clk = clk_get(&pdev->dev, "usart");
1272 clk_enable(atmel_port->clk);
1273 port->uartclk = clk_get_rate(atmel_port->clk);
1274 clk_disable(atmel_port->clk);
1275
1276 }
1277
1278 atmel_port->use_dma_rx = data->use_dma_rx;
1279 atmel_port->use_dma_tx = data->use_dma_tx;
1280 if (atmel_use_dma_tx(port))
1281 port->fifosize = PDC_BUFFER_SIZE;
1282}
1283
1284
1285
1286
1287void __init atmel_register_uart_fns(struct atmel_port_fns *fns)
1288{
1289 if (fns->enable_ms)
1290 atmel_pops.enable_ms = fns->enable_ms;
1291 if (fns->get_mctrl)
1292 atmel_pops.get_mctrl = fns->get_mctrl;
1293 if (fns->set_mctrl)
1294 atmel_pops.set_mctrl = fns->set_mctrl;
1295 atmel_open_hook = fns->open;
1296 atmel_close_hook = fns->close;
1297 atmel_pops.pm = fns->pm;
1298 atmel_pops.set_wake = fns->set_wake;
1299}
1300
1301#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1302static void atmel_console_putchar(struct uart_port *port, int ch)
1303{
1304 while (!(UART_GET_CSR(port) & ATMEL_US_TXRDY))
1305 cpu_relax();
1306 UART_PUT_CHAR(port, ch);
1307}
1308
1309
1310
1311
1312static void atmel_console_write(struct console *co, const char *s, u_int count)
1313{
1314 struct uart_port *port = &atmel_ports[co->index].uart;
1315 unsigned int status, imr;
1316 unsigned int pdc_tx;
1317
1318
1319
1320
1321 imr = UART_GET_IMR(port);
1322 UART_PUT_IDR(port, ATMEL_US_RXRDY | ATMEL_US_TXRDY);
1323
1324
1325 pdc_tx = UART_GET_PTSR(port) & ATMEL_PDC_TXTEN;
1326 UART_PUT_PTCR(port, ATMEL_PDC_TXTDIS);
1327
1328 uart_console_write(port, s, count, atmel_console_putchar);
1329
1330
1331
1332
1333
1334 do {
1335 status = UART_GET_CSR(port);
1336 } while (!(status & ATMEL_US_TXRDY));
1337
1338
1339 if (pdc_tx)
1340 UART_PUT_PTCR(port, ATMEL_PDC_TXTEN);
1341
1342
1343 UART_PUT_IER(port, imr);
1344}
1345
1346
1347
1348
1349
1350static void __init atmel_console_get_options(struct uart_port *port, int *baud,
1351 int *parity, int *bits)
1352{
1353 unsigned int mr, quot;
1354
1355
1356
1357
1358
1359 quot = UART_GET_BRGR(port) & ATMEL_US_CD;
1360 if (!quot)
1361 return;
1362
1363 mr = UART_GET_MR(port) & ATMEL_US_CHRL;
1364 if (mr == ATMEL_US_CHRL_8)
1365 *bits = 8;
1366 else
1367 *bits = 7;
1368
1369 mr = UART_GET_MR(port) & ATMEL_US_PAR;
1370 if (mr == ATMEL_US_PAR_EVEN)
1371 *parity = 'e';
1372 else if (mr == ATMEL_US_PAR_ODD)
1373 *parity = 'o';
1374
1375
1376
1377
1378
1379
1380
1381 *baud = port->uartclk / (16 * (quot - 1));
1382}
1383
1384static int __init atmel_console_setup(struct console *co, char *options)
1385{
1386 struct uart_port *port = &atmel_ports[co->index].uart;
1387 int baud = 115200;
1388 int bits = 8;
1389 int parity = 'n';
1390 int flow = 'n';
1391
1392 if (port->membase == NULL) {
1393
1394 return -ENODEV;
1395 }
1396
1397 clk_enable(atmel_ports[co->index].clk);
1398
1399 UART_PUT_IDR(port, -1);
1400 UART_PUT_CR(port, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1401 UART_PUT_CR(port, ATMEL_US_TXEN | ATMEL_US_RXEN);
1402
1403 if (options)
1404 uart_parse_options(options, &baud, &parity, &bits, &flow);
1405 else
1406 atmel_console_get_options(port, &baud, &parity, &bits);
1407
1408 return uart_set_options(port, co, baud, parity, bits, flow);
1409}
1410
1411static struct uart_driver atmel_uart;
1412
1413static struct console atmel_console = {
1414 .name = ATMEL_DEVICENAME,
1415 .write = atmel_console_write,
1416 .device = uart_console_device,
1417 .setup = atmel_console_setup,
1418 .flags = CON_PRINTBUFFER,
1419 .index = -1,
1420 .data = &atmel_uart,
1421};
1422
1423#define ATMEL_CONSOLE_DEVICE (&atmel_console)
1424
1425
1426
1427
1428static int __init atmel_console_init(void)
1429{
1430 if (atmel_default_console_device) {
1431 add_preferred_console(ATMEL_DEVICENAME,
1432 atmel_default_console_device->id, NULL);
1433 atmel_init_port(&atmel_ports[atmel_default_console_device->id],
1434 atmel_default_console_device);
1435 register_console(&atmel_console);
1436 }
1437
1438 return 0;
1439}
1440
1441console_initcall(atmel_console_init);
1442
1443
1444
1445
1446static int __init atmel_late_console_init(void)
1447{
1448 if (atmel_default_console_device
1449 && !(atmel_console.flags & CON_ENABLED))
1450 register_console(&atmel_console);
1451
1452 return 0;
1453}
1454
1455core_initcall(atmel_late_console_init);
1456
1457static inline bool atmel_is_console_port(struct uart_port *port)
1458{
1459 return port->cons && port->cons->index == port->line;
1460}
1461
1462#else
1463#define ATMEL_CONSOLE_DEVICE NULL
1464
1465static inline bool atmel_is_console_port(struct uart_port *port)
1466{
1467 return false;
1468}
1469#endif
1470
1471static struct uart_driver atmel_uart = {
1472 .owner = THIS_MODULE,
1473 .driver_name = "atmel_serial",
1474 .dev_name = ATMEL_DEVICENAME,
1475 .major = SERIAL_ATMEL_MAJOR,
1476 .minor = MINOR_START,
1477 .nr = ATMEL_MAX_UART,
1478 .cons = ATMEL_CONSOLE_DEVICE,
1479};
1480
1481#ifdef CONFIG_PM
1482static bool atmel_serial_clk_will_stop(void)
1483{
1484#ifdef CONFIG_ARCH_AT91
1485 return at91_suspend_entering_slow_clock();
1486#else
1487 return false;
1488#endif
1489}
1490
1491static int atmel_serial_suspend(struct platform_device *pdev,
1492 pm_message_t state)
1493{
1494 struct uart_port *port = platform_get_drvdata(pdev);
1495 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1496
1497 if (atmel_is_console_port(port) && console_suspend_enabled) {
1498
1499 while (!(UART_GET_CSR(port) & ATMEL_US_TXEMPTY))
1500 cpu_relax();
1501 }
1502
1503
1504 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
1505 if (atmel_serial_clk_will_stop())
1506 device_set_wakeup_enable(&pdev->dev, 0);
1507
1508 uart_suspend_port(&atmel_uart, port);
1509
1510 return 0;
1511}
1512
1513static int atmel_serial_resume(struct platform_device *pdev)
1514{
1515 struct uart_port *port = platform_get_drvdata(pdev);
1516 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1517
1518 uart_resume_port(&atmel_uart, port);
1519 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
1520
1521 return 0;
1522}
1523#else
1524#define atmel_serial_suspend NULL
1525#define atmel_serial_resume NULL
1526#endif
1527
1528static int __devinit atmel_serial_probe(struct platform_device *pdev)
1529{
1530 struct atmel_uart_port *port;
1531 void *data;
1532 int ret;
1533
1534 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
1535
1536 port = &atmel_ports[pdev->id];
1537 port->backup_imr = 0;
1538
1539 atmel_init_port(port, pdev);
1540
1541 if (!atmel_use_dma_rx(&port->uart)) {
1542 ret = -ENOMEM;
1543 data = kmalloc(sizeof(struct atmel_uart_char)
1544 * ATMEL_SERIAL_RINGSIZE, GFP_KERNEL);
1545 if (!data)
1546 goto err_alloc_ring;
1547 port->rx_ring.buf = data;
1548 }
1549
1550 ret = uart_add_one_port(&atmel_uart, &port->uart);
1551 if (ret)
1552 goto err_add_port;
1553
1554#ifdef CONFIG_SERIAL_ATMEL_CONSOLE
1555 if (atmel_is_console_port(&port->uart)
1556 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
1557
1558
1559
1560
1561 clk_disable(port->clk);
1562 }
1563#endif
1564
1565 device_init_wakeup(&pdev->dev, 1);
1566 platform_set_drvdata(pdev, port);
1567
1568 return 0;
1569
1570err_add_port:
1571 kfree(port->rx_ring.buf);
1572 port->rx_ring.buf = NULL;
1573err_alloc_ring:
1574 if (!atmel_is_console_port(&port->uart)) {
1575 clk_put(port->clk);
1576 port->clk = NULL;
1577 }
1578
1579 return ret;
1580}
1581
1582static int __devexit atmel_serial_remove(struct platform_device *pdev)
1583{
1584 struct uart_port *port = platform_get_drvdata(pdev);
1585 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1586 int ret = 0;
1587
1588 device_init_wakeup(&pdev->dev, 0);
1589 platform_set_drvdata(pdev, NULL);
1590
1591 ret = uart_remove_one_port(&atmel_uart, port);
1592
1593 tasklet_kill(&atmel_port->tasklet);
1594 kfree(atmel_port->rx_ring.buf);
1595
1596
1597
1598 clk_put(atmel_port->clk);
1599
1600 return ret;
1601}
1602
1603static struct platform_driver atmel_serial_driver = {
1604 .probe = atmel_serial_probe,
1605 .remove = __devexit_p(atmel_serial_remove),
1606 .suspend = atmel_serial_suspend,
1607 .resume = atmel_serial_resume,
1608 .driver = {
1609 .name = "atmel_usart",
1610 .owner = THIS_MODULE,
1611 },
1612};
1613
1614static int __init atmel_serial_init(void)
1615{
1616 int ret;
1617
1618 ret = uart_register_driver(&atmel_uart);
1619 if (ret)
1620 return ret;
1621
1622 ret = platform_driver_register(&atmel_serial_driver);
1623 if (ret)
1624 uart_unregister_driver(&atmel_uart);
1625
1626 return ret;
1627}
1628
1629static void __exit atmel_serial_exit(void)
1630{
1631 platform_driver_unregister(&atmel_serial_driver);
1632 uart_unregister_driver(&atmel_uart);
1633}
1634
1635module_init(atmel_serial_init);
1636module_exit(atmel_serial_exit);
1637
1638MODULE_AUTHOR("Rick Bronson");
1639MODULE_DESCRIPTION("Atmel AT91 / AT32 serial port driver");
1640MODULE_LICENSE("GPL");
1641MODULE_ALIAS("platform:atmel_usart");
1642