LXR linux/drivers/serial/ip22zilog.h

   1#ifndef _IP22_ZILOG_H
   2#define _IP22_ZILOG_H
   3
   4#include <asm/byteorder.h>
   5
   6struct zilog_channel {
   7#ifdef __BIG_ENDIAN
   8        volatile unsigned char unused0[3];
   9        volatile unsigned char control;
  10        volatile unsigned char unused1[3];
  11        volatile unsigned char data;
  12#else /* __LITTLE_ENDIAN */
  13        volatile unsigned char control;
  14        volatile unsigned char unused0[3];
  15        volatile unsigned char data;
  16        volatile unsigned char unused1[3];
  17#endif
  18};
  19
  20struct zilog_layout {
  21        struct zilog_channel channelB;
  22        struct zilog_channel channelA;
  23};
  24
  25#define NUM_ZSREGS    16
  26
  27/* Conversion routines to/from brg time constants from/to bits
  28 * per second.
  29 */
  30#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
  31#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
  32
  33/* The Zilog register set */
  34
  35#define FLAG    0x7e
  36
  37/* Write Register 0 */
  38#define R0      0               /* Register selects */
  39#define R1      1
  40#define R2      2
  41#define R3      3
  42#define R4      4
  43#define R5      5
  44#define R6      6
  45#define R7      7
  46#define R8      8
  47#define R9      9
  48#define R10     10
  49#define R11     11
  50#define R12     12
  51#define R13     13
  52#define R14     14
  53#define R15     15
  54
  55#define NULLCODE        0       /* Null Code */
  56#define POINT_HIGH      0x8     /* Select upper half of registers */
  57#define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
  58#define SEND_ABORT      0x18    /* HDLC Abort */
  59#define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
  60#define RES_Tx_P        0x28    /* Reset TxINT Pending */
  61#define ERR_RES         0x30    /* Error Reset */
  62#define RES_H_IUS       0x38    /* Reset highest IUS */
  63
  64#define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
  65#define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
  66#define RES_EOM_L       0xC0    /* Reset EOM latch */
  67
  68/* Write Register 1 */
  69
  70#define EXT_INT_ENAB    0x1     /* Ext Int Enable */
  71#define TxINT_ENAB      0x2     /* Tx Int Enable */
  72#define PAR_SPEC        0x4     /* Parity is special condition */
  73
  74#define RxINT_DISAB     0       /* Rx Int Disable */
  75#define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
  76#define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
  77#define INT_ERR_Rx      0x18    /* Int on error only */
  78#define RxINT_MASK      0x18
  79
  80#define WT_RDY_RT       0x20    /* Wait/Ready on R/T */
  81#define WT_FN_RDYFN     0x40    /* Wait/FN/Ready FN */
  82#define WT_RDY_ENAB     0x80    /* Wait/Ready Enable */
  83
  84/* Write Register #2 (Interrupt Vector) */
  85
  86/* Write Register 3 */
  87
  88#define RxENAB          0x1     /* Rx Enable */
  89#define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
  90#define ADD_SM          0x4     /* Address Search Mode (SDLC) */
  91#define RxCRC_ENAB      0x8     /* Rx CRC Enable */
  92#define ENT_HM          0x10    /* Enter Hunt Mode */
  93#define AUTO_ENAB       0x20    /* Auto Enables */
  94#define Rx5             0x0     /* Rx 5 Bits/Character */
  95#define Rx7             0x40    /* Rx 7 Bits/Character */
  96#define Rx6             0x80    /* Rx 6 Bits/Character */
  97#define Rx8             0xc0    /* Rx 8 Bits/Character */
  98#define RxN_MASK        0xc0
  99
 100/* Write Register 4 */
 101
 102#define PAR_ENAB        0x1     /* Parity Enable */
 103#define PAR_EVEN        0x2     /* Parity Even/Odd* */
 104
 105#define SYNC_ENAB       0       /* Sync Modes Enable */
 106#define SB1             0x4     /* 1 stop bit/char */
 107#define SB15            0x8     /* 1.5 stop bits/char */
 108#define SB2             0xc     /* 2 stop bits/char */
 109
 110#define MONSYNC         0       /* 8 Bit Sync character */
 111#define BISYNC          0x10    /* 16 bit sync character */
 112#define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 113#define EXTSYNC         0x30    /* External Sync Mode */
 114
 115#define X1CLK           0x0     /* x1 clock mode */
 116#define X16CLK          0x40    /* x16 clock mode */
 117#define X32CLK          0x80    /* x32 clock mode */
 118#define X64CLK          0xC0    /* x64 clock mode */
 119#define XCLK_MASK       0xC0
 120
 121/* Write Register 5 */
 122
 123#define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 124#define RTS             0x2     /* RTS */
 125#define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 126#define TxENAB          0x8     /* Tx Enable */
 127#define SND_BRK         0x10    /* Send Break */
 128#define Tx5             0x0     /* Tx 5 bits (or less)/character */
 129#define Tx7             0x20    /* Tx 7 bits/character */
 130#define Tx6             0x40    /* Tx 6 bits/character */
 131#define Tx8             0x60    /* Tx 8 bits/character */
 132#define TxN_MASK        0x60
 133#define DTR             0x80    /* DTR */
 134
 135/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 136
 137/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 138
 139/* Write Register 8 (transmit buffer) */
 140
 141/* Write Register 9 (Master interrupt control) */
 142#define VIS     1       /* Vector Includes Status */
 143#define NV      2       /* No Vector */
 144#define DLC     4       /* Disable Lower Chain */
 145#define MIE     8       /* Master Interrupt Enable */
 146#define STATHI  0x10    /* Status high */
 147#define NORESET 0       /* No reset on write to R9 */
 148#define CHRB    0x40    /* Reset channel B */
 149#define CHRA    0x80    /* Reset channel A */
 150#define FHWRES  0xc0    /* Force hardware reset */
 151
 152/* Write Register 10 (misc control bits) */
 153#define BIT6    1       /* 6 bit/8bit sync */
 154#define LOOPMODE 2      /* SDLC Loop mode */
 155#define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 156#define MARKIDLE 8      /* Mark/flag on idle */
 157#define GAOP    0x10    /* Go active on poll */
 158#define NRZ     0       /* NRZ mode */
 159#define NRZI    0x20    /* NRZI mode */
 160#define FM1     0x40    /* FM1 (transition = 1) */
 161#define FM0     0x60    /* FM0 (transition = 0) */
 162#define CRCPS   0x80    /* CRC Preset I/O */
 163
 164/* Write Register 11 (Clock Mode control) */
 165#define TRxCXT  0       /* TRxC = Xtal output */
 166#define TRxCTC  1       /* TRxC = Transmit clock */
 167#define TRxCBR  2       /* TRxC = BR Generator Output */
 168#define TRxCDP  3       /* TRxC = DPLL output */
 169#define TRxCOI  4       /* TRxC O/I */
 170#define TCRTxCP 0       /* Transmit clock = RTxC pin */
 171#define TCTRxCP 8       /* Transmit clock = TRxC pin */
 172#define TCBR    0x10    /* Transmit clock = BR Generator output */
 173#define TCDPLL  0x18    /* Transmit clock = DPLL output */
 174#define RCRTxCP 0       /* Receive clock = RTxC pin */
 175#define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 176#define RCBR    0x40    /* Receive clock = BR Generator output */
 177#define RCDPLL  0x60    /* Receive clock = DPLL output */
 178#define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 179
 180/* Write Register 12 (lower byte of baud rate generator time constant) */
 181
 182/* Write Register 13 (upper byte of baud rate generator time constant) */
 183
 184/* Write Register 14 (Misc control bits) */
 185#define BRENAB  1       /* Baud rate generator enable */
 186#define BRSRC   2       /* Baud rate generator source */
 187#define DTRREQ  4       /* DTR/Request function */
 188#define AUTOECHO 8      /* Auto Echo */
 189#define LOOPBAK 0x10    /* Local loopback */
 190#define SEARCH  0x20    /* Enter search mode */
 191#define RMC     0x40    /* Reset missing clock */
 192#define DISDPLL 0x60    /* Disable DPLL */
 193#define SSBR    0x80    /* Set DPLL source = BR generator */
 194#define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 195#define SFMM    0xc0    /* Set FM mode */
 196#define SNRZI   0xe0    /* Set NRZI mode */
 197
 198/* Write Register 15 (external/status interrupt control) */
 199#define ZCIE    2       /* Zero count IE */
 200#define DCDIE   8       /* DCD IE */
 201#define SYNCIE  0x10    /* Sync/hunt IE */
 202#define CTSIE   0x20    /* CTS IE */
 203#define TxUIE   0x40    /* Tx Underrun/EOM IE */
 204#define BRKIE   0x80    /* Break/Abort IE */
 205
 206
 207/* Read Register 0 */
 208#define Rx_CH_AV        0x1     /* Rx Character Available */
 209#define ZCOUNT          0x2     /* Zero count */
 210#define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 211#define DCD             0x8     /* DCD */
 212#define SYNC            0x10    /* Sync/hunt */
 213#define CTS             0x20    /* CTS */
 214#define TxEOM           0x40    /* Tx underrun */
 215#define BRK_ABRT        0x80    /* Break/Abort */
 216
 217/* Read Register 1 */
 218#define ALL_SNT         0x1     /* All sent */
 219/* Residue Data for 8 Rx bits/char programmed */
 220#define RES3            0x8     /* 0/3 */
 221#define RES4            0x4     /* 0/4 */
 222#define RES5            0xc     /* 0/5 */
 223#define RES6            0x2     /* 0/6 */
 224#define RES7            0xa     /* 0/7 */
 225#define RES8            0x6     /* 0/8 */
 226#define RES18           0xe     /* 1/8 */
 227#define RES28           0x0     /* 2/8 */
 228/* Special Rx Condition Interrupts */
 229#define PAR_ERR         0x10    /* Parity error */
 230#define Rx_OVR          0x20    /* Rx Overrun Error */
 231#define CRC_ERR         0x40    /* CRC/Framing Error */
 232#define END_FR          0x80    /* End of Frame (SDLC) */
 233
 234/* Read Register 2 (channel b only) - Interrupt vector */
 235#define CHB_Tx_EMPTY    0x00
 236#define CHB_EXT_STAT    0x02
 237#define CHB_Rx_AVAIL    0x04
 238#define CHB_SPECIAL     0x06
 239#define CHA_Tx_EMPTY    0x08
 240#define CHA_EXT_STAT    0x0a
 241#define CHA_Rx_AVAIL    0x0c
 242#define CHA_SPECIAL     0x0e
 243#define STATUS_MASK     0x0e
 244
 245/* Read Register 3 (interrupt pending register) ch a only */
 246#define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 247#define CHBTxIP 0x2             /* Channel B Tx IP */
 248#define CHBRxIP 0x4             /* Channel B Rx IP */
 249#define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 250#define CHATxIP 0x10            /* Channel A Tx IP */
 251#define CHARxIP 0x20            /* Channel A Rx IP */
 252
 253/* Read Register 8 (receive data register) */
 254
 255/* Read Register 10  (misc status bits) */
 256#define ONLOOP  2               /* On loop */
 257#define LOOPSEND 0x10           /* Loop sending */
 258#define CLK2MIS 0x40            /* Two clocks missing */
 259#define CLK1MIS 0x80            /* One clock missing */
 260
 261/* Read Register 12 (lower byte of baud rate generator constant) */
 262
 263/* Read Register 13 (upper byte of baud rate generator constant) */
 264
 265/* Read Register 15 (value of WR 15) */
 266
 267/* Misc macros */
 268#define ZS_CLEARERR(channel)    do { writeb(ERR_RES, &channel->control); \
 269                                     udelay(5); } while(0)
 270
 271#define ZS_CLEARSTAT(channel)   do { writeb(RES_EXT_INT, &channel->control); \
 272                                     udelay(5); } while(0)
 273
 274#define ZS_CLEARFIFO(channel)   do { readb(&channel->data); \
 275                                     udelay(2); \
 276                                     readb(&channel->data); \
 277                                     udelay(2); \
 278                                     readb(&channel->data); \
 279                                     udelay(2); } while(0)
 280
 281#endif /* _IP22_ZILOG_H */
 282