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11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/errno.h>
19#include <linux/interrupt.h>
20#include <linux/platform_device.h>
21#include <linux/dma-mapping.h>
22#include <linux/spi/spi.h>
23#include <linux/workqueue.h>
24
25#include <asm/dma.h>
26#include <asm/portmux.h>
27#include <asm/bfin5xx_spi.h>
28#include <asm/cacheflush.h>
29
30#define DRV_NAME "bfin-spi"
31#define DRV_AUTHOR "Bryan Wu, Luke Yang"
32#define DRV_DESC "Blackfin on-chip SPI Controller Driver"
33#define DRV_VERSION "1.0"
34
35MODULE_AUTHOR(DRV_AUTHOR);
36MODULE_DESCRIPTION(DRV_DESC);
37MODULE_LICENSE("GPL");
38
39#define START_STATE ((void *)0)
40#define RUNNING_STATE ((void *)1)
41#define DONE_STATE ((void *)2)
42#define ERROR_STATE ((void *)-1)
43#define QUEUE_RUNNING 0
44#define QUEUE_STOPPED 1
45
46
47#define SPI_IDLE_TXVAL 0x0000
48
49struct driver_data {
50
51 struct platform_device *pdev;
52
53
54 struct spi_master *master;
55
56
57 void __iomem *regs_base;
58
59
60 u16 *pin_req;
61
62
63 struct bfin5xx_spi_master *master_info;
64
65
66 struct workqueue_struct *workqueue;
67 struct work_struct pump_messages;
68 spinlock_t lock;
69 struct list_head queue;
70 int busy;
71 int run;
72
73
74 struct tasklet_struct pump_transfers;
75
76
77 struct spi_message *cur_msg;
78 struct spi_transfer *cur_transfer;
79 struct chip_data *cur_chip;
80 size_t len_in_bytes;
81 size_t len;
82 void *tx;
83 void *tx_end;
84 void *rx;
85 void *rx_end;
86
87
88 int dma_channel;
89 int dma_mapped;
90 int dma_requested;
91 dma_addr_t rx_dma;
92 dma_addr_t tx_dma;
93
94 size_t rx_map_len;
95 size_t tx_map_len;
96 u8 n_bytes;
97 int cs_change;
98 void (*write) (struct driver_data *);
99 void (*read) (struct driver_data *);
100 void (*duplex) (struct driver_data *);
101};
102
103struct chip_data {
104 u16 ctl_reg;
105 u16 baud;
106 u16 flag;
107
108 u8 chip_select_num;
109 u8 n_bytes;
110 u8 width;
111 u8 enable_dma;
112 u8 bits_per_word;
113 u8 cs_change_per_word;
114 u16 cs_chg_udelay;
115 u32 cs_gpio;
116 u16 idle_tx_val;
117 void (*write) (struct driver_data *);
118 void (*read) (struct driver_data *);
119 void (*duplex) (struct driver_data *);
120};
121
122#define DEFINE_SPI_REG(reg, off) \
123static inline u16 read_##reg(struct driver_data *drv_data) \
124 { return bfin_read16(drv_data->regs_base + off); } \
125static inline void write_##reg(struct driver_data *drv_data, u16 v) \
126 { bfin_write16(drv_data->regs_base + off, v); }
127
128DEFINE_SPI_REG(CTRL, 0x00)
129DEFINE_SPI_REG(FLAG, 0x04)
130DEFINE_SPI_REG(STAT, 0x08)
131DEFINE_SPI_REG(TDBR, 0x0C)
132DEFINE_SPI_REG(RDBR, 0x10)
133DEFINE_SPI_REG(BAUD, 0x14)
134DEFINE_SPI_REG(SHAW, 0x18)
135
136static void bfin_spi_enable(struct driver_data *drv_data)
137{
138 u16 cr;
139
140 cr = read_CTRL(drv_data);
141 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
142}
143
144static void bfin_spi_disable(struct driver_data *drv_data)
145{
146 u16 cr;
147
148 cr = read_CTRL(drv_data);
149 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
150}
151
152
153static u16 hz_to_spi_baud(u32 speed_hz)
154{
155 u_long sclk = get_sclk();
156 u16 spi_baud = (sclk / (2 * speed_hz));
157
158 if ((sclk % (2 * speed_hz)) > 0)
159 spi_baud++;
160
161 if (spi_baud < MIN_SPI_BAUD_VAL)
162 spi_baud = MIN_SPI_BAUD_VAL;
163
164 return spi_baud;
165}
166
167static int bfin_spi_flush(struct driver_data *drv_data)
168{
169 unsigned long limit = loops_per_jiffy << 1;
170
171
172 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
173 cpu_relax();
174
175 write_STAT(drv_data, BIT_STAT_CLR);
176
177 return limit;
178}
179
180
181static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip)
182{
183 if (likely(chip->chip_select_num)) {
184 u16 flag = read_FLAG(drv_data);
185
186 flag |= chip->flag;
187 flag &= ~(chip->flag << 8);
188
189 write_FLAG(drv_data, flag);
190 } else {
191 gpio_set_value(chip->cs_gpio, 0);
192 }
193}
194
195static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
196{
197 if (likely(chip->chip_select_num)) {
198 u16 flag = read_FLAG(drv_data);
199
200 flag &= ~chip->flag;
201 flag |= (chip->flag << 8);
202
203 write_FLAG(drv_data, flag);
204 } else {
205 gpio_set_value(chip->cs_gpio, 1);
206 }
207
208
209 if (chip->cs_chg_udelay)
210 udelay(chip->cs_chg_udelay);
211}
212
213
214static void bfin_spi_restore_state(struct driver_data *drv_data)
215{
216 struct chip_data *chip = drv_data->cur_chip;
217
218
219 write_STAT(drv_data, BIT_STAT_CLR);
220 bfin_spi_disable(drv_data);
221 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
222
223
224 write_CTRL(drv_data, chip->ctl_reg);
225 write_BAUD(drv_data, chip->baud);
226
227 bfin_spi_enable(drv_data);
228 bfin_spi_cs_active(drv_data, chip);
229}
230
231
232static inline void bfin_spi_dummy_read(struct driver_data *drv_data)
233{
234 (void) read_RDBR(drv_data);
235}
236
237static void bfin_spi_null_writer(struct driver_data *drv_data)
238{
239 u8 n_bytes = drv_data->n_bytes;
240 u16 tx_val = drv_data->cur_chip->idle_tx_val;
241
242
243 bfin_spi_dummy_read(drv_data);
244
245 while (drv_data->tx < drv_data->tx_end) {
246 write_TDBR(drv_data, tx_val);
247 drv_data->tx += n_bytes;
248
249
250 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
251 cpu_relax();
252
253 bfin_spi_dummy_read(drv_data);
254 }
255}
256
257static void bfin_spi_null_reader(struct driver_data *drv_data)
258{
259 u8 n_bytes = drv_data->n_bytes;
260 u16 tx_val = drv_data->cur_chip->idle_tx_val;
261
262
263 bfin_spi_dummy_read(drv_data);
264
265 while (drv_data->rx < drv_data->rx_end) {
266 write_TDBR(drv_data, tx_val);
267 drv_data->rx += n_bytes;
268 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
269 cpu_relax();
270 bfin_spi_dummy_read(drv_data);
271 }
272}
273
274static void bfin_spi_u8_writer(struct driver_data *drv_data)
275{
276
277 bfin_spi_dummy_read(drv_data);
278
279 while (drv_data->tx < drv_data->tx_end) {
280 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
281
282
283 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
284 cpu_relax();
285
286 bfin_spi_dummy_read(drv_data);
287 }
288}
289
290static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data)
291{
292 struct chip_data *chip = drv_data->cur_chip;
293
294
295 bfin_spi_dummy_read(drv_data);
296
297 while (drv_data->tx < drv_data->tx_end) {
298 bfin_spi_cs_active(drv_data, chip);
299 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
300
301 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
302 cpu_relax();
303 bfin_spi_dummy_read(drv_data);
304 bfin_spi_cs_deactive(drv_data, chip);
305 }
306}
307
308static void bfin_spi_u8_reader(struct driver_data *drv_data)
309{
310 u16 tx_val = drv_data->cur_chip->idle_tx_val;
311
312
313 bfin_spi_dummy_read(drv_data);
314
315 while (drv_data->rx < drv_data->rx_end) {
316 write_TDBR(drv_data, tx_val);
317 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
318 cpu_relax();
319 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
320 }
321}
322
323static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data)
324{
325 struct chip_data *chip = drv_data->cur_chip;
326 u16 tx_val = chip->idle_tx_val;
327
328
329 bfin_spi_dummy_read(drv_data);
330
331 while (drv_data->rx < drv_data->rx_end) {
332 bfin_spi_cs_active(drv_data, chip);
333 write_TDBR(drv_data, tx_val);
334 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
335 cpu_relax();
336 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
337 bfin_spi_cs_deactive(drv_data, chip);
338 }
339}
340
341static void bfin_spi_u8_duplex(struct driver_data *drv_data)
342{
343
344 bfin_spi_dummy_read(drv_data);
345
346 while (drv_data->rx < drv_data->rx_end) {
347 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
348 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
349 cpu_relax();
350 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
351 }
352}
353
354static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data)
355{
356 struct chip_data *chip = drv_data->cur_chip;
357
358
359 bfin_spi_dummy_read(drv_data);
360
361 while (drv_data->rx < drv_data->rx_end) {
362 bfin_spi_cs_active(drv_data, chip);
363 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
364 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
365 cpu_relax();
366 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
367 bfin_spi_cs_deactive(drv_data, chip);
368 }
369}
370
371static void bfin_spi_u16_writer(struct driver_data *drv_data)
372{
373
374 bfin_spi_dummy_read(drv_data);
375
376 while (drv_data->tx < drv_data->tx_end) {
377 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
378 drv_data->tx += 2;
379
380
381 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
382 cpu_relax();
383
384 bfin_spi_dummy_read(drv_data);
385 }
386}
387
388static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data)
389{
390 struct chip_data *chip = drv_data->cur_chip;
391
392
393 bfin_spi_dummy_read(drv_data);
394
395 while (drv_data->tx < drv_data->tx_end) {
396 bfin_spi_cs_active(drv_data, chip);
397 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
398 drv_data->tx += 2;
399
400 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
401 cpu_relax();
402 bfin_spi_dummy_read(drv_data);
403 bfin_spi_cs_deactive(drv_data, chip);
404 }
405}
406
407static void bfin_spi_u16_reader(struct driver_data *drv_data)
408{
409 u16 tx_val = drv_data->cur_chip->idle_tx_val;
410
411
412 bfin_spi_dummy_read(drv_data);
413
414 while (drv_data->rx < drv_data->rx_end) {
415 write_TDBR(drv_data, tx_val);
416 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
417 cpu_relax();
418 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
419 drv_data->rx += 2;
420 }
421}
422
423static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data)
424{
425 struct chip_data *chip = drv_data->cur_chip;
426 u16 tx_val = chip->idle_tx_val;
427
428
429 bfin_spi_dummy_read(drv_data);
430
431 while (drv_data->rx < drv_data->rx_end) {
432 bfin_spi_cs_active(drv_data, chip);
433 write_TDBR(drv_data, tx_val);
434 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
435 cpu_relax();
436 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
437 drv_data->rx += 2;
438 bfin_spi_cs_deactive(drv_data, chip);
439 }
440}
441
442static void bfin_spi_u16_duplex(struct driver_data *drv_data)
443{
444
445 bfin_spi_dummy_read(drv_data);
446
447 while (drv_data->rx < drv_data->rx_end) {
448 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
449 drv_data->tx += 2;
450 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
451 cpu_relax();
452 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
453 drv_data->rx += 2;
454 }
455}
456
457static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data)
458{
459 struct chip_data *chip = drv_data->cur_chip;
460
461
462 bfin_spi_dummy_read(drv_data);
463
464 while (drv_data->rx < drv_data->rx_end) {
465 bfin_spi_cs_active(drv_data, chip);
466 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
467 drv_data->tx += 2;
468 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
469 cpu_relax();
470 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
471 drv_data->rx += 2;
472 bfin_spi_cs_deactive(drv_data, chip);
473 }
474}
475
476
477static void *bfin_spi_next_transfer(struct driver_data *drv_data)
478{
479 struct spi_message *msg = drv_data->cur_msg;
480 struct spi_transfer *trans = drv_data->cur_transfer;
481
482
483 if (trans->transfer_list.next != &msg->transfers) {
484 drv_data->cur_transfer =
485 list_entry(trans->transfer_list.next,
486 struct spi_transfer, transfer_list);
487 return RUNNING_STATE;
488 } else
489 return DONE_STATE;
490}
491
492
493
494
495
496static void bfin_spi_giveback(struct driver_data *drv_data)
497{
498 struct chip_data *chip = drv_data->cur_chip;
499 struct spi_transfer *last_transfer;
500 unsigned long flags;
501 struct spi_message *msg;
502
503 spin_lock_irqsave(&drv_data->lock, flags);
504 msg = drv_data->cur_msg;
505 drv_data->cur_msg = NULL;
506 drv_data->cur_transfer = NULL;
507 drv_data->cur_chip = NULL;
508 queue_work(drv_data->workqueue, &drv_data->pump_messages);
509 spin_unlock_irqrestore(&drv_data->lock, flags);
510
511 last_transfer = list_entry(msg->transfers.prev,
512 struct spi_transfer, transfer_list);
513
514 msg->state = NULL;
515
516 if (!drv_data->cs_change)
517 bfin_spi_cs_deactive(drv_data, chip);
518
519
520 if (drv_data->tx_dma != 0xFFFF)
521 bfin_spi_disable(drv_data);
522
523 if (msg->complete)
524 msg->complete(msg->context);
525}
526
527static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
528{
529 struct driver_data *drv_data = dev_id;
530 struct chip_data *chip = drv_data->cur_chip;
531 struct spi_message *msg = drv_data->cur_msg;
532 unsigned long timeout;
533 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
534 u16 spistat = read_STAT(drv_data);
535
536 dev_dbg(&drv_data->pdev->dev,
537 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
538 dmastat, spistat);
539
540 clear_dma_irqstat(drv_data->dma_channel);
541
542
543 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
544 cpu_relax();
545
546
547
548
549
550
551
552 if (drv_data->tx != NULL) {
553 while ((read_STAT(drv_data) & TXS) ||
554 (read_STAT(drv_data) & TXS))
555 cpu_relax();
556 }
557
558 dev_dbg(&drv_data->pdev->dev,
559 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
560 dmastat, read_STAT(drv_data));
561
562 timeout = jiffies + HZ;
563 while (!(read_STAT(drv_data) & SPIF))
564 if (!time_before(jiffies, timeout)) {
565 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
566 break;
567 } else
568 cpu_relax();
569
570 if ((dmastat & DMA_ERR) && (spistat & RBSY)) {
571 msg->state = ERROR_STATE;
572 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
573 } else {
574 msg->actual_length += drv_data->len_in_bytes;
575
576 if (drv_data->cs_change)
577 bfin_spi_cs_deactive(drv_data, chip);
578
579
580 msg->state = bfin_spi_next_transfer(drv_data);
581 }
582
583
584 tasklet_schedule(&drv_data->pump_transfers);
585
586
587 dev_dbg(&drv_data->pdev->dev,
588 "disable dma channel irq%d\n",
589 drv_data->dma_channel);
590 dma_disable_irq(drv_data->dma_channel);
591
592 return IRQ_HANDLED;
593}
594
595static void bfin_spi_pump_transfers(unsigned long data)
596{
597 struct driver_data *drv_data = (struct driver_data *)data;
598 struct spi_message *message = NULL;
599 struct spi_transfer *transfer = NULL;
600 struct spi_transfer *previous = NULL;
601 struct chip_data *chip = NULL;
602 u8 width;
603 u16 cr, dma_width, dma_config;
604 u32 tranf_success = 1;
605 u8 full_duplex = 0;
606
607
608 message = drv_data->cur_msg;
609 transfer = drv_data->cur_transfer;
610 chip = drv_data->cur_chip;
611
612
613
614
615
616
617 if (message->state == ERROR_STATE) {
618 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
619 message->status = -EIO;
620 bfin_spi_giveback(drv_data);
621 return;
622 }
623
624
625 if (message->state == DONE_STATE) {
626 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
627 message->status = 0;
628 bfin_spi_giveback(drv_data);
629 return;
630 }
631
632
633 if (message->state == RUNNING_STATE) {
634 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
635 previous = list_entry(transfer->transfer_list.prev,
636 struct spi_transfer, transfer_list);
637 if (previous->delay_usecs)
638 udelay(previous->delay_usecs);
639 }
640
641
642 if (bfin_spi_flush(drv_data) == 0) {
643 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
644 message->status = -EIO;
645 bfin_spi_giveback(drv_data);
646 return;
647 }
648
649 if (transfer->len == 0) {
650
651 message->state = bfin_spi_next_transfer(drv_data);
652
653 tasklet_schedule(&drv_data->pump_transfers);
654 }
655
656 if (transfer->tx_buf != NULL) {
657 drv_data->tx = (void *)transfer->tx_buf;
658 drv_data->tx_end = drv_data->tx + transfer->len;
659 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
660 transfer->tx_buf, drv_data->tx_end);
661 } else {
662 drv_data->tx = NULL;
663 }
664
665 if (transfer->rx_buf != NULL) {
666 full_duplex = transfer->tx_buf != NULL;
667 drv_data->rx = transfer->rx_buf;
668 drv_data->rx_end = drv_data->rx + transfer->len;
669 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
670 transfer->rx_buf, drv_data->rx_end);
671 } else {
672 drv_data->rx = NULL;
673 }
674
675 drv_data->rx_dma = transfer->rx_dma;
676 drv_data->tx_dma = transfer->tx_dma;
677 drv_data->len_in_bytes = transfer->len;
678 drv_data->cs_change = transfer->cs_change;
679
680
681 switch (transfer->bits_per_word) {
682 case 8:
683 drv_data->n_bytes = 1;
684 width = CFG_SPI_WORDSIZE8;
685 drv_data->read = chip->cs_change_per_word ?
686 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
687 drv_data->write = chip->cs_change_per_word ?
688 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
689 drv_data->duplex = chip->cs_change_per_word ?
690 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
691 break;
692
693 case 16:
694 drv_data->n_bytes = 2;
695 width = CFG_SPI_WORDSIZE16;
696 drv_data->read = chip->cs_change_per_word ?
697 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
698 drv_data->write = chip->cs_change_per_word ?
699 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
700 drv_data->duplex = chip->cs_change_per_word ?
701 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
702 break;
703
704 default:
705
706 drv_data->n_bytes = chip->n_bytes;
707 width = chip->width;
708 drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
709 drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader;
710 drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer;
711 break;
712 }
713 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
714 cr |= (width << 8);
715 write_CTRL(drv_data, cr);
716
717 if (width == CFG_SPI_WORDSIZE16) {
718 drv_data->len = (transfer->len) >> 1;
719 } else {
720 drv_data->len = transfer->len;
721 }
722 dev_dbg(&drv_data->pdev->dev,
723 "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n",
724 drv_data->write, chip->write, bfin_spi_null_writer);
725
726
727 message->state = RUNNING_STATE;
728 dma_config = 0;
729
730
731 if (transfer->speed_hz)
732 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
733 else
734 write_BAUD(drv_data, chip->baud);
735
736 write_STAT(drv_data, BIT_STAT_CLR);
737 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
738 if (drv_data->cs_change)
739 bfin_spi_cs_active(drv_data, chip);
740
741 dev_dbg(&drv_data->pdev->dev,
742 "now pumping a transfer: width is %d, len is %d\n",
743 width, transfer->len);
744
745
746
747
748
749
750
751 if (!full_duplex && drv_data->cur_chip->enable_dma
752 && drv_data->len > 6) {
753
754 unsigned long dma_start_addr, flags;
755
756 disable_dma(drv_data->dma_channel);
757 clear_dma_irqstat(drv_data->dma_channel);
758
759
760 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
761 set_dma_x_count(drv_data->dma_channel, drv_data->len);
762 if (width == CFG_SPI_WORDSIZE16) {
763 set_dma_x_modify(drv_data->dma_channel, 2);
764 dma_width = WDSIZE_16;
765 } else {
766 set_dma_x_modify(drv_data->dma_channel, 1);
767 dma_width = WDSIZE_8;
768 }
769
770
771 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
772 cpu_relax();
773
774
775 if (drv_data->tx_dma == 0xFFFF) {
776 dev_dbg(&drv_data->pdev->dev,
777 "doing autobuffer DMA out.\n");
778
779
780 dma_config =
781 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
782 set_dma_config(drv_data->dma_channel, dma_config);
783 set_dma_start_addr(drv_data->dma_channel,
784 (unsigned long)drv_data->tx);
785 enable_dma(drv_data->dma_channel);
786
787
788 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
789
790
791
792
793 message->status = 0;
794 bfin_spi_giveback(drv_data);
795 return;
796 }
797
798
799 dma_config = (RESTART | dma_width | DI_EN);
800 if (drv_data->rx != NULL) {
801
802 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
803 drv_data->rx, drv_data->len_in_bytes);
804
805
806 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
807 invalidate_dcache_range((unsigned long) drv_data->rx,
808 (unsigned long) (drv_data->rx +
809 drv_data->len_in_bytes));
810
811 dma_config |= WNR;
812 dma_start_addr = (unsigned long)drv_data->rx;
813 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
814
815 } else if (drv_data->tx != NULL) {
816 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
817
818
819 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
820 flush_dcache_range((unsigned long) drv_data->tx,
821 (unsigned long) (drv_data->tx +
822 drv_data->len_in_bytes));
823
824 dma_start_addr = (unsigned long)drv_data->tx;
825 cr |= BIT_CTL_TIMOD_DMA_TX;
826
827 } else
828 BUG();
829
830
831
832
833
834
835
836
837
838
839 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
840 set_dma_config(drv_data->dma_channel, dma_config);
841 local_irq_save(flags);
842 SSYNC();
843 write_CTRL(drv_data, cr);
844 enable_dma(drv_data->dma_channel);
845 dma_enable_irq(drv_data->dma_channel);
846 local_irq_restore(flags);
847
848 } else {
849
850 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
851
852
853
854
855 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
856
857 if (full_duplex) {
858
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
863
864 drv_data->duplex(drv_data);
865
866 if (drv_data->tx != drv_data->tx_end)
867 tranf_success = 0;
868 } else if (drv_data->tx != NULL) {
869
870 dev_dbg(&drv_data->pdev->dev,
871 "IO write: cr is 0x%x\n", cr);
872
873 drv_data->write(drv_data);
874
875 if (drv_data->tx != drv_data->tx_end)
876 tranf_success = 0;
877 } else if (drv_data->rx != NULL) {
878
879 dev_dbg(&drv_data->pdev->dev,
880 "IO read: cr is 0x%x\n", cr);
881
882 drv_data->read(drv_data);
883 if (drv_data->rx != drv_data->rx_end)
884 tranf_success = 0;
885 }
886
887 if (!tranf_success) {
888 dev_dbg(&drv_data->pdev->dev,
889 "IO write error!\n");
890 message->state = ERROR_STATE;
891 } else {
892
893 message->actual_length += drv_data->len_in_bytes;
894
895 message->state = bfin_spi_next_transfer(drv_data);
896 if (drv_data->cs_change)
897 bfin_spi_cs_deactive(drv_data, chip);
898 }
899
900 tasklet_schedule(&drv_data->pump_transfers);
901 }
902}
903
904
905static void bfin_spi_pump_messages(struct work_struct *work)
906{
907 struct driver_data *drv_data;
908 unsigned long flags;
909
910 drv_data = container_of(work, struct driver_data, pump_messages);
911
912
913 spin_lock_irqsave(&drv_data->lock, flags);
914 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
915
916 drv_data->busy = 0;
917 spin_unlock_irqrestore(&drv_data->lock, flags);
918 return;
919 }
920
921
922 if (drv_data->cur_msg) {
923 spin_unlock_irqrestore(&drv_data->lock, flags);
924 return;
925 }
926
927
928 drv_data->cur_msg = list_entry(drv_data->queue.next,
929 struct spi_message, queue);
930
931
932 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
933 bfin_spi_restore_state(drv_data);
934
935 list_del_init(&drv_data->cur_msg->queue);
936
937
938 drv_data->cur_msg->state = START_STATE;
939 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
940 struct spi_transfer, transfer_list);
941
942 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
943 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
944 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
945 drv_data->cur_chip->ctl_reg);
946
947 dev_dbg(&drv_data->pdev->dev,
948 "the first transfer len is %d\n",
949 drv_data->cur_transfer->len);
950
951
952 tasklet_schedule(&drv_data->pump_transfers);
953
954 drv_data->busy = 1;
955 spin_unlock_irqrestore(&drv_data->lock, flags);
956}
957
958
959
960
961
962static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
963{
964 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
965 unsigned long flags;
966
967 spin_lock_irqsave(&drv_data->lock, flags);
968
969 if (drv_data->run == QUEUE_STOPPED) {
970 spin_unlock_irqrestore(&drv_data->lock, flags);
971 return -ESHUTDOWN;
972 }
973
974 msg->actual_length = 0;
975 msg->status = -EINPROGRESS;
976 msg->state = START_STATE;
977
978 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
979 list_add_tail(&msg->queue, &drv_data->queue);
980
981 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
982 queue_work(drv_data->workqueue, &drv_data->pump_messages);
983
984 spin_unlock_irqrestore(&drv_data->lock, flags);
985
986 return 0;
987}
988
989#define MAX_SPI_SSEL 7
990
991static u16 ssel[][MAX_SPI_SSEL] = {
992 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
993 P_SPI0_SSEL4, P_SPI0_SSEL5,
994 P_SPI0_SSEL6, P_SPI0_SSEL7},
995
996 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
997 P_SPI1_SSEL4, P_SPI1_SSEL5,
998 P_SPI1_SSEL6, P_SPI1_SSEL7},
999
1000 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1001 P_SPI2_SSEL4, P_SPI2_SSEL5,
1002 P_SPI2_SSEL6, P_SPI2_SSEL7},
1003};
1004
1005
1006static int bfin_spi_setup(struct spi_device *spi)
1007{
1008 struct bfin5xx_spi_chip *chip_info = NULL;
1009 struct chip_data *chip;
1010 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1011 int ret;
1012
1013 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1014 return -EINVAL;
1015
1016
1017 chip = spi_get_ctldata(spi);
1018 if (chip == NULL) {
1019 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1020 if (!chip)
1021 return -ENOMEM;
1022
1023 chip->enable_dma = 0;
1024 chip_info = spi->controller_data;
1025 }
1026
1027
1028 if (chip_info) {
1029
1030
1031
1032
1033
1034
1035 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1036 dev_err(&spi->dev, "do not set bits in ctl_reg "
1037 "that the SPI framework manages\n");
1038 return -EINVAL;
1039 }
1040
1041 chip->enable_dma = chip_info->enable_dma != 0
1042 && drv_data->master_info->enable_dma;
1043 chip->ctl_reg = chip_info->ctl_reg;
1044 chip->bits_per_word = chip_info->bits_per_word;
1045 chip->cs_change_per_word = chip_info->cs_change_per_word;
1046 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1047 chip->cs_gpio = chip_info->cs_gpio;
1048 chip->idle_tx_val = chip_info->idle_tx_val;
1049 }
1050
1051
1052 if (spi->mode & SPI_CPOL)
1053 chip->ctl_reg |= CPOL;
1054 if (spi->mode & SPI_CPHA)
1055 chip->ctl_reg |= CPHA;
1056 if (spi->mode & SPI_LSB_FIRST)
1057 chip->ctl_reg |= LSBF;
1058
1059 chip->ctl_reg |= MSTR;
1060
1061
1062
1063
1064
1065 if (chip->enable_dma && !drv_data->dma_requested) {
1066
1067 if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) {
1068 dev_dbg(&spi->dev,
1069 "Unable to request BlackFin SPI DMA channel\n");
1070 return -ENODEV;
1071 }
1072 if (set_dma_callback(drv_data->dma_channel,
1073 bfin_spi_dma_irq_handler, drv_data) < 0) {
1074 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1075 return -EPERM;
1076 }
1077 dma_disable_irq(drv_data->dma_channel);
1078 drv_data->dma_requested = 1;
1079 }
1080
1081
1082
1083
1084
1085 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1086 chip->flag = 1 << (spi->chip_select);
1087 chip->chip_select_num = spi->chip_select;
1088
1089 if (chip->chip_select_num == 0) {
1090 ret = gpio_request(chip->cs_gpio, spi->modalias);
1091 if (ret) {
1092 if (drv_data->dma_requested)
1093 free_dma(drv_data->dma_channel);
1094 return ret;
1095 }
1096 gpio_direction_output(chip->cs_gpio, 1);
1097 }
1098
1099 switch (chip->bits_per_word) {
1100 case 8:
1101 chip->n_bytes = 1;
1102 chip->width = CFG_SPI_WORDSIZE8;
1103 chip->read = chip->cs_change_per_word ?
1104 bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader;
1105 chip->write = chip->cs_change_per_word ?
1106 bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer;
1107 chip->duplex = chip->cs_change_per_word ?
1108 bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex;
1109 break;
1110
1111 case 16:
1112 chip->n_bytes = 2;
1113 chip->width = CFG_SPI_WORDSIZE16;
1114 chip->read = chip->cs_change_per_word ?
1115 bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader;
1116 chip->write = chip->cs_change_per_word ?
1117 bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer;
1118 chip->duplex = chip->cs_change_per_word ?
1119 bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex;
1120 break;
1121
1122 default:
1123 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1124 chip->bits_per_word);
1125 if (chip_info)
1126 kfree(chip);
1127 return -ENODEV;
1128 }
1129
1130 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1131 spi->modalias, chip->width, chip->enable_dma);
1132 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1133 chip->ctl_reg, chip->flag);
1134
1135 spi_set_ctldata(spi, chip);
1136
1137 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1138 if ((chip->chip_select_num > 0)
1139 && (chip->chip_select_num <= spi->master->num_chipselect))
1140 peripheral_request(ssel[spi->master->bus_num]
1141 [chip->chip_select_num-1], spi->modalias);
1142
1143 bfin_spi_cs_deactive(drv_data, chip);
1144
1145 return 0;
1146}
1147
1148
1149
1150
1151
1152static void bfin_spi_cleanup(struct spi_device *spi)
1153{
1154 struct chip_data *chip = spi_get_ctldata(spi);
1155
1156 if (!chip)
1157 return;
1158
1159 if ((chip->chip_select_num > 0)
1160 && (chip->chip_select_num <= spi->master->num_chipselect))
1161 peripheral_free(ssel[spi->master->bus_num]
1162 [chip->chip_select_num-1]);
1163
1164 if (chip->chip_select_num == 0)
1165 gpio_free(chip->cs_gpio);
1166
1167 kfree(chip);
1168}
1169
1170static inline int bfin_spi_init_queue(struct driver_data *drv_data)
1171{
1172 INIT_LIST_HEAD(&drv_data->queue);
1173 spin_lock_init(&drv_data->lock);
1174
1175 drv_data->run = QUEUE_STOPPED;
1176 drv_data->busy = 0;
1177
1178
1179 tasklet_init(&drv_data->pump_transfers,
1180 bfin_spi_pump_transfers, (unsigned long)drv_data);
1181
1182
1183 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1184 drv_data->workqueue = create_singlethread_workqueue(
1185 dev_name(drv_data->master->dev.parent));
1186 if (drv_data->workqueue == NULL)
1187 return -EBUSY;
1188
1189 return 0;
1190}
1191
1192static inline int bfin_spi_start_queue(struct driver_data *drv_data)
1193{
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&drv_data->lock, flags);
1197
1198 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1199 spin_unlock_irqrestore(&drv_data->lock, flags);
1200 return -EBUSY;
1201 }
1202
1203 drv_data->run = QUEUE_RUNNING;
1204 drv_data->cur_msg = NULL;
1205 drv_data->cur_transfer = NULL;
1206 drv_data->cur_chip = NULL;
1207 spin_unlock_irqrestore(&drv_data->lock, flags);
1208
1209 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1210
1211 return 0;
1212}
1213
1214static inline int bfin_spi_stop_queue(struct driver_data *drv_data)
1215{
1216 unsigned long flags;
1217 unsigned limit = 500;
1218 int status = 0;
1219
1220 spin_lock_irqsave(&drv_data->lock, flags);
1221
1222
1223
1224
1225
1226
1227
1228 drv_data->run = QUEUE_STOPPED;
1229 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1230 spin_unlock_irqrestore(&drv_data->lock, flags);
1231 msleep(10);
1232 spin_lock_irqsave(&drv_data->lock, flags);
1233 }
1234
1235 if (!list_empty(&drv_data->queue) || drv_data->busy)
1236 status = -EBUSY;
1237
1238 spin_unlock_irqrestore(&drv_data->lock, flags);
1239
1240 return status;
1241}
1242
1243static inline int bfin_spi_destroy_queue(struct driver_data *drv_data)
1244{
1245 int status;
1246
1247 status = bfin_spi_stop_queue(drv_data);
1248 if (status != 0)
1249 return status;
1250
1251 destroy_workqueue(drv_data->workqueue);
1252
1253 return 0;
1254}
1255
1256static int __init bfin_spi_probe(struct platform_device *pdev)
1257{
1258 struct device *dev = &pdev->dev;
1259 struct bfin5xx_spi_master *platform_info;
1260 struct spi_master *master;
1261 struct driver_data *drv_data = 0;
1262 struct resource *res;
1263 int status = 0;
1264
1265 platform_info = dev->platform_data;
1266
1267
1268 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1269 if (!master) {
1270 dev_err(&pdev->dev, "can not alloc spi_master\n");
1271 return -ENOMEM;
1272 }
1273
1274 drv_data = spi_master_get_devdata(master);
1275 drv_data->master = master;
1276 drv_data->master_info = platform_info;
1277 drv_data->pdev = pdev;
1278 drv_data->pin_req = platform_info->pin_req;
1279
1280
1281 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1282
1283 master->bus_num = pdev->id;
1284 master->num_chipselect = platform_info->num_chipselect;
1285 master->cleanup = bfin_spi_cleanup;
1286 master->setup = bfin_spi_setup;
1287 master->transfer = bfin_spi_transfer;
1288
1289
1290 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291 if (res == NULL) {
1292 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1293 status = -ENOENT;
1294 goto out_error_get_res;
1295 }
1296
1297 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1298 if (drv_data->regs_base == NULL) {
1299 dev_err(dev, "Cannot map IO\n");
1300 status = -ENXIO;
1301 goto out_error_ioremap;
1302 }
1303
1304 drv_data->dma_channel = platform_get_irq(pdev, 0);
1305 if (drv_data->dma_channel < 0) {
1306 dev_err(dev, "No DMA channel specified\n");
1307 status = -ENOENT;
1308 goto out_error_no_dma_ch;
1309 }
1310
1311
1312 status = bfin_spi_init_queue(drv_data);
1313 if (status != 0) {
1314 dev_err(dev, "problem initializing queue\n");
1315 goto out_error_queue_alloc;
1316 }
1317
1318 status = bfin_spi_start_queue(drv_data);
1319 if (status != 0) {
1320 dev_err(dev, "problem starting queue\n");
1321 goto out_error_queue_alloc;
1322 }
1323
1324 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1325 if (status != 0) {
1326 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1327 goto out_error_queue_alloc;
1328 }
1329
1330
1331 platform_set_drvdata(pdev, drv_data);
1332 status = spi_register_master(master);
1333 if (status != 0) {
1334 dev_err(dev, "problem registering spi master\n");
1335 goto out_error_queue_alloc;
1336 }
1337
1338 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1339 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1340 drv_data->dma_channel);
1341 return status;
1342
1343out_error_queue_alloc:
1344 bfin_spi_destroy_queue(drv_data);
1345out_error_no_dma_ch:
1346 iounmap((void *) drv_data->regs_base);
1347out_error_ioremap:
1348out_error_get_res:
1349 spi_master_put(master);
1350
1351 return status;
1352}
1353
1354
1355static int __devexit bfin_spi_remove(struct platform_device *pdev)
1356{
1357 struct driver_data *drv_data = platform_get_drvdata(pdev);
1358 int status = 0;
1359
1360 if (!drv_data)
1361 return 0;
1362
1363
1364 status = bfin_spi_destroy_queue(drv_data);
1365 if (status != 0)
1366 return status;
1367
1368
1369 bfin_spi_disable(drv_data);
1370
1371
1372 if (drv_data->master_info->enable_dma) {
1373 if (dma_channel_active(drv_data->dma_channel))
1374 free_dma(drv_data->dma_channel);
1375 }
1376
1377
1378 spi_unregister_master(drv_data->master);
1379
1380 peripheral_free_list(drv_data->pin_req);
1381
1382
1383 platform_set_drvdata(pdev, NULL);
1384
1385 return 0;
1386}
1387
1388#ifdef CONFIG_PM
1389static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1390{
1391 struct driver_data *drv_data = platform_get_drvdata(pdev);
1392 int status = 0;
1393
1394 status = bfin_spi_stop_queue(drv_data);
1395 if (status != 0)
1396 return status;
1397
1398
1399 bfin_spi_disable(drv_data);
1400
1401 return 0;
1402}
1403
1404static int bfin_spi_resume(struct platform_device *pdev)
1405{
1406 struct driver_data *drv_data = platform_get_drvdata(pdev);
1407 int status = 0;
1408
1409
1410 bfin_spi_enable(drv_data);
1411
1412
1413 status = bfin_spi_start_queue(drv_data);
1414 if (status != 0) {
1415 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1416 return status;
1417 }
1418
1419 return 0;
1420}
1421#else
1422#define bfin_spi_suspend NULL
1423#define bfin_spi_resume NULL
1424#endif
1425
1426MODULE_ALIAS("platform:bfin-spi");
1427static struct platform_driver bfin_spi_driver = {
1428 .driver = {
1429 .name = DRV_NAME,
1430 .owner = THIS_MODULE,
1431 },
1432 .suspend = bfin_spi_suspend,
1433 .resume = bfin_spi_resume,
1434 .remove = __devexit_p(bfin_spi_remove),
1435};
1436
1437static int __init bfin_spi_init(void)
1438{
1439 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1440}
1441module_init(bfin_spi_init);
1442
1443static void __exit bfin_spi_exit(void)
1444{
1445 platform_driver_unregister(&bfin_spi_driver);
1446}
1447module_exit(bfin_spi_exit);
1448