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21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
33#include <linux/spi/spi.h>
34#include <linux/spi/spi_bitbang.h>
35#include <linux/types.h>
36
37#include <mach/spi.h>
38
39#define DRIVER_NAME "spi_imx"
40
41#define MXC_CSPIRXDATA 0x00
42#define MXC_CSPITXDATA 0x04
43#define MXC_CSPICTRL 0x08
44#define MXC_CSPIINT 0x0c
45#define MXC_RESET 0x1c
46
47
48#define MXC_INT_RR (1 << 0)
49#define MXC_INT_TE (1 << 1)
50
51struct spi_imx_config {
52 unsigned int speed_hz;
53 unsigned int bpw;
54 unsigned int mode;
55 int cs;
56};
57
58struct spi_imx_data {
59 struct spi_bitbang bitbang;
60
61 struct completion xfer_done;
62 void *base;
63 int irq;
64 struct clk *clk;
65 unsigned long spi_clk;
66 int *chipselect;
67
68 unsigned int count;
69 void (*tx)(struct spi_imx_data *);
70 void (*rx)(struct spi_imx_data *);
71 void *rx_buf;
72 const void *tx_buf;
73 unsigned int txfifo;
74
75
76 void (*intctrl)(struct spi_imx_data *, int);
77 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
78 void (*trigger)(struct spi_imx_data *);
79 int (*rx_available)(struct spi_imx_data *);
80};
81
82#define MXC_SPI_BUF_RX(type) \
83static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
84{ \
85 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
86 \
87 if (spi_imx->rx_buf) { \
88 *(type *)spi_imx->rx_buf = val; \
89 spi_imx->rx_buf += sizeof(type); \
90 } \
91}
92
93#define MXC_SPI_BUF_TX(type) \
94static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
95{ \
96 type val = 0; \
97 \
98 if (spi_imx->tx_buf) { \
99 val = *(type *)spi_imx->tx_buf; \
100 spi_imx->tx_buf += sizeof(type); \
101 } \
102 \
103 spi_imx->count -= sizeof(type); \
104 \
105 writel(val, spi_imx->base + MXC_CSPITXDATA); \
106}
107
108MXC_SPI_BUF_RX(u8)
109MXC_SPI_BUF_TX(u8)
110MXC_SPI_BUF_RX(u16)
111MXC_SPI_BUF_TX(u16)
112MXC_SPI_BUF_RX(u32)
113MXC_SPI_BUF_TX(u32)
114
115
116
117
118static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
119 256, 384, 512, 768, 1024};
120
121
122static unsigned int spi_imx_clkdiv_1(unsigned int fin,
123 unsigned int fspi)
124{
125 int i, max;
126
127 if (cpu_is_mx21())
128 max = 18;
129 else
130 max = 16;
131
132 for (i = 2; i < max; i++)
133 if (fspi * mxc_clkdivs[i] >= fin)
134 return i;
135
136 return max;
137}
138
139
140static unsigned int spi_imx_clkdiv_2(unsigned int fin,
141 unsigned int fspi)
142{
143 int i, div = 4;
144
145 for (i = 0; i < 7; i++) {
146 if (fspi * div >= fin)
147 return i;
148 div <<= 1;
149 }
150
151 return 7;
152}
153
154#define MX31_INTREG_TEEN (1 << 0)
155#define MX31_INTREG_RREN (1 << 3)
156
157#define MX31_CSPICTRL_ENABLE (1 << 0)
158#define MX31_CSPICTRL_MASTER (1 << 1)
159#define MX31_CSPICTRL_XCH (1 << 2)
160#define MX31_CSPICTRL_POL (1 << 4)
161#define MX31_CSPICTRL_PHA (1 << 5)
162#define MX31_CSPICTRL_SSCTL (1 << 6)
163#define MX31_CSPICTRL_SSPOL (1 << 7)
164#define MX31_CSPICTRL_BC_SHIFT 8
165#define MX35_CSPICTRL_BL_SHIFT 20
166#define MX31_CSPICTRL_CS_SHIFT 24
167#define MX35_CSPICTRL_CS_SHIFT 12
168#define MX31_CSPICTRL_DR_SHIFT 16
169
170#define MX31_CSPISTATUS 0x14
171#define MX31_STATUS_RR (1 << 3)
172
173
174
175
176
177static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
178{
179 unsigned int val = 0;
180
181 if (enable & MXC_INT_TE)
182 val |= MX31_INTREG_TEEN;
183 if (enable & MXC_INT_RR)
184 val |= MX31_INTREG_RREN;
185
186 writel(val, spi_imx->base + MXC_CSPIINT);
187}
188
189static void mx31_trigger(struct spi_imx_data *spi_imx)
190{
191 unsigned int reg;
192
193 reg = readl(spi_imx->base + MXC_CSPICTRL);
194 reg |= MX31_CSPICTRL_XCH;
195 writel(reg, spi_imx->base + MXC_CSPICTRL);
196}
197
198static int mx31_config(struct spi_imx_data *spi_imx,
199 struct spi_imx_config *config)
200{
201 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
202
203 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
204 MX31_CSPICTRL_DR_SHIFT;
205
206 if (cpu_is_mx31())
207 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
208 else if (cpu_is_mx35()) {
209 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
210 reg |= MX31_CSPICTRL_SSCTL;
211 }
212
213 if (config->mode & SPI_CPHA)
214 reg |= MX31_CSPICTRL_PHA;
215 if (config->mode & SPI_CPOL)
216 reg |= MX31_CSPICTRL_POL;
217 if (config->mode & SPI_CS_HIGH)
218 reg |= MX31_CSPICTRL_SSPOL;
219 if (config->cs < 0) {
220 if (cpu_is_mx31())
221 reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
222 else if (cpu_is_mx35())
223 reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
224 }
225
226 writel(reg, spi_imx->base + MXC_CSPICTRL);
227
228 return 0;
229}
230
231static int mx31_rx_available(struct spi_imx_data *spi_imx)
232{
233 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
234}
235
236#define MX27_INTREG_RR (1 << 4)
237#define MX27_INTREG_TEEN (1 << 9)
238#define MX27_INTREG_RREN (1 << 13)
239
240#define MX27_CSPICTRL_POL (1 << 5)
241#define MX27_CSPICTRL_PHA (1 << 6)
242#define MX27_CSPICTRL_SSPOL (1 << 8)
243#define MX27_CSPICTRL_XCH (1 << 9)
244#define MX27_CSPICTRL_ENABLE (1 << 10)
245#define MX27_CSPICTRL_MASTER (1 << 11)
246#define MX27_CSPICTRL_DR_SHIFT 14
247#define MX27_CSPICTRL_CS_SHIFT 19
248
249static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
250{
251 unsigned int val = 0;
252
253 if (enable & MXC_INT_TE)
254 val |= MX27_INTREG_TEEN;
255 if (enable & MXC_INT_RR)
256 val |= MX27_INTREG_RREN;
257
258 writel(val, spi_imx->base + MXC_CSPIINT);
259}
260
261static void mx27_trigger(struct spi_imx_data *spi_imx)
262{
263 unsigned int reg;
264
265 reg = readl(spi_imx->base + MXC_CSPICTRL);
266 reg |= MX27_CSPICTRL_XCH;
267 writel(reg, spi_imx->base + MXC_CSPICTRL);
268}
269
270static int mx27_config(struct spi_imx_data *spi_imx,
271 struct spi_imx_config *config)
272{
273 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
274
275 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
276 MX27_CSPICTRL_DR_SHIFT;
277 reg |= config->bpw - 1;
278
279 if (config->mode & SPI_CPHA)
280 reg |= MX27_CSPICTRL_PHA;
281 if (config->mode & SPI_CPOL)
282 reg |= MX27_CSPICTRL_POL;
283 if (config->mode & SPI_CS_HIGH)
284 reg |= MX27_CSPICTRL_SSPOL;
285 if (config->cs < 0)
286 reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
287
288 writel(reg, spi_imx->base + MXC_CSPICTRL);
289
290 return 0;
291}
292
293static int mx27_rx_available(struct spi_imx_data *spi_imx)
294{
295 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
296}
297
298#define MX1_INTREG_RR (1 << 3)
299#define MX1_INTREG_TEEN (1 << 8)
300#define MX1_INTREG_RREN (1 << 11)
301
302#define MX1_CSPICTRL_POL (1 << 4)
303#define MX1_CSPICTRL_PHA (1 << 5)
304#define MX1_CSPICTRL_XCH (1 << 8)
305#define MX1_CSPICTRL_ENABLE (1 << 9)
306#define MX1_CSPICTRL_MASTER (1 << 10)
307#define MX1_CSPICTRL_DR_SHIFT 13
308
309static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
310{
311 unsigned int val = 0;
312
313 if (enable & MXC_INT_TE)
314 val |= MX1_INTREG_TEEN;
315 if (enable & MXC_INT_RR)
316 val |= MX1_INTREG_RREN;
317
318 writel(val, spi_imx->base + MXC_CSPIINT);
319}
320
321static void mx1_trigger(struct spi_imx_data *spi_imx)
322{
323 unsigned int reg;
324
325 reg = readl(spi_imx->base + MXC_CSPICTRL);
326 reg |= MX1_CSPICTRL_XCH;
327 writel(reg, spi_imx->base + MXC_CSPICTRL);
328}
329
330static int mx1_config(struct spi_imx_data *spi_imx,
331 struct spi_imx_config *config)
332{
333 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
334
335 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
336 MX1_CSPICTRL_DR_SHIFT;
337 reg |= config->bpw - 1;
338
339 if (config->mode & SPI_CPHA)
340 reg |= MX1_CSPICTRL_PHA;
341 if (config->mode & SPI_CPOL)
342 reg |= MX1_CSPICTRL_POL;
343
344 writel(reg, spi_imx->base + MXC_CSPICTRL);
345
346 return 0;
347}
348
349static int mx1_rx_available(struct spi_imx_data *spi_imx)
350{
351 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
352}
353
354static void spi_imx_chipselect(struct spi_device *spi, int is_active)
355{
356 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
357 int gpio = spi_imx->chipselect[spi->chip_select];
358 int active = is_active != BITBANG_CS_INACTIVE;
359 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
360
361 if (gpio < 0)
362 return;
363
364 gpio_set_value(gpio, dev_is_lowactive ^ active);
365}
366
367static void spi_imx_push(struct spi_imx_data *spi_imx)
368{
369 while (spi_imx->txfifo < 8) {
370 if (!spi_imx->count)
371 break;
372 spi_imx->tx(spi_imx);
373 spi_imx->txfifo++;
374 }
375
376 spi_imx->trigger(spi_imx);
377}
378
379static irqreturn_t spi_imx_isr(int irq, void *dev_id)
380{
381 struct spi_imx_data *spi_imx = dev_id;
382
383 while (spi_imx->rx_available(spi_imx)) {
384 spi_imx->rx(spi_imx);
385 spi_imx->txfifo--;
386 }
387
388 if (spi_imx->count) {
389 spi_imx_push(spi_imx);
390 return IRQ_HANDLED;
391 }
392
393 if (spi_imx->txfifo) {
394
395
396
397 spi_imx->intctrl(spi_imx, MXC_INT_RR);
398 return IRQ_HANDLED;
399 }
400
401 spi_imx->intctrl(spi_imx, 0);
402 complete(&spi_imx->xfer_done);
403
404 return IRQ_HANDLED;
405}
406
407static int spi_imx_setupxfer(struct spi_device *spi,
408 struct spi_transfer *t)
409{
410 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
411 struct spi_imx_config config;
412
413 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
414 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
415 config.mode = spi->mode;
416 config.cs = spi_imx->chipselect[spi->chip_select];
417
418 if (!config.speed_hz)
419 config.speed_hz = spi->max_speed_hz;
420 if (!config.bpw)
421 config.bpw = spi->bits_per_word;
422 if (!config.speed_hz)
423 config.speed_hz = spi->max_speed_hz;
424
425
426 if (config.bpw <= 8) {
427 spi_imx->rx = spi_imx_buf_rx_u8;
428 spi_imx->tx = spi_imx_buf_tx_u8;
429 } else if (config.bpw <= 16) {
430 spi_imx->rx = spi_imx_buf_rx_u16;
431 spi_imx->tx = spi_imx_buf_tx_u16;
432 } else if (config.bpw <= 32) {
433 spi_imx->rx = spi_imx_buf_rx_u32;
434 spi_imx->tx = spi_imx_buf_tx_u32;
435 } else
436 BUG();
437
438 spi_imx->config(spi_imx, &config);
439
440 return 0;
441}
442
443static int spi_imx_transfer(struct spi_device *spi,
444 struct spi_transfer *transfer)
445{
446 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
447
448 spi_imx->tx_buf = transfer->tx_buf;
449 spi_imx->rx_buf = transfer->rx_buf;
450 spi_imx->count = transfer->len;
451 spi_imx->txfifo = 0;
452
453 init_completion(&spi_imx->xfer_done);
454
455 spi_imx_push(spi_imx);
456
457 spi_imx->intctrl(spi_imx, MXC_INT_TE);
458
459 wait_for_completion(&spi_imx->xfer_done);
460
461 return transfer->len;
462}
463
464static int spi_imx_setup(struct spi_device *spi)
465{
466 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
467 int gpio = spi_imx->chipselect[spi->chip_select];
468
469 pr_debug("%s: mode %d, %u bpw, %d hz\n", __func__,
470 spi->mode, spi->bits_per_word, spi->max_speed_hz);
471
472 if (gpio >= 0)
473 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
474
475 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
476
477 return 0;
478}
479
480static void spi_imx_cleanup(struct spi_device *spi)
481{
482}
483
484static int __init spi_imx_probe(struct platform_device *pdev)
485{
486 struct spi_imx_master *mxc_platform_info;
487 struct spi_master *master;
488 struct spi_imx_data *spi_imx;
489 struct resource *res;
490 int i, ret;
491
492 mxc_platform_info = (struct spi_imx_master *)pdev->dev.platform_data;
493 if (!mxc_platform_info) {
494 dev_err(&pdev->dev, "can't get the platform data\n");
495 return -EINVAL;
496 }
497
498 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
499 if (!master)
500 return -ENOMEM;
501
502 platform_set_drvdata(pdev, master);
503
504 master->bus_num = pdev->id;
505 master->num_chipselect = mxc_platform_info->num_chipselect;
506
507 spi_imx = spi_master_get_devdata(master);
508 spi_imx->bitbang.master = spi_master_get(master);
509 spi_imx->chipselect = mxc_platform_info->chipselect;
510
511 for (i = 0; i < master->num_chipselect; i++) {
512 if (spi_imx->chipselect[i] < 0)
513 continue;
514 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
515 if (ret) {
516 i--;
517 while (i > 0)
518 if (spi_imx->chipselect[i] >= 0)
519 gpio_free(spi_imx->chipselect[i--]);
520 dev_err(&pdev->dev, "can't get cs gpios");
521 goto out_master_put;
522 }
523 }
524
525 spi_imx->bitbang.chipselect = spi_imx_chipselect;
526 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
527 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
528 spi_imx->bitbang.master->setup = spi_imx_setup;
529 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
530 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
531
532 init_completion(&spi_imx->xfer_done);
533
534 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
535 if (!res) {
536 dev_err(&pdev->dev, "can't get platform resource\n");
537 ret = -ENOMEM;
538 goto out_gpio_free;
539 }
540
541 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
542 dev_err(&pdev->dev, "request_mem_region failed\n");
543 ret = -EBUSY;
544 goto out_gpio_free;
545 }
546
547 spi_imx->base = ioremap(res->start, resource_size(res));
548 if (!spi_imx->base) {
549 ret = -EINVAL;
550 goto out_release_mem;
551 }
552
553 spi_imx->irq = platform_get_irq(pdev, 0);
554 if (!spi_imx->irq) {
555 ret = -EINVAL;
556 goto out_iounmap;
557 }
558
559 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
560 if (ret) {
561 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
562 goto out_iounmap;
563 }
564
565 if (cpu_is_mx31() || cpu_is_mx35()) {
566 spi_imx->intctrl = mx31_intctrl;
567 spi_imx->config = mx31_config;
568 spi_imx->trigger = mx31_trigger;
569 spi_imx->rx_available = mx31_rx_available;
570 } else if (cpu_is_mx27() || cpu_is_mx21()) {
571 spi_imx->intctrl = mx27_intctrl;
572 spi_imx->config = mx27_config;
573 spi_imx->trigger = mx27_trigger;
574 spi_imx->rx_available = mx27_rx_available;
575 } else if (cpu_is_mx1()) {
576 spi_imx->intctrl = mx1_intctrl;
577 spi_imx->config = mx1_config;
578 spi_imx->trigger = mx1_trigger;
579 spi_imx->rx_available = mx1_rx_available;
580 } else
581 BUG();
582
583 spi_imx->clk = clk_get(&pdev->dev, NULL);
584 if (IS_ERR(spi_imx->clk)) {
585 dev_err(&pdev->dev, "unable to get clock\n");
586 ret = PTR_ERR(spi_imx->clk);
587 goto out_free_irq;
588 }
589
590 clk_enable(spi_imx->clk);
591 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
592
593 if (!cpu_is_mx31() || !cpu_is_mx35())
594 writel(1, spi_imx->base + MXC_RESET);
595
596 spi_imx->intctrl(spi_imx, 0);
597
598 ret = spi_bitbang_start(&spi_imx->bitbang);
599 if (ret) {
600 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
601 goto out_clk_put;
602 }
603
604 dev_info(&pdev->dev, "probed\n");
605
606 return ret;
607
608out_clk_put:
609 clk_disable(spi_imx->clk);
610 clk_put(spi_imx->clk);
611out_free_irq:
612 free_irq(spi_imx->irq, spi_imx);
613out_iounmap:
614 iounmap(spi_imx->base);
615out_release_mem:
616 release_mem_region(res->start, resource_size(res));
617out_gpio_free:
618 for (i = 0; i < master->num_chipselect; i++)
619 if (spi_imx->chipselect[i] >= 0)
620 gpio_free(spi_imx->chipselect[i]);
621out_master_put:
622 spi_master_put(master);
623 kfree(master);
624 platform_set_drvdata(pdev, NULL);
625 return ret;
626}
627
628static int __exit spi_imx_remove(struct platform_device *pdev)
629{
630 struct spi_master *master = platform_get_drvdata(pdev);
631 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
633 int i;
634
635 spi_bitbang_stop(&spi_imx->bitbang);
636
637 writel(0, spi_imx->base + MXC_CSPICTRL);
638 clk_disable(spi_imx->clk);
639 clk_put(spi_imx->clk);
640 free_irq(spi_imx->irq, spi_imx);
641 iounmap(spi_imx->base);
642
643 for (i = 0; i < master->num_chipselect; i++)
644 if (spi_imx->chipselect[i] >= 0)
645 gpio_free(spi_imx->chipselect[i]);
646
647 spi_master_put(master);
648
649 release_mem_region(res->start, resource_size(res));
650
651 platform_set_drvdata(pdev, NULL);
652
653 return 0;
654}
655
656static struct platform_driver spi_imx_driver = {
657 .driver = {
658 .name = DRIVER_NAME,
659 .owner = THIS_MODULE,
660 },
661 .probe = spi_imx_probe,
662 .remove = __exit_p(spi_imx_remove),
663};
664
665static int __init spi_imx_init(void)
666{
667 return platform_driver_register(&spi_imx_driver);
668}
669
670static void __exit spi_imx_exit(void)
671{
672 platform_driver_unregister(&spi_imx_driver);
673}
674
675module_init(spi_imx_init);
676module_exit(spi_imx_exit);
677
678MODULE_DESCRIPTION("SPI Master Controller driver");
679MODULE_AUTHOR("Sascha Hauer, Pengutronix");
680MODULE_LICENSE("GPL");
681
