LXR linux/drivers/staging/comedi/comedi.h

   1/*
   2    include/comedi.h (installed as /usr/include/comedi.h)
   3    header file for comedi
   4
   5    COMEDI - Linux Control and Measurement Device Interface
   6    Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU Lesser General Public License as published by
  10    the Free Software Foundation; either version 2 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program; if not, write to the Free Software
  20    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21
  22*/
  23
  24#ifndef _COMEDI_H
  25#define _COMEDI_H
  26
  27#ifdef __cplusplus
  28extern "C" {
  29#endif
  30
  31#define COMEDI_MAJORVERSION     0
  32#define COMEDI_MINORVERSION     7
  33#define COMEDI_MICROVERSION     76
  34#define VERSION "0.7.76"
  35
  36/* comedi's major device number */
  37#define COMEDI_MAJOR 98
  38
  39/*
  40   maximum number of minor devices.  This can be increased, although
  41   kernel structures are currently statically allocated, thus you
  42   don't want this to be much more than you actually use.
  43 */
  44#define COMEDI_NDEVICES 16
  45
  46/* number of config options in the config structure */
  47#define COMEDI_NDEVCONFOPTS 32
  48/*length of nth chunk of firmware data*/
  49#define COMEDI_DEVCONF_AUX_DATA3_LENGTH         25
  50#define COMEDI_DEVCONF_AUX_DATA2_LENGTH         26
  51#define COMEDI_DEVCONF_AUX_DATA1_LENGTH         27
  52#define COMEDI_DEVCONF_AUX_DATA0_LENGTH         28
  53#define COMEDI_DEVCONF_AUX_DATA_HI              29      /* most significant 32 bits of pointer address (if needed) */
  54#define COMEDI_DEVCONF_AUX_DATA_LO              30      /* least significant 32 bits of pointer address */
  55#define COMEDI_DEVCONF_AUX_DATA_LENGTH          31      /* total data length */
  56
  57/* max length of device and driver names */
  58#define COMEDI_NAMELEN 20
  59
  60/* packs and unpacks a channel/range number */
  61
  62#define CR_PACK(chan, rng, aref)                ((((aref)&0x3)<<24) | (((rng)&0xff)<<16) | (chan))
  63#define CR_PACK_FLAGS(chan, range, aref, flags) (CR_PACK(chan, range, aref) | ((flags) & CR_FLAGS_MASK))
  64
  65#define CR_CHAN(a)      ((a)&0xffff)
  66#define CR_RANGE(a)     (((a)>>16)&0xff)
  67#define CR_AREF(a)      (((a)>>24)&0x03)
  68
  69#define CR_FLAGS_MASK   0xfc000000
  70#define CR_ALT_FILTER   (1<<26)
  71#define CR_DITHER       CR_ALT_FILTER
  72#define CR_DEGLITCH     CR_ALT_FILTER
  73#define CR_ALT_SOURCE   (1<<27)
  74#define CR_EDGE         (1<<30)
  75#define CR_INVERT       (1<<31)
  76
  77#define AREF_GROUND     0x00    /* analog ref = analog ground */
  78#define AREF_COMMON     0x01    /* analog ref = analog common */
  79#define AREF_DIFF       0x02    /* analog ref = differential */
  80#define AREF_OTHER      0x03    /* analog ref = other (undefined) */
  81
  82/* counters -- these are arbitrary values */
  83#define GPCT_RESET              0x0001
  84#define GPCT_SET_SOURCE         0x0002
  85#define GPCT_SET_GATE           0x0004
  86#define GPCT_SET_DIRECTION      0x0008
  87#define GPCT_SET_OPERATION      0x0010
  88#define GPCT_ARM                0x0020
  89#define GPCT_DISARM             0x0040
  90#define GPCT_GET_INT_CLK_FRQ    0x0080
  91
  92#define GPCT_INT_CLOCK          0x0001
  93#define GPCT_EXT_PIN            0x0002
  94#define GPCT_NO_GATE            0x0004
  95#define GPCT_UP                 0x0008
  96#define GPCT_DOWN               0x0010
  97#define GPCT_HWUD               0x0020
  98#define GPCT_SIMPLE_EVENT       0x0040
  99#define GPCT_SINGLE_PERIOD      0x0080
 100#define GPCT_SINGLE_PW          0x0100
 101#define GPCT_CONT_PULSE_OUT     0x0200
 102#define GPCT_SINGLE_PULSE_OUT   0x0400
 103
 104/* instructions */
 105
 106#define INSN_MASK_WRITE         0x8000000
 107#define INSN_MASK_READ          0x4000000
 108#define INSN_MASK_SPECIAL       0x2000000
 109
 110#define INSN_READ               (0 | INSN_MASK_READ)
 111#define INSN_WRITE              (1 | INSN_MASK_WRITE)
 112#define INSN_BITS               (2 | INSN_MASK_READ|INSN_MASK_WRITE)
 113#define INSN_CONFIG             (3 | INSN_MASK_READ|INSN_MASK_WRITE)
 114#define INSN_GTOD               (4 | INSN_MASK_READ|INSN_MASK_SPECIAL)
 115#define INSN_WAIT               (5 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 116#define INSN_INTTRIG            (6 | INSN_MASK_WRITE|INSN_MASK_SPECIAL)
 117
 118/* trigger flags */
 119/* These flags are used in comedi_trig structures */
 120
 121#define TRIG_BOGUS      0x0001  /* do the motions */
 122#define TRIG_DITHER     0x0002  /* enable dithering */
 123#define TRIG_DEGLITCH   0x0004  /* enable deglitching */
 124        /*#define TRIG_RT       0x0008 *//* perform op in real time */
 125#define TRIG_CONFIG     0x0010  /* perform configuration, not triggering */
 126#define TRIG_WAKE_EOS   0x0020  /* wake up on end-of-scan events */
 127        /*#define TRIG_WRITE    0x0040*//* write to bidirectional devices */
 128
 129/* command flags */
 130/* These flags are used in comedi_cmd structures */
 131
 132#define CMDF_PRIORITY           0x00000008      /* try to use a real-time interrupt while performing command */
 133
 134#define TRIG_RT         CMDF_PRIORITY   /* compatibility definition */
 135
 136#define CMDF_WRITE              0x00000040
 137#define TRIG_WRITE      CMDF_WRITE      /* compatibility definition */
 138
 139#define CMDF_RAWDATA            0x00000080
 140
 141#define COMEDI_EV_START         0x00040000
 142#define COMEDI_EV_SCAN_BEGIN    0x00080000
 143#define COMEDI_EV_CONVERT       0x00100000
 144#define COMEDI_EV_SCAN_END      0x00200000
 145#define COMEDI_EV_STOP          0x00400000
 146
 147#define TRIG_ROUND_MASK         0x00030000
 148#define TRIG_ROUND_NEAREST      0x00000000
 149#define TRIG_ROUND_DOWN         0x00010000
 150#define TRIG_ROUND_UP           0x00020000
 151#define TRIG_ROUND_UP_NEXT      0x00030000
 152
 153/* trigger sources */
 154
 155#define TRIG_ANY        0xffffffff
 156#define TRIG_INVALID    0x00000000
 157
 158#define TRIG_NONE       0x00000001      /* never trigger */
 159#define TRIG_NOW        0x00000002      /* trigger now + N ns */
 160#define TRIG_FOLLOW     0x00000004      /* trigger on next lower level trig */
 161#define TRIG_TIME       0x00000008      /* trigger at time N ns */
 162#define TRIG_TIMER      0x00000010      /* trigger at rate N ns */
 163#define TRIG_COUNT      0x00000020      /* trigger when count reaches N */
 164#define TRIG_EXT        0x00000040      /* trigger on external signal N */
 165#define TRIG_INT        0x00000080      /* trigger on comedi-internal signal N */
 166#define TRIG_OTHER      0x00000100      /* driver defined */
 167
 168/* subdevice flags */
 169
 170#define SDF_BUSY        0x0001  /* device is busy */
 171#define SDF_BUSY_OWNER  0x0002  /* device is busy with your job */
 172#define SDF_LOCKED      0x0004  /* subdevice is locked */
 173#define SDF_LOCK_OWNER  0x0008  /* you own lock */
 174#define SDF_MAXDATA     0x0010  /* maxdata depends on channel */
 175#define SDF_FLAGS       0x0020  /* flags depend on channel */
 176#define SDF_RANGETYPE   0x0040  /* range type depends on channel */
 177#define SDF_MODE0       0x0080  /* can do mode 0 */
 178#define SDF_MODE1       0x0100  /* can do mode 1 */
 179#define SDF_MODE2       0x0200  /* can do mode 2 */
 180#define SDF_MODE3       0x0400  /* can do mode 3 */
 181#define SDF_MODE4       0x0800  /* can do mode 4 */
 182#define SDF_CMD         0x1000  /* can do commands (deprecated) */
 183#define SDF_SOFT_CALIBRATED     0x2000  /* subdevice uses software calibration */
 184#define SDF_CMD_WRITE           0x4000  /* can do output commands */
 185#define SDF_CMD_READ            0x8000  /* can do input commands */
 186
 187#define SDF_READABLE    0x00010000      /* subdevice can be read (e.g. analog input) */
 188#define SDF_WRITABLE    0x00020000      /* subdevice can be written (e.g. analog output) */
 189#define SDF_WRITEABLE   SDF_WRITABLE    /* spelling error in API */
 190#define SDF_INTERNAL    0x00040000      /* subdevice does not have externally visible lines */
 191#define SDF_GROUND      0x00100000      /* can do aref=ground */
 192#define SDF_COMMON      0x00200000      /* can do aref=common */
 193#define SDF_DIFF        0x00400000      /* can do aref=diff */
 194#define SDF_OTHER       0x00800000      /* can do aref=other */
 195#define SDF_DITHER      0x01000000      /* can do dithering */
 196#define SDF_DEGLITCH    0x02000000      /* can do deglitching */
 197#define SDF_MMAP        0x04000000      /* can do mmap() */
 198#define SDF_RUNNING     0x08000000      /* subdevice is acquiring data */
 199#define SDF_LSAMPL      0x10000000      /* subdevice uses 32-bit samples */
 200#define SDF_PACKED      0x20000000      /* subdevice can do packed DIO */
 201/* re recyle these flags for PWM */
 202#define SDF_PWM_COUNTER SDF_MODE0       /* PWM can automatically switch off */
 203#define SDF_PWM_HBRIDGE SDF_MODE1       /* PWM is signed (H-bridge) */
 204
 205/* subdevice types */
 206
 207        enum comedi_subdevice_type {
 208                COMEDI_SUBD_UNUSED,     /* unused by driver */
 209                COMEDI_SUBD_AI, /* analog input */
 210                COMEDI_SUBD_AO, /* analog output */
 211                COMEDI_SUBD_DI, /* digital input */
 212                COMEDI_SUBD_DO, /* digital output */
 213                COMEDI_SUBD_DIO,        /* digital input/output */
 214                COMEDI_SUBD_COUNTER,    /* counter */
 215                COMEDI_SUBD_TIMER,      /* timer */
 216                COMEDI_SUBD_MEMORY,     /* memory, EEPROM, DPRAM */
 217                COMEDI_SUBD_CALIB,      /* calibration DACs */
 218                COMEDI_SUBD_PROC,       /* processor, DSP */
 219                COMEDI_SUBD_SERIAL,     /* serial IO */
 220                COMEDI_SUBD_PWM /* PWM */
 221        };
 222
 223/* configuration instructions */
 224
 225        enum configuration_ids {
 226                INSN_CONFIG_DIO_INPUT = 0,
 227                INSN_CONFIG_DIO_OUTPUT = 1,
 228                INSN_CONFIG_DIO_OPENDRAIN = 2,
 229                INSN_CONFIG_ANALOG_TRIG = 16,
 230/*      INSN_CONFIG_WAVEFORM = 17, */
 231/*      INSN_CONFIG_TRIG = 18, */
 232/*      INSN_CONFIG_COUNTER = 19, */
 233                INSN_CONFIG_ALT_SOURCE = 20,
 234                INSN_CONFIG_DIGITAL_TRIG = 21,
 235                INSN_CONFIG_BLOCK_SIZE = 22,
 236                INSN_CONFIG_TIMER_1 = 23,
 237                INSN_CONFIG_FILTER = 24,
 238                INSN_CONFIG_CHANGE_NOTIFY = 25,
 239
 240                 /*ALPHA*/ INSN_CONFIG_SERIAL_CLOCK = 26,
 241                INSN_CONFIG_BIDIRECTIONAL_DATA = 27,
 242                INSN_CONFIG_DIO_QUERY = 28,
 243                INSN_CONFIG_PWM_OUTPUT = 29,
 244                INSN_CONFIG_GET_PWM_OUTPUT = 30,
 245                INSN_CONFIG_ARM = 31,
 246                INSN_CONFIG_DISARM = 32,
 247                INSN_CONFIG_GET_COUNTER_STATUS = 33,
 248                INSN_CONFIG_RESET = 34,
 249                INSN_CONFIG_GPCT_SINGLE_PULSE_GENERATOR = 1001, /* Use CTR as single pulsegenerator */
 250                INSN_CONFIG_GPCT_PULSE_TRAIN_GENERATOR = 1002,  /* Use CTR as pulsetraingenerator */
 251                INSN_CONFIG_GPCT_QUADRATURE_ENCODER = 1003,     /* Use the counter as encoder */
 252                INSN_CONFIG_SET_GATE_SRC = 2001,        /* Set gate source */
 253                INSN_CONFIG_GET_GATE_SRC = 2002,        /* Get gate source */
 254                INSN_CONFIG_SET_CLOCK_SRC = 2003,       /* Set master clock source */
 255                INSN_CONFIG_GET_CLOCK_SRC = 2004,       /* Get master clock source */
 256                INSN_CONFIG_SET_OTHER_SRC = 2005,       /* Set other source */
 257                /*      INSN_CONFIG_GET_OTHER_SRC = 2006,*//* Get other source */
 258                INSN_CONFIG_GET_HARDWARE_BUFFER_SIZE = 2006,    /* Get size in bytes of
 259                                                                   subdevice's on-board
 260                                                                   fifos used during
 261                                                                   streaming
 262                                                                   input/output */
 263                INSN_CONFIG_SET_COUNTER_MODE = 4097,
 264                INSN_CONFIG_8254_SET_MODE = INSN_CONFIG_SET_COUNTER_MODE,       /* deprecated */
 265                INSN_CONFIG_8254_READ_STATUS = 4098,
 266                INSN_CONFIG_SET_ROUTING = 4099,
 267                INSN_CONFIG_GET_ROUTING = 4109,
 268/* PWM */
 269                INSN_CONFIG_PWM_SET_PERIOD = 5000,      /* sets frequency */
 270                INSN_CONFIG_PWM_GET_PERIOD = 5001,      /* gets frequency */
 271                INSN_CONFIG_GET_PWM_STATUS = 5002,      /* is it running? */
 272                INSN_CONFIG_PWM_SET_H_BRIDGE = 5003,    /* sets H bridge: duty cycle and sign bit for a relay  at the same time */
 273                INSN_CONFIG_PWM_GET_H_BRIDGE = 5004     /* gets H bridge data: duty cycle and the sign bit */
 274        };
 275
 276        enum comedi_io_direction {
 277                COMEDI_INPUT = 0,
 278                COMEDI_OUTPUT = 1,
 279                COMEDI_OPENDRAIN = 2
 280        };
 281
 282        enum comedi_support_level {
 283                COMEDI_UNKNOWN_SUPPORT = 0,
 284                COMEDI_SUPPORTED,
 285                COMEDI_UNSUPPORTED
 286        };
 287
 288/* ioctls */
 289
 290#define CIO 'd'
 291#define COMEDI_DEVCONFIG _IOW(CIO, 0, struct comedi_devconfig)
 292#define COMEDI_DEVINFO _IOR(CIO, 1, struct comedi_devinfo)
 293#define COMEDI_SUBDINFO _IOR(CIO, 2, struct comedi_subdinfo)
 294#define COMEDI_CHANINFO _IOR(CIO, 3, struct comedi_chaninfo)
 295#define COMEDI_TRIG _IOWR(CIO, 4, comedi_trig)
 296#define COMEDI_LOCK _IO(CIO, 5)
 297#define COMEDI_UNLOCK _IO(CIO, 6)
 298#define COMEDI_CANCEL _IO(CIO, 7)
 299#define COMEDI_RANGEINFO _IOR(CIO, 8, struct comedi_rangeinfo)
 300#define COMEDI_CMD _IOR(CIO, 9, struct comedi_cmd)
 301#define COMEDI_CMDTEST _IOR(CIO, 10, struct comedi_cmd)
 302#define COMEDI_INSNLIST _IOR(CIO, 11, struct comedi_insnlist)
 303#define COMEDI_INSN _IOR(CIO, 12, struct comedi_insn)
 304#define COMEDI_BUFCONFIG _IOR(CIO, 13, struct comedi_bufconfig)
 305#define COMEDI_BUFINFO _IOWR(CIO, 14, struct comedi_bufinfo)
 306#define COMEDI_POLL _IO(CIO, 15)
 307
 308/* structures */
 309
 310        struct comedi_trig {
 311                unsigned int subdev;    /* subdevice */
 312                unsigned int mode;      /* mode */
 313                unsigned int flags;
 314                unsigned int n_chan;    /* number of channels */
 315                unsigned int *chanlist; /* channel/range list */
 316                short *data;    /* data list, size depends on subd flags */
 317                unsigned int n; /* number of scans */
 318                unsigned int trigsrc;
 319                unsigned int trigvar;
 320                unsigned int trigvar1;
 321                unsigned int data_len;
 322                unsigned int unused[3];
 323        };
 324
 325        struct comedi_insn {
 326                unsigned int insn;
 327                unsigned int n;
 328                unsigned int *data;
 329                unsigned int subdev;
 330                unsigned int chanspec;
 331                unsigned int unused[3];
 332        };
 333
 334        struct comedi_insnlist {
 335                unsigned int n_insns;
 336                struct comedi_insn *insns;
 337        };
 338
 339        struct comedi_cmd {
 340                unsigned int subdev;
 341                unsigned int flags;
 342
 343                unsigned int start_src;
 344                unsigned int start_arg;
 345
 346                unsigned int scan_begin_src;
 347                unsigned int scan_begin_arg;
 348
 349                unsigned int convert_src;
 350                unsigned int convert_arg;
 351
 352                unsigned int scan_end_src;
 353                unsigned int scan_end_arg;
 354
 355                unsigned int stop_src;
 356                unsigned int stop_arg;
 357
 358                unsigned int *chanlist; /* channel/range list */
 359                unsigned int chanlist_len;
 360
 361                short *data;    /* data list, size depends on subd flags */
 362                unsigned int data_len;
 363        };
 364
 365        struct comedi_chaninfo {
 366                unsigned int subdev;
 367                unsigned int *maxdata_list;
 368                unsigned int *flaglist;
 369                unsigned int *rangelist;
 370                unsigned int unused[4];
 371        };
 372
 373        struct comedi_rangeinfo {
 374                unsigned int range_type;
 375                void *range_ptr;
 376        };
 377
 378        struct comedi_krange {
 379                int min;        /* fixed point, multiply by 1e-6 */
 380                int max;        /* fixed point, multiply by 1e-6 */
 381                unsigned int flags;
 382        };
 383
 384        struct comedi_subdinfo {
 385                unsigned int type;
 386                unsigned int n_chan;
 387                unsigned int subd_flags;
 388                unsigned int timer_type;
 389                unsigned int len_chanlist;
 390                unsigned int maxdata;
 391                unsigned int flags;     /* channel flags */
 392                unsigned int range_type;        /* lookup in kernel */
 393                unsigned int settling_time_0;
 394                unsigned insn_bits_support;     /* see support_level enum for values */
 395                unsigned int unused[8];
 396        };
 397
 398        struct comedi_devinfo {
 399                unsigned int version_code;
 400                unsigned int n_subdevs;
 401                char driver_name[COMEDI_NAMELEN];
 402                char board_name[COMEDI_NAMELEN];
 403                int read_subdevice;
 404                int write_subdevice;
 405                int unused[30];
 406        };
 407
 408        struct comedi_devconfig {
 409                char board_name[COMEDI_NAMELEN];
 410                int options[COMEDI_NDEVCONFOPTS];
 411        };
 412
 413        struct comedi_bufconfig {
 414                unsigned int subdevice;
 415                unsigned int flags;
 416
 417                unsigned int maximum_size;
 418                unsigned int size;
 419
 420                unsigned int unused[4];
 421        };
 422
 423        struct comedi_bufinfo {
 424                unsigned int subdevice;
 425                unsigned int bytes_read;
 426
 427                unsigned int buf_write_ptr;
 428                unsigned int buf_read_ptr;
 429                unsigned int buf_write_count;
 430                unsigned int buf_read_count;
 431
 432                unsigned int bytes_written;
 433
 434                unsigned int unused[4];
 435        };
 436
 437/* range stuff */
 438
 439#define __RANGE(a, b)   ((((a)&0xffff)<<16)|((b)&0xffff))
 440
 441#define RANGE_OFFSET(a)         (((a)>>16)&0xffff)
 442#define RANGE_LENGTH(b)         ((b)&0xffff)
 443
 444#define RF_UNIT(flags)          ((flags)&0xff)
 445#define RF_EXTERNAL             (1<<8)
 446
 447#define UNIT_volt               0
 448#define UNIT_mA                 1
 449#define UNIT_none               2
 450
 451#define COMEDI_MIN_SPEED        ((unsigned int)0xffffffff)
 452
 453/* callback stuff */
 454/* only relevant to kernel modules. */
 455
 456#define COMEDI_CB_EOS           1       /* end of scan */
 457#define COMEDI_CB_EOA           2       /* end of acquisition */
 458#define COMEDI_CB_BLOCK         4       /* DEPRECATED: convenient block size */
 459#define COMEDI_CB_EOBUF         8       /* DEPRECATED: end of buffer */
 460#define COMEDI_CB_ERROR         16      /* card error during acquisition */
 461#define COMEDI_CB_OVERFLOW      32      /* buffer overflow/underflow */
 462
 463/**********************************************************/
 464/* everything after this line is ALPHA */
 465/**********************************************************/
 466
 467/*
 468  8254 specific configuration.
 469
 470  It supports two config commands:
 471
 472  0 ID: INSN_CONFIG_SET_COUNTER_MODE
 473  1 8254 Mode
 474    I8254_MODE0, I8254_MODE1, ..., I8254_MODE5
 475    OR'ed with:
 476    I8254_BCD, I8254_BINARY
 477
 478  0 ID: INSN_CONFIG_8254_READ_STATUS
 479  1 <-- Status byte returned here.
 480    B7 = Output
 481    B6 = NULL Count
 482    B5 - B0 Current mode.
 483
 484*/
 485
 486        enum i8254_mode {
 487                I8254_MODE0 = (0 << 1), /* Interrupt on terminal count */
 488                I8254_MODE1 = (1 << 1), /* Hardware retriggerable one-shot */
 489                I8254_MODE2 = (2 << 1), /* Rate generator */
 490                I8254_MODE3 = (3 << 1), /* Square wave mode */
 491                I8254_MODE4 = (4 << 1), /* Software triggered strobe */
 492                I8254_MODE5 = (5 << 1), /* Hardware triggered strobe (retriggerable) */
 493                I8254_BCD = 1,  /* use binary-coded decimal instead of binary (pretty useless) */
 494                I8254_BINARY = 0
 495        };
 496
 497        static inline unsigned NI_USUAL_PFI_SELECT(unsigned pfi_channel) {
 498                if (pfi_channel < 10)
 499                        return 0x1 + pfi_channel;
 500                else
 501                        return 0xb + pfi_channel;
 502        } static inline unsigned NI_USUAL_RTSI_SELECT(unsigned rtsi_channel) {
 503                if (rtsi_channel < 7)
 504                        return 0xb + rtsi_channel;
 505                else
 506                        return 0x1b;
 507        }
 508/* mode bits for NI general-purpose counters, set with
 509 * INSN_CONFIG_SET_COUNTER_MODE */
 510#define NI_GPCT_COUNTING_MODE_SHIFT 16
 511#define NI_GPCT_INDEX_PHASE_BITSHIFT 20
 512#define NI_GPCT_COUNTING_DIRECTION_SHIFT 24
 513        enum ni_gpct_mode_bits {
 514                NI_GPCT_GATE_ON_BOTH_EDGES_BIT = 0x4,
 515                NI_GPCT_EDGE_GATE_MODE_MASK = 0x18,
 516                NI_GPCT_EDGE_GATE_STARTS_STOPS_BITS = 0x0,
 517                NI_GPCT_EDGE_GATE_STOPS_STARTS_BITS = 0x8,
 518                NI_GPCT_EDGE_GATE_STARTS_BITS = 0x10,
 519                NI_GPCT_EDGE_GATE_NO_STARTS_NO_STOPS_BITS = 0x18,
 520                NI_GPCT_STOP_MODE_MASK = 0x60,
 521                NI_GPCT_STOP_ON_GATE_BITS = 0x00,
 522                NI_GPCT_STOP_ON_GATE_OR_TC_BITS = 0x20,
 523                NI_GPCT_STOP_ON_GATE_OR_SECOND_TC_BITS = 0x40,
 524                NI_GPCT_LOAD_B_SELECT_BIT = 0x80,
 525                NI_GPCT_OUTPUT_MODE_MASK = 0x300,
 526                NI_GPCT_OUTPUT_TC_PULSE_BITS = 0x100,
 527                NI_GPCT_OUTPUT_TC_TOGGLE_BITS = 0x200,
 528                NI_GPCT_OUTPUT_TC_OR_GATE_TOGGLE_BITS = 0x300,
 529                NI_GPCT_HARDWARE_DISARM_MASK = 0xc00,
 530                NI_GPCT_NO_HARDWARE_DISARM_BITS = 0x000,
 531                NI_GPCT_DISARM_AT_TC_BITS = 0x400,
 532                NI_GPCT_DISARM_AT_GATE_BITS = 0x800,
 533                NI_GPCT_DISARM_AT_TC_OR_GATE_BITS = 0xc00,
 534                NI_GPCT_LOADING_ON_TC_BIT = 0x1000,
 535                NI_GPCT_LOADING_ON_GATE_BIT = 0x4000,
 536                NI_GPCT_COUNTING_MODE_MASK = 0x7 << NI_GPCT_COUNTING_MODE_SHIFT,
 537                NI_GPCT_COUNTING_MODE_NORMAL_BITS =
 538                    0x0 << NI_GPCT_COUNTING_MODE_SHIFT,
 539                NI_GPCT_COUNTING_MODE_QUADRATURE_X1_BITS =
 540                    0x1 << NI_GPCT_COUNTING_MODE_SHIFT,
 541                NI_GPCT_COUNTING_MODE_QUADRATURE_X2_BITS =
 542                    0x2 << NI_GPCT_COUNTING_MODE_SHIFT,
 543                NI_GPCT_COUNTING_MODE_QUADRATURE_X4_BITS =
 544                    0x3 << NI_GPCT_COUNTING_MODE_SHIFT,
 545                NI_GPCT_COUNTING_MODE_TWO_PULSE_BITS =
 546                    0x4 << NI_GPCT_COUNTING_MODE_SHIFT,
 547                NI_GPCT_COUNTING_MODE_SYNC_SOURCE_BITS =
 548                    0x6 << NI_GPCT_COUNTING_MODE_SHIFT,
 549                NI_GPCT_INDEX_PHASE_MASK = 0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 550                NI_GPCT_INDEX_PHASE_LOW_A_LOW_B_BITS =
 551                    0x0 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 552                NI_GPCT_INDEX_PHASE_LOW_A_HIGH_B_BITS =
 553                    0x1 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 554                NI_GPCT_INDEX_PHASE_HIGH_A_LOW_B_BITS =
 555                    0x2 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 556                NI_GPCT_INDEX_PHASE_HIGH_A_HIGH_B_BITS =
 557                    0x3 << NI_GPCT_INDEX_PHASE_BITSHIFT,
 558                NI_GPCT_INDEX_ENABLE_BIT = 0x400000,
 559                NI_GPCT_COUNTING_DIRECTION_MASK =
 560                    0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 561                NI_GPCT_COUNTING_DIRECTION_DOWN_BITS =
 562                    0x00 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 563                NI_GPCT_COUNTING_DIRECTION_UP_BITS =
 564                    0x1 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 565                NI_GPCT_COUNTING_DIRECTION_HW_UP_DOWN_BITS =
 566                    0x2 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 567                NI_GPCT_COUNTING_DIRECTION_HW_GATE_BITS =
 568                    0x3 << NI_GPCT_COUNTING_DIRECTION_SHIFT,
 569                NI_GPCT_RELOAD_SOURCE_MASK = 0xc000000,
 570                NI_GPCT_RELOAD_SOURCE_FIXED_BITS = 0x0,
 571                NI_GPCT_RELOAD_SOURCE_SWITCHING_BITS = 0x4000000,
 572                NI_GPCT_RELOAD_SOURCE_GATE_SELECT_BITS = 0x8000000,
 573                NI_GPCT_OR_GATE_BIT = 0x10000000,
 574                NI_GPCT_INVERT_OUTPUT_BIT = 0x20000000
 575        };
 576
 577/* Bits for setting a clock source with
 578 * INSN_CONFIG_SET_CLOCK_SRC when using NI general-purpose counters. */
 579        enum ni_gpct_clock_source_bits {
 580                NI_GPCT_CLOCK_SRC_SELECT_MASK = 0x3f,
 581                NI_GPCT_TIMEBASE_1_CLOCK_SRC_BITS = 0x0,
 582                NI_GPCT_TIMEBASE_2_CLOCK_SRC_BITS = 0x1,
 583                NI_GPCT_TIMEBASE_3_CLOCK_SRC_BITS = 0x2,
 584                NI_GPCT_LOGIC_LOW_CLOCK_SRC_BITS = 0x3,
 585                NI_GPCT_NEXT_GATE_CLOCK_SRC_BITS = 0x4,
 586                NI_GPCT_NEXT_TC_CLOCK_SRC_BITS = 0x5,
 587                NI_GPCT_SOURCE_PIN_i_CLOCK_SRC_BITS = 0x6,      /* NI 660x-specific */
 588                NI_GPCT_PXI10_CLOCK_SRC_BITS = 0x7,
 589                NI_GPCT_PXI_STAR_TRIGGER_CLOCK_SRC_BITS = 0x8,
 590                NI_GPCT_ANALOG_TRIGGER_OUT_CLOCK_SRC_BITS = 0x9,
 591                NI_GPCT_PRESCALE_MODE_CLOCK_SRC_MASK = 0x30000000,
 592                NI_GPCT_NO_PRESCALE_CLOCK_SRC_BITS = 0x0,
 593                NI_GPCT_PRESCALE_X2_CLOCK_SRC_BITS = 0x10000000,        /* divide source by 2 */
 594                NI_GPCT_PRESCALE_X8_CLOCK_SRC_BITS = 0x20000000,        /* divide source by 8 */
 595                NI_GPCT_INVERT_CLOCK_SRC_BIT = 0x80000000
 596        };
 597        static inline unsigned NI_GPCT_SOURCE_PIN_CLOCK_SRC_BITS(unsigned n) {
 598                /* NI 660x-specific */
 599                return 0x10 + n;
 600        }
 601        static inline unsigned NI_GPCT_RTSI_CLOCK_SRC_BITS(unsigned n) {
 602                return 0x18 + n;
 603        }
 604        static inline unsigned NI_GPCT_PFI_CLOCK_SRC_BITS(unsigned n) {
 605                /* no pfi on NI 660x */
 606                return 0x20 + n;
 607        }
 608
 609/* Possibilities for setting a gate source with
 610INSN_CONFIG_SET_GATE_SRC when using NI general-purpose counters.
 611May be bitwise-or'd with CR_EDGE or CR_INVERT. */
 612        enum ni_gpct_gate_select {
 613                /* m-series gates */
 614                NI_GPCT_TIMESTAMP_MUX_GATE_SELECT = 0x0,
 615                NI_GPCT_AI_START2_GATE_SELECT = 0x12,
 616                NI_GPCT_PXI_STAR_TRIGGER_GATE_SELECT = 0x13,
 617                NI_GPCT_NEXT_OUT_GATE_SELECT = 0x14,
 618                NI_GPCT_AI_START1_GATE_SELECT = 0x1c,
 619                NI_GPCT_NEXT_SOURCE_GATE_SELECT = 0x1d,
 620                NI_GPCT_ANALOG_TRIGGER_OUT_GATE_SELECT = 0x1e,
 621                NI_GPCT_LOGIC_LOW_GATE_SELECT = 0x1f,
 622                /* more gates for 660x */
 623                NI_GPCT_SOURCE_PIN_i_GATE_SELECT = 0x100,
 624                NI_GPCT_GATE_PIN_i_GATE_SELECT = 0x101,
 625                /* more gates for 660x "second gate" */
 626                NI_GPCT_UP_DOWN_PIN_i_GATE_SELECT = 0x201,
 627                NI_GPCT_SELECTED_GATE_GATE_SELECT = 0x21e,
 628                /* m-series "second gate" sources are unknown,
 629                   we should add them here with an offset of 0x300 when known. */
 630                NI_GPCT_DISABLED_GATE_SELECT = 0x8000,
 631        };
 632        static inline unsigned NI_GPCT_GATE_PIN_GATE_SELECT(unsigned n) {
 633                return 0x102 + n;
 634        }
 635        static inline unsigned NI_GPCT_RTSI_GATE_SELECT(unsigned n) {
 636                return NI_USUAL_RTSI_SELECT(n);
 637        }
 638        static inline unsigned NI_GPCT_PFI_GATE_SELECT(unsigned n) {
 639                return NI_USUAL_PFI_SELECT(n);
 640        }
 641        static inline unsigned NI_GPCT_UP_DOWN_PIN_GATE_SELECT(unsigned n) {
 642                return 0x202 + n;
 643        }
 644
 645/* Possibilities for setting a source with
 646INSN_CONFIG_SET_OTHER_SRC when using NI general-purpose counters. */
 647        enum ni_gpct_other_index {
 648                NI_GPCT_SOURCE_ENCODER_A,
 649                NI_GPCT_SOURCE_ENCODER_B,
 650                NI_GPCT_SOURCE_ENCODER_Z
 651        };
 652        enum ni_gpct_other_select {
 653                /* m-series gates */
 654                /* Still unknown, probably only need NI_GPCT_PFI_OTHER_SELECT */
 655                NI_GPCT_DISABLED_OTHER_SELECT = 0x8000,
 656        };
 657        static inline unsigned NI_GPCT_PFI_OTHER_SELECT(unsigned n) {
 658                return NI_USUAL_PFI_SELECT(n);
 659        }
 660
 661/* start sources for ni general-purpose counters for use with
 662INSN_CONFIG_ARM */
 663        enum ni_gpct_arm_source {
 664                NI_GPCT_ARM_IMMEDIATE = 0x0,
 665                NI_GPCT_ARM_PAIRED_IMMEDIATE = 0x1,     /* Start both the counter and
 666                                                           the adjacent paired counter
 667                                                           simultaneously */
 668                /* NI doesn't document bits for selecting hardware arm triggers.  If
 669                 * the NI_GPCT_ARM_UNKNOWN bit is set, we will pass the least
 670                 * significant bits (3 bits for 660x or 5 bits for m-series) through to
 671                 * the hardware.  This will at least allow someone to figure out what
 672                 * the bits do later. */
 673                NI_GPCT_ARM_UNKNOWN = 0x1000,
 674        };
 675
 676/* digital filtering options for ni 660x for use with INSN_CONFIG_FILTER. */
 677        enum ni_gpct_filter_select {
 678                NI_GPCT_FILTER_OFF = 0x0,
 679                NI_GPCT_FILTER_TIMEBASE_3_SYNC = 0x1,
 680                NI_GPCT_FILTER_100x_TIMEBASE_1 = 0x2,
 681                NI_GPCT_FILTER_20x_TIMEBASE_1 = 0x3,
 682                NI_GPCT_FILTER_10x_TIMEBASE_1 = 0x4,
 683                NI_GPCT_FILTER_2x_TIMEBASE_1 = 0x5,
 684                NI_GPCT_FILTER_2x_TIMEBASE_3 = 0x6
 685        };
 686
 687/* PFI digital filtering options for ni m-series for use with
 688 * INSN_CONFIG_FILTER. */
 689        enum ni_pfi_filter_select {
 690                NI_PFI_FILTER_OFF = 0x0,
 691                NI_PFI_FILTER_125ns = 0x1,
 692                NI_PFI_FILTER_6425ns = 0x2,
 693                NI_PFI_FILTER_2550us = 0x3
 694        };
 695
 696/* master clock sources for ni mio boards and INSN_CONFIG_SET_CLOCK_SRC */
 697        enum ni_mio_clock_source {
 698                NI_MIO_INTERNAL_CLOCK = 0,
 699                NI_MIO_RTSI_CLOCK = 1,  /* doesn't work for m-series, use
 700                                           NI_MIO_PLL_RTSI_CLOCK() */
 701                /* the NI_MIO_PLL_* sources are m-series only */
 702                NI_MIO_PLL_PXI_STAR_TRIGGER_CLOCK = 2,
 703                NI_MIO_PLL_PXI10_CLOCK = 3,
 704                NI_MIO_PLL_RTSI0_CLOCK = 4
 705        };
 706        static inline unsigned NI_MIO_PLL_RTSI_CLOCK(unsigned rtsi_channel) {
 707                return NI_MIO_PLL_RTSI0_CLOCK + rtsi_channel;
 708        }
 709
 710/* Signals which can be routed to an NI RTSI pin with INSN_CONFIG_SET_ROUTING.
 711 The numbers assigned are not arbitrary, they correspond to the bits required
 712 to program the board. */
 713        enum ni_rtsi_routing {
 714                NI_RTSI_OUTPUT_ADR_START1 = 0,
 715                NI_RTSI_OUTPUT_ADR_START2 = 1,
 716                NI_RTSI_OUTPUT_SCLKG = 2,
 717                NI_RTSI_OUTPUT_DACUPDN = 3,
 718                NI_RTSI_OUTPUT_DA_START1 = 4,
 719                NI_RTSI_OUTPUT_G_SRC0 = 5,
 720                NI_RTSI_OUTPUT_G_GATE0 = 6,
 721                NI_RTSI_OUTPUT_RGOUT0 = 7,
 722                NI_RTSI_OUTPUT_RTSI_BRD_0 = 8,
 723                NI_RTSI_OUTPUT_RTSI_OSC = 12    /* pre-m-series always have RTSI clock
 724                                                   on line 7 */
 725        };
 726        static inline unsigned NI_RTSI_OUTPUT_RTSI_BRD(unsigned n) {
 727                return NI_RTSI_OUTPUT_RTSI_BRD_0 + n;
 728        }
 729
 730/* Signals which can be routed to an NI PFI pin on an m-series board with
 731 * INSN_CONFIG_SET_ROUTING.  These numbers are also returned by
 732 * INSN_CONFIG_GET_ROUTING on pre-m-series boards, even though their routing
 733 * cannot be changed.  The numbers assigned are not arbitrary, they correspond
 734 * to the bits required to program the board. */
 735        enum ni_pfi_routing {
 736                NI_PFI_OUTPUT_PFI_DEFAULT = 0,
 737                NI_PFI_OUTPUT_AI_START1 = 1,
 738                NI_PFI_OUTPUT_AI_START2 = 2,
 739                NI_PFI_OUTPUT_AI_CONVERT = 3,
 740                NI_PFI_OUTPUT_G_SRC1 = 4,
 741                NI_PFI_OUTPUT_G_GATE1 = 5,
 742                NI_PFI_OUTPUT_AO_UPDATE_N = 6,
 743                NI_PFI_OUTPUT_AO_START1 = 7,
 744                NI_PFI_OUTPUT_AI_START_PULSE = 8,
 745                NI_PFI_OUTPUT_G_SRC0 = 9,
 746                NI_PFI_OUTPUT_G_GATE0 = 10,
 747                NI_PFI_OUTPUT_EXT_STROBE = 11,
 748                NI_PFI_OUTPUT_AI_EXT_MUX_CLK = 12,
 749                NI_PFI_OUTPUT_GOUT0 = 13,
 750                NI_PFI_OUTPUT_GOUT1 = 14,
 751                NI_PFI_OUTPUT_FREQ_OUT = 15,
 752                NI_PFI_OUTPUT_PFI_DO = 16,
 753                NI_PFI_OUTPUT_I_ATRIG = 17,
 754                NI_PFI_OUTPUT_RTSI0 = 18,
 755                NI_PFI_OUTPUT_PXI_STAR_TRIGGER_IN = 26,
 756                NI_PFI_OUTPUT_SCXI_TRIG1 = 27,
 757                NI_PFI_OUTPUT_DIO_CHANGE_DETECT_RTSI = 28,
 758                NI_PFI_OUTPUT_CDI_SAMPLE = 29,
 759                NI_PFI_OUTPUT_CDO_UPDATE = 30
 760        };
 761        static inline unsigned NI_PFI_OUTPUT_RTSI(unsigned rtsi_channel) {
 762                return NI_PFI_OUTPUT_RTSI0 + rtsi_channel;
 763        }
 764
 765/* Signals which can be routed to output on a NI PFI pin on a 660x board
 766 with INSN_CONFIG_SET_ROUTING.  The numbers assigned are
 767 not arbitrary, they correspond to the bits required
 768 to program the board.  Lines 0 to 7 can only be set to
 769 NI_660X_PFI_OUTPUT_DIO.  Lines 32 to 39 can only be set to
 770 NI_660X_PFI_OUTPUT_COUNTER. */
 771        enum ni_660x_pfi_routing {
 772                NI_660X_PFI_OUTPUT_COUNTER = 1, /* counter */
 773                NI_660X_PFI_OUTPUT_DIO = 2,     /* static digital output */
 774        };
 775
 776/* NI External Trigger lines.  These values are not arbitrary, but are related
 777 * to the bits required to program the board (offset by 1 for historical
 778 * reasons). */
 779        static inline unsigned NI_EXT_PFI(unsigned pfi_channel) {
 780                return NI_USUAL_PFI_SELECT(pfi_channel) - 1;
 781        }
 782        static inline unsigned NI_EXT_RTSI(unsigned rtsi_channel) {
 783                return NI_USUAL_RTSI_SELECT(rtsi_channel) - 1;
 784        }
 785
 786/* status bits for INSN_CONFIG_GET_COUNTER_STATUS */
 787        enum comedi_counter_status_flags {
 788                COMEDI_COUNTER_ARMED = 0x1,
 789                COMEDI_COUNTER_COUNTING = 0x2,
 790                COMEDI_COUNTER_TERMINAL_COUNT = 0x4,
 791        };
 792
 793/* Clock sources for CDIO subdevice on NI m-series boards.  Used as the
 794 * scan_begin_arg for a comedi_command. These sources may also be bitwise-or'd
 795 * with CR_INVERT to change polarity. */
 796        enum ni_m_series_cdio_scan_begin_src {
 797                NI_CDIO_SCAN_BEGIN_SRC_GROUND = 0,
 798                NI_CDIO_SCAN_BEGIN_SRC_AI_START = 18,
 799                NI_CDIO_SCAN_BEGIN_SRC_AI_CONVERT = 19,
 800                NI_CDIO_SCAN_BEGIN_SRC_PXI_STAR_TRIGGER = 20,
 801                NI_CDIO_SCAN_BEGIN_SRC_G0_OUT = 28,
 802                NI_CDIO_SCAN_BEGIN_SRC_G1_OUT = 29,
 803                NI_CDIO_SCAN_BEGIN_SRC_ANALOG_TRIGGER = 30,
 804                NI_CDIO_SCAN_BEGIN_SRC_AO_UPDATE = 31,
 805                NI_CDIO_SCAN_BEGIN_SRC_FREQ_OUT = 32,
 806                NI_CDIO_SCAN_BEGIN_SRC_DIO_CHANGE_DETECT_IRQ = 33
 807        };
 808        static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) {
 809                return NI_USUAL_PFI_SELECT(pfi_channel);
 810        }
 811        static inline unsigned NI_CDIO_SCAN_BEGIN_SRC_RTSI(unsigned
 812                                                           rtsi_channel) {
 813                return NI_USUAL_RTSI_SELECT(rtsi_channel);
 814        }
 815
 816/* scan_begin_src for scan_begin_arg==TRIG_EXT with analog output command on NI
 817 * boards.  These scan begin sources can also be bitwise-or'd with CR_INVERT to
 818 * change polarity. */
 819        static inline unsigned NI_AO_SCAN_BEGIN_SRC_PFI(unsigned pfi_channel) {
 820                return NI_USUAL_PFI_SELECT(pfi_channel);
 821        }
 822        static inline unsigned NI_AO_SCAN_BEGIN_SRC_RTSI(unsigned rtsi_channel) {
 823                return NI_USUAL_RTSI_SELECT(rtsi_channel);
 824        }
 825
 826/* Bits for setting a clock source with
 827 * INSN_CONFIG_SET_CLOCK_SRC when using NI frequency output subdevice. */
 828        enum ni_freq_out_clock_source_bits {
 829                NI_FREQ_OUT_TIMEBASE_1_DIV_2_CLOCK_SRC, /* 10 MHz */
 830                NI_FREQ_OUT_TIMEBASE_2_CLOCK_SRC        /* 100 KHz */
 831        };
 832
 833/* Values for setting a clock source with INSN_CONFIG_SET_CLOCK_SRC for
 834 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 835        enum amplc_dio_clock_source {
 836                AMPLC_DIO_CLK_CLKN,     /* per channel external clock
 837                                           input/output pin (pin is only an
 838                                           input when clock source set to this
 839                                           value, otherwise it is an output) */
 840                AMPLC_DIO_CLK_10MHZ,    /* 10 MHz internal clock */
 841                AMPLC_DIO_CLK_1MHZ,     /* 1 MHz internal clock */
 842                AMPLC_DIO_CLK_100KHZ,   /* 100 kHz internal clock */
 843                AMPLC_DIO_CLK_10KHZ,    /* 10 kHz internal clock */
 844                AMPLC_DIO_CLK_1KHZ,     /* 1 kHz internal clock */
 845                AMPLC_DIO_CLK_OUTNM1,   /* output of preceding counter channel
 846                                           (for channel 0, preceding counter
 847                                           channel is channel 2 on preceding
 848                                           counter subdevice, for first counter
 849                                           subdevice, preceding counter
 850                                           subdevice is the last counter
 851                                           subdevice) */
 852                AMPLC_DIO_CLK_EXT       /* per chip external input pin */
 853        };
 854
 855/* Values for setting a gate source with INSN_CONFIG_SET_GATE_SRC for
 856 * 8254 counter subdevices on Amplicon DIO boards (amplc_dio200 driver). */
 857        enum amplc_dio_gate_source {
 858                AMPLC_DIO_GAT_VCC,      /* internal high logic level */
 859                AMPLC_DIO_GAT_GND,      /* internal low logic level */
 860                AMPLC_DIO_GAT_GATN,     /* per channel external gate input */
 861                AMPLC_DIO_GAT_NOUTNM2,  /* negated output of counter channel
 862                                           minus 2 (for channels 0 or 1,
 863                                           channel minus 2 is channel 1 or 2 on
 864                                           the preceding counter subdevice, for
 865                                           the first counter subdevice the
 866                                           preceding counter subdevice is the
 867                                           last counter subdevice) */
 868                AMPLC_DIO_GAT_RESERVED4,
 869                AMPLC_DIO_GAT_RESERVED5,
 870                AMPLC_DIO_GAT_RESERVED6,
 871                AMPLC_DIO_GAT_RESERVED7
 872        };
 873
 874#ifdef __cplusplus
 875}
 876#endif
 877
 878#endif /* _COMEDI_H */
 879