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24#ifndef _MITE_H_
25#define _MITE_H_
26
27#include <linux/pci.h>
28#include "../comedidev.h"
29
30#define PCI_VENDOR_ID_NATINST 0x1093
31
32
33#define PCIMIO_COMPAT
34
35#ifdef DEBUG_MITE
36#define MDPRINTK(format, args...) printk(format , ## args)
37#else
38#define MDPRINTK(format, args...)
39#endif
40
41#define MAX_MITE_DMA_CHANNELS 8
42
43struct mite_dma_descriptor {
44 u32 count;
45 u32 addr;
46 u32 next;
47 u32 dar;
48};
49
50struct mite_dma_descriptor_ring {
51 struct device *hw_dev;
52 unsigned int n_links;
53 struct mite_dma_descriptor *descriptors;
54 dma_addr_t descriptors_dma_addr;
55};
56
57struct mite_channel {
58 struct mite_struct *mite;
59 unsigned channel;
60 int dir;
61 int done;
62 struct mite_dma_descriptor_ring *ring;
63};
64
65struct mite_struct {
66 struct mite_struct *next;
67 int used;
68
69 struct pci_dev *pcidev;
70 resource_size_t mite_phys_addr;
71 void *mite_io_addr;
72 resource_size_t daq_phys_addr;
73 void *daq_io_addr;
74
75 struct mite_channel channels[MAX_MITE_DMA_CHANNELS];
76 short channel_allocated[MAX_MITE_DMA_CHANNELS];
77 int num_channels;
78 unsigned fifo_size;
79 spinlock_t lock;
80};
81
82static inline struct mite_dma_descriptor_ring *mite_alloc_ring(struct
83 mite_struct
84 *mite)
85{
86 struct mite_dma_descriptor_ring *ring =
87 kmalloc(sizeof(struct mite_dma_descriptor_ring), GFP_KERNEL);
88 if (ring == NULL)
89 return ring;
90 ring->hw_dev = get_device(&mite->pcidev->dev);
91 if (ring->hw_dev == NULL) {
92 kfree(ring);
93 return NULL;
94 }
95 ring->n_links = 0;
96 ring->descriptors = NULL;
97 ring->descriptors_dma_addr = 0;
98 return ring;
99};
100
101static inline void mite_free_ring(struct mite_dma_descriptor_ring *ring)
102{
103 if (ring) {
104 if (ring->descriptors) {
105 dma_free_coherent(ring->hw_dev,
106 ring->n_links *
107 sizeof(struct mite_dma_descriptor),
108 ring->descriptors,
109 ring->descriptors_dma_addr);
110 }
111 put_device(ring->hw_dev);
112 kfree(ring);
113 }
114};
115
116extern struct mite_struct *mite_devices;
117
118static inline unsigned int mite_irq(struct mite_struct *mite)
119{
120 return mite->pcidev->irq;
121};
122
123static inline unsigned int mite_device_id(struct mite_struct *mite)
124{
125 return mite->pcidev->device;
126};
127
128void mite_init(void);
129void mite_cleanup(void);
130int mite_setup(struct mite_struct *mite);
131int mite_setup2(struct mite_struct *mite, unsigned use_iodwbsr_1);
132void mite_unsetup(struct mite_struct *mite);
133void mite_list_devices(void);
134struct mite_channel *mite_request_channel_in_range(struct mite_struct *mite,
135 struct
136 mite_dma_descriptor_ring
137 *ring, unsigned min_channel,
138 unsigned max_channel);
139static inline struct mite_channel *mite_request_channel(struct mite_struct
140 *mite,
141 struct
142 mite_dma_descriptor_ring
143 *ring)
144{
145 return mite_request_channel_in_range(mite, ring, 0,
146 mite->num_channels - 1);
147}
148
149void mite_release_channel(struct mite_channel *mite_chan);
150
151unsigned mite_dma_tcr(struct mite_channel *mite_chan);
152void mite_dma_arm(struct mite_channel *mite_chan);
153void mite_dma_disarm(struct mite_channel *mite_chan);
154int mite_sync_input_dma(struct mite_channel *mite_chan,
155 struct comedi_async *async);
156int mite_sync_output_dma(struct mite_channel *mite_chan,
157 struct comedi_async *async);
158u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan);
159u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan);
160u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan);
161u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan);
162u32 mite_bytes_in_transit(struct mite_channel *mite_chan);
163unsigned mite_get_status(struct mite_channel *mite_chan);
164int mite_done(struct mite_channel *mite_chan);
165
166#if 0
167unsigned long mite_ll_from_kvmem(struct mite_struct *mite,
168 struct comedi_async *async, int len);
169void mite_setregs(struct mite_struct *mite, unsigned long ll_start, int chan,
170 int dir);
171#endif
172
173void mite_prep_dma(struct mite_channel *mite_chan,
174 unsigned int num_device_bits, unsigned int num_memory_bits);
175int mite_buf_change(struct mite_dma_descriptor_ring *ring,
176 struct comedi_async *async);
177
178#ifdef DEBUG_MITE
179void mite_print_chsr(unsigned int chsr);
180void mite_dump_regs(struct mite_channel *mite_chan);
181#endif
182
183static inline int CHAN_OFFSET(int channel)
184{
185 return 0x500 + 0x100 * channel;
186};
187
188enum mite_registers {
189
190
191
192 MITE_UNKNOWN_DMA_BURST_REG = 0x28,
193 MITE_IODWBSR = 0xc0,
194 MITE_IODWBSR_1 = 0xc4,
195 MITE_IODWCR_1 = 0xf4,
196 MITE_PCI_CONFIG_OFFSET = 0x300,
197 MITE_CSIGR = 0x460
198};
199static inline int MITE_CHOR(int channel)
200{
201 return CHAN_OFFSET(channel) + 0x0;
202};
203
204static inline int MITE_CHCR(int channel)
205{
206 return CHAN_OFFSET(channel) + 0x4;
207};
208
209static inline int MITE_TCR(int channel)
210{
211 return CHAN_OFFSET(channel) + 0x8;
212};
213
214static inline int MITE_MCR(int channel)
215{
216 return CHAN_OFFSET(channel) + 0xc;
217};
218
219static inline int MITE_MAR(int channel)
220{
221 return CHAN_OFFSET(channel) + 0x10;
222};
223
224static inline int MITE_DCR(int channel)
225{
226 return CHAN_OFFSET(channel) + 0x14;
227};
228
229static inline int MITE_DAR(int channel)
230{
231 return CHAN_OFFSET(channel) + 0x18;
232};
233
234static inline int MITE_LKCR(int channel)
235{
236 return CHAN_OFFSET(channel) + 0x1c;
237};
238
239static inline int MITE_LKAR(int channel)
240{
241 return CHAN_OFFSET(channel) + 0x20;
242};
243
244static inline int MITE_LLKAR(int channel)
245{
246 return CHAN_OFFSET(channel) + 0x24;
247};
248
249static inline int MITE_BAR(int channel)
250{
251 return CHAN_OFFSET(channel) + 0x28;
252};
253
254static inline int MITE_BCR(int channel)
255{
256 return CHAN_OFFSET(channel) + 0x2c;
257};
258
259static inline int MITE_SAR(int channel)
260{
261 return CHAN_OFFSET(channel) + 0x30;
262};
263
264static inline int MITE_WSCR(int channel)
265{
266 return CHAN_OFFSET(channel) + 0x34;
267};
268
269static inline int MITE_WSER(int channel)
270{
271 return CHAN_OFFSET(channel) + 0x38;
272};
273
274static inline int MITE_CHSR(int channel)
275{
276 return CHAN_OFFSET(channel) + 0x3c;
277};
278
279static inline int MITE_FCR(int channel)
280{
281 return CHAN_OFFSET(channel) + 0x40;
282};
283
284enum MITE_IODWBSR_bits {
285 WENAB = 0x80,
286};
287
288static inline unsigned MITE_IODWBSR_1_WSIZE_bits(unsigned size)
289{
290 unsigned order = 0;
291 while (size >>= 1)
292 ++order;
293 BUG_ON(order < 1);
294 return (order - 1) & 0x1f;
295}
296
297enum MITE_UNKNOWN_DMA_BURST_bits {
298 UNKNOWN_DMA_BURST_ENABLE_BITS = 0x600
299};
300
301static inline int mite_csigr_version(u32 csigr_bits)
302{
303 return csigr_bits & 0xf;
304};
305
306static inline int mite_csigr_type(u32 csigr_bits)
307{
308 return (csigr_bits >> 4) & 0xf;
309};
310
311static inline int mite_csigr_mmode(u32 csigr_bits)
312{
313 return (csigr_bits >> 8) & 0x3;
314};
315
316static inline int mite_csigr_imode(u32 csigr_bits)
317{
318 return (csigr_bits >> 12) & 0x3;
319};
320
321static inline int mite_csigr_dmac(u32 csigr_bits)
322{
323 return (csigr_bits >> 16) & 0xf;
324};
325
326static inline int mite_csigr_wpdep(u32 csigr_bits)
327{
328 unsigned int wpdep_bits = (csigr_bits >> 20) & 0x7;
329 if (wpdep_bits == 0)
330 return 0;
331 else
332 return 1 << (wpdep_bits - 1);
333};
334
335static inline int mite_csigr_wins(u32 csigr_bits)
336{
337 return (csigr_bits >> 24) & 0x1f;
338};
339
340static inline int mite_csigr_iowins(u32 csigr_bits)
341{
342 return (csigr_bits >> 29) & 0x7;
343};
344
345enum MITE_MCR_bits {
346 MCRPON = 0,
347};
348
349enum MITE_DCR_bits {
350 DCR_NORMAL = (1 << 29),
351 DCRPON = 0,
352};
353
354enum MITE_CHOR_bits {
355 CHOR_DMARESET = (1 << 31),
356 CHOR_SET_SEND_TC = (1 << 11),
357 CHOR_CLR_SEND_TC = (1 << 10),
358 CHOR_SET_LPAUSE = (1 << 9),
359 CHOR_CLR_LPAUSE = (1 << 8),
360 CHOR_CLRDONE = (1 << 7),
361 CHOR_CLRRB = (1 << 6),
362 CHOR_CLRLC = (1 << 5),
363 CHOR_FRESET = (1 << 4),
364 CHOR_ABORT = (1 << 3),
365 CHOR_STOP = (1 << 2),
366 CHOR_CONT = (1 << 1),
367 CHOR_START = (1 << 0),
368 CHOR_PON = (CHOR_CLR_SEND_TC | CHOR_CLR_LPAUSE),
369};
370
371enum MITE_CHCR_bits {
372 CHCR_SET_DMA_IE = (1 << 31),
373 CHCR_CLR_DMA_IE = (1 << 30),
374 CHCR_SET_LINKP_IE = (1 << 29),
375 CHCR_CLR_LINKP_IE = (1 << 28),
376 CHCR_SET_SAR_IE = (1 << 27),
377 CHCR_CLR_SAR_IE = (1 << 26),
378 CHCR_SET_DONE_IE = (1 << 25),
379 CHCR_CLR_DONE_IE = (1 << 24),
380 CHCR_SET_MRDY_IE = (1 << 23),
381 CHCR_CLR_MRDY_IE = (1 << 22),
382 CHCR_SET_DRDY_IE = (1 << 21),
383 CHCR_CLR_DRDY_IE = (1 << 20),
384 CHCR_SET_LC_IE = (1 << 19),
385 CHCR_CLR_LC_IE = (1 << 18),
386 CHCR_SET_CONT_RB_IE = (1 << 17),
387 CHCR_CLR_CONT_RB_IE = (1 << 16),
388 CHCR_FIFODIS = (1 << 15),
389 CHCR_FIFO_ON = 0,
390 CHCR_BURSTEN = (1 << 14),
391 CHCR_NO_BURSTEN = 0,
392 CHCR_BYTE_SWAP_DEVICE = (1 << 6),
393 CHCR_BYTE_SWAP_MEMORY = (1 << 4),
394 CHCR_DIR = (1 << 3),
395 CHCR_DEV_TO_MEM = CHCR_DIR,
396 CHCR_MEM_TO_DEV = 0,
397 CHCR_NORMAL = (0 << 0),
398 CHCR_CONTINUE = (1 << 0),
399 CHCR_RINGBUFF = (2 << 0),
400 CHCR_LINKSHORT = (4 << 0),
401 CHCR_LINKLONG = (5 << 0),
402 CHCRPON =
403 (CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
404 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
405 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE),
406};
407
408enum ConfigRegister_bits {
409 CR_REQS_MASK = 0x7 << 16,
410 CR_ASEQDONT = 0x0 << 10,
411 CR_ASEQUP = 0x1 << 10,
412 CR_ASEQDOWN = 0x2 << 10,
413 CR_ASEQ_MASK = 0x3 << 10,
414 CR_PSIZE8 = (1 << 8),
415 CR_PSIZE16 = (2 << 8),
416 CR_PSIZE32 = (3 << 8),
417 CR_PORTCPU = (0 << 6),
418 CR_PORTIO = (1 << 6),
419 CR_PORTVXI = (2 << 6),
420 CR_PORTMXI = (3 << 6),
421 CR_AMDEVICE = (1 << 0),
422};
423static inline int CR_REQS(int source)
424{
425 return (source & 0x7) << 16;
426};
427
428static inline int CR_REQSDRQ(unsigned drq_line)
429{
430
431
432 return CR_REQS((drq_line & 0x3) | 0x4);
433}
434
435static inline int CR_RL(unsigned int retry_limit)
436{
437 int value = 0;
438
439 while (retry_limit) {
440 retry_limit >>= 1;
441 value++;
442 }
443 if (value > 0x7)
444 printk("comedi: bug! retry_limit too large\n");
445 return (value & 0x7) << 21;
446}
447
448enum CHSR_bits {
449 CHSR_INT = (1 << 31),
450 CHSR_LPAUSES = (1 << 29),
451 CHSR_SARS = (1 << 27),
452 CHSR_DONE = (1 << 25),
453 CHSR_MRDY = (1 << 23),
454 CHSR_DRDY = (1 << 21),
455 CHSR_LINKC = (1 << 19),
456 CHSR_CONTS_RB = (1 << 17),
457 CHSR_ERROR = (1 << 15),
458 CHSR_SABORT = (1 << 14),
459 CHSR_HABORT = (1 << 13),
460 CHSR_STOPS = (1 << 12),
461 CHSR_OPERR_mask = (3 << 10),
462 CHSR_OPERR_NOERROR = (0 << 10),
463 CHSR_OPERR_FIFOERROR = (1 << 10),
464 CHSR_OPERR_LINKERROR = (1 << 10),
465 CHSR_XFERR = (1 << 9),
466 CHSR_END = (1 << 8),
467 CHSR_DRQ1 = (1 << 7),
468 CHSR_DRQ0 = (1 << 6),
469 CHSR_LxERR_mask = (3 << 4),
470 CHSR_LBERR = (1 << 4),
471 CHSR_LRERR = (2 << 4),
472 CHSR_LOERR = (3 << 4),
473 CHSR_MxERR_mask = (3 << 2),
474 CHSR_MBERR = (1 << 2),
475 CHSR_MRERR = (2 << 2),
476 CHSR_MOERR = (3 << 2),
477 CHSR_DxERR_mask = (3 << 0),
478 CHSR_DBERR = (1 << 0),
479 CHSR_DRERR = (2 << 0),
480 CHSR_DOERR = (3 << 0),
481};
482
483static inline void mite_dma_reset(struct mite_channel *mite_chan)
484{
485 writel(CHOR_DMARESET | CHOR_FRESET,
486 mite_chan->mite->mite_io_addr + MITE_CHOR(mite_chan->channel));
487};
488
489#endif
490
