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24#ifndef _COMEDI_NI_TIO_INTERNAL_H
25#define _COMEDI_NI_TIO_INTERNAL_H
26
27#include "ni_tio.h"
28
29static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
30 counter_index)
31{
32 switch (counter_index) {
33 case 0:
34 return NITIO_G0_Autoincrement_Reg;
35 break;
36 case 1:
37 return NITIO_G1_Autoincrement_Reg;
38 break;
39 case 2:
40 return NITIO_G2_Autoincrement_Reg;
41 break;
42 case 3:
43 return NITIO_G3_Autoincrement_Reg;
44 break;
45 default:
46 BUG();
47 break;
48 }
49 return 0;
50}
51
52static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
53{
54 switch (counter_index) {
55 case 0:
56 return NITIO_G0_Command_Reg;
57 break;
58 case 1:
59 return NITIO_G1_Command_Reg;
60 break;
61 case 2:
62 return NITIO_G2_Command_Reg;
63 break;
64 case 3:
65 return NITIO_G3_Command_Reg;
66 break;
67 default:
68 BUG();
69 break;
70 }
71 return 0;
72}
73
74static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
75 counter_index)
76{
77 switch (counter_index) {
78 case 0:
79 return NITIO_G0_Counting_Mode_Reg;
80 break;
81 case 1:
82 return NITIO_G1_Counting_Mode_Reg;
83 break;
84 case 2:
85 return NITIO_G2_Counting_Mode_Reg;
86 break;
87 case 3:
88 return NITIO_G3_Counting_Mode_Reg;
89 break;
90 default:
91 BUG();
92 break;
93 }
94 return 0;
95}
96
97static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
98 counter_index)
99{
100 switch (counter_index) {
101 case 0:
102 return NITIO_G0_Input_Select_Reg;
103 break;
104 case 1:
105 return NITIO_G1_Input_Select_Reg;
106 break;
107 case 2:
108 return NITIO_G2_Input_Select_Reg;
109 break;
110 case 3:
111 return NITIO_G3_Input_Select_Reg;
112 break;
113 default:
114 BUG();
115 break;
116 }
117 return 0;
118}
119
120static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
121 counter_index)
122{
123 switch (counter_index) {
124 case 0:
125 case 1:
126 return NITIO_G01_Joint_Reset_Reg;
127 break;
128 case 2:
129 case 3:
130 return NITIO_G23_Joint_Reset_Reg;
131 break;
132 default:
133 BUG();
134 break;
135 }
136 return 0;
137}
138
139static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
140 counter_index)
141{
142 switch (counter_index) {
143 case 0:
144 case 1:
145 return NITIO_G01_Joint_Status1_Reg;
146 break;
147 case 2:
148 case 3:
149 return NITIO_G23_Joint_Status1_Reg;
150 break;
151 default:
152 BUG();
153 break;
154 }
155 return 0;
156}
157
158static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
159 counter_index)
160{
161 switch (counter_index) {
162 case 0:
163 case 1:
164 return NITIO_G01_Joint_Status2_Reg;
165 break;
166 case 2:
167 case 3:
168 return NITIO_G23_Joint_Status2_Reg;
169 break;
170 default:
171 BUG();
172 break;
173 }
174 return 0;
175}
176
177static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
178{
179 switch (counter_index) {
180 case 0:
181 case 1:
182 return NITIO_G01_Status_Reg;
183 break;
184 case 2:
185 case 3:
186 return NITIO_G23_Status_Reg;
187 break;
188 default:
189 BUG();
190 break;
191 }
192 return 0;
193}
194
195static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
196{
197 switch (counter_index) {
198 case 0:
199 return NITIO_G0_LoadA_Reg;
200 break;
201 case 1:
202 return NITIO_G1_LoadA_Reg;
203 break;
204 case 2:
205 return NITIO_G2_LoadA_Reg;
206 break;
207 case 3:
208 return NITIO_G3_LoadA_Reg;
209 break;
210 default:
211 BUG();
212 break;
213 }
214 return 0;
215}
216
217static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
218{
219 switch (counter_index) {
220 case 0:
221 return NITIO_G0_LoadB_Reg;
222 break;
223 case 1:
224 return NITIO_G1_LoadB_Reg;
225 break;
226 case 2:
227 return NITIO_G2_LoadB_Reg;
228 break;
229 case 3:
230 return NITIO_G3_LoadB_Reg;
231 break;
232 default:
233 BUG();
234 break;
235 }
236 return 0;
237}
238
239static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
240{
241 switch (counter_index) {
242 case 0:
243 return NITIO_G0_Mode_Reg;
244 break;
245 case 1:
246 return NITIO_G1_Mode_Reg;
247 break;
248 case 2:
249 return NITIO_G2_Mode_Reg;
250 break;
251 case 3:
252 return NITIO_G3_Mode_Reg;
253 break;
254 default:
255 BUG();
256 break;
257 }
258 return 0;
259}
260
261static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
262{
263 switch (counter_index) {
264 case 0:
265 return NITIO_G0_SW_Save_Reg;
266 break;
267 case 1:
268 return NITIO_G1_SW_Save_Reg;
269 break;
270 case 2:
271 return NITIO_G2_SW_Save_Reg;
272 break;
273 case 3:
274 return NITIO_G3_SW_Save_Reg;
275 break;
276 default:
277 BUG();
278 break;
279 }
280 return 0;
281}
282
283static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
284{
285 switch (counter_index) {
286 case 0:
287 return NITIO_G0_Second_Gate_Reg;
288 break;
289 case 1:
290 return NITIO_G1_Second_Gate_Reg;
291 break;
292 case 2:
293 return NITIO_G2_Second_Gate_Reg;
294 break;
295 case 3:
296 return NITIO_G3_Second_Gate_Reg;
297 break;
298 default:
299 BUG();
300 break;
301 }
302 return 0;
303}
304
305static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
306{
307 switch (counter_index) {
308 case 0:
309 return NITIO_G0_DMA_Config_Reg;
310 break;
311 case 1:
312 return NITIO_G1_DMA_Config_Reg;
313 break;
314 case 2:
315 return NITIO_G2_DMA_Config_Reg;
316 break;
317 case 3:
318 return NITIO_G3_DMA_Config_Reg;
319 break;
320 default:
321 BUG();
322 break;
323 }
324 return 0;
325}
326
327static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
328{
329 switch (counter_index) {
330 case 0:
331 return NITIO_G0_DMA_Status_Reg;
332 break;
333 case 1:
334 return NITIO_G1_DMA_Status_Reg;
335 break;
336 case 2:
337 return NITIO_G2_DMA_Status_Reg;
338 break;
339 case 3:
340 return NITIO_G3_DMA_Status_Reg;
341 break;
342 default:
343 BUG();
344 break;
345 }
346 return 0;
347}
348
349static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
350{
351 switch (counter_index) {
352 case 0:
353 return NITIO_G0_ABZ_Reg;
354 break;
355 case 1:
356 return NITIO_G1_ABZ_Reg;
357 break;
358 default:
359 BUG();
360 break;
361 }
362 return 0;
363}
364
365static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(int
366 counter_index)
367{
368 switch (counter_index) {
369 case 0:
370 return NITIO_G0_Interrupt_Acknowledge_Reg;
371 break;
372 case 1:
373 return NITIO_G1_Interrupt_Acknowledge_Reg;
374 break;
375 case 2:
376 return NITIO_G2_Interrupt_Acknowledge_Reg;
377 break;
378 case 3:
379 return NITIO_G3_Interrupt_Acknowledge_Reg;
380 break;
381 default:
382 BUG();
383 break;
384 }
385 return 0;
386}
387
388static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
389{
390 switch (counter_index) {
391 case 0:
392 return NITIO_G0_Status_Reg;
393 break;
394 case 1:
395 return NITIO_G1_Status_Reg;
396 break;
397 case 2:
398 return NITIO_G2_Status_Reg;
399 break;
400 case 3:
401 return NITIO_G3_Status_Reg;
402 break;
403 default:
404 BUG();
405 break;
406 }
407 return 0;
408}
409
410static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(int
411 counter_index)
412{
413 switch (counter_index) {
414 case 0:
415 return NITIO_G0_Interrupt_Enable_Reg;
416 break;
417 case 1:
418 return NITIO_G1_Interrupt_Enable_Reg;
419 break;
420 case 2:
421 return NITIO_G2_Interrupt_Enable_Reg;
422 break;
423 case 3:
424 return NITIO_G3_Interrupt_Enable_Reg;
425 break;
426 default:
427 BUG();
428 break;
429 }
430 return 0;
431}
432
433enum Gi_Auto_Increment_Reg_Bits {
434 Gi_Auto_Increment_Mask = 0xff
435};
436
437#define Gi_Up_Down_Shift 5
438enum Gi_Command_Reg_Bits {
439 Gi_Arm_Bit = 0x1,
440 Gi_Save_Trace_Bit = 0x2,
441 Gi_Load_Bit = 0x4,
442 Gi_Disarm_Bit = 0x10,
443 Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
444 Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
445 Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
446 Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
447 Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
448 Gi_Write_Switch_Bit = 0x80,
449 Gi_Synchronize_Gate_Bit = 0x100,
450 Gi_Little_Big_Endian_Bit = 0x200,
451 Gi_Bank_Switch_Start_Bit = 0x400,
452 Gi_Bank_Switch_Mode_Bit = 0x800,
453 Gi_Bank_Switch_Enable_Bit = 0x1000,
454 Gi_Arm_Copy_Bit = 0x2000,
455 Gi_Save_Trace_Copy_Bit = 0x4000,
456 Gi_Disarm_Copy_Bit = 0x8000
457};
458
459#define Gi_Index_Phase_Bitshift 5
460#define Gi_HW_Arm_Select_Shift 8
461enum Gi_Counting_Mode_Reg_Bits {
462 Gi_Counting_Mode_Mask = 0x7,
463 Gi_Counting_Mode_Normal_Bits = 0x0,
464 Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
465 Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
466 Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
467 Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
468 Gi_Counting_Mode_Sync_Source_Bits = 0x6,
469 Gi_Index_Mode_Bit = 0x10,
470 Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
471 Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
472 Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
473 Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
474 Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
475 Gi_HW_Arm_Enable_Bit = 0x80,
476 Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
477 Gi_660x_Prescale_X8_Bit = 0x1000,
478 Gi_M_Series_Prescale_X8_Bit = 0x2000,
479 Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
480
481 Gi_660x_Alternate_Sync_Bit = 0x2000,
482 Gi_M_Series_Alternate_Sync_Bit = 0x4000,
483 Gi_660x_Prescale_X2_Bit = 0x4000,
484 Gi_M_Series_Prescale_X2_Bit = 0x8000,
485};
486
487#define Gi_Source_Select_Shift 2
488#define Gi_Gate_Select_Shift 7
489enum Gi_Input_Select_Bits {
490 Gi_Read_Acknowledges_Irq = 0x1,
491 Gi_Write_Acknowledges_Irq = 0x2,
492 Gi_Source_Select_Mask = 0x7c,
493 Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
494 Gi_Gate_Select_Load_Source_Bit = 0x1000,
495 Gi_Or_Gate_Bit = 0x2000,
496 Gi_Output_Polarity_Bit = 0x4000,
497 Gi_Source_Polarity_Bit = 0x8000
498};
499
500enum Gi_Mode_Bits {
501 Gi_Gating_Mode_Mask = 0x3,
502 Gi_Gating_Disabled_Bits = 0x0,
503 Gi_Level_Gating_Bits = 0x1,
504 Gi_Rising_Edge_Gating_Bits = 0x2,
505 Gi_Falling_Edge_Gating_Bits = 0x3,
506 Gi_Gate_On_Both_Edges_Bit = 0x4,
507 Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
508 Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
509 Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
510 Gi_Edge_Gate_Starts_Bits = 0x10,
511 Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
512 Gi_Stop_Mode_Mask = 0x60,
513 Gi_Stop_on_Gate_Bits = 0x00,
514 Gi_Stop_on_Gate_or_TC_Bits = 0x20,
515 Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
516 Gi_Load_Source_Select_Bit = 0x80,
517 Gi_Output_Mode_Mask = 0x300,
518 Gi_Output_TC_Pulse_Bits = 0x100,
519 Gi_Output_TC_Toggle_Bits = 0x200,
520 Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
521 Gi_Counting_Once_Mask = 0xc00,
522 Gi_No_Hardware_Disarm_Bits = 0x000,
523 Gi_Disarm_at_TC_Bits = 0x400,
524 Gi_Disarm_at_Gate_Bits = 0x800,
525 Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
526 Gi_Loading_On_TC_Bit = 0x1000,
527 Gi_Gate_Polarity_Bit = 0x2000,
528 Gi_Loading_On_Gate_Bit = 0x4000,
529 Gi_Reload_Source_Switching_Bit = 0x8000
530};
531
532#define Gi_Second_Gate_Select_Shift 7
533
534
535enum Gi_Second_Gate_Bits {
536 Gi_Second_Gate_Mode_Bit = 0x1,
537 Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
538 Gi_Second_Gate_Polarity_Bit = 0x2000,
539 Gi_Second_Gate_Subselect_Bit = 0x4000,
540 Gi_Source_Subselect_Bit = 0x8000
541};
542static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
543{
544 return (second_gate_select << Gi_Second_Gate_Select_Shift) &
545 Gi_Second_Gate_Select_Mask;
546}
547
548enum Gxx_Status_Bits {
549 G0_Save_Bit = 0x1,
550 G1_Save_Bit = 0x2,
551 G0_Counting_Bit = 0x4,
552 G1_Counting_Bit = 0x8,
553 G0_Next_Load_Source_Bit = 0x10,
554 G1_Next_Load_Source_Bit = 0x20,
555 G0_Stale_Data_Bit = 0x40,
556 G1_Stale_Data_Bit = 0x80,
557 G0_Armed_Bit = 0x100,
558 G1_Armed_Bit = 0x200,
559 G0_No_Load_Between_Gates_Bit = 0x400,
560 G1_No_Load_Between_Gates_Bit = 0x800,
561 G0_TC_Error_Bit = 0x1000,
562 G1_TC_Error_Bit = 0x2000,
563 G0_Gate_Error_Bit = 0x4000,
564 G1_Gate_Error_Bit = 0x8000
565};
566static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
567{
568 if (counter_index % 2)
569 return G1_Counting_Bit;
570 return G0_Counting_Bit;
571}
572
573static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
574{
575 if (counter_index % 2)
576 return G1_Armed_Bit;
577 return G0_Armed_Bit;
578}
579
580static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
581 counter_index)
582{
583 if (counter_index % 2)
584 return G1_Next_Load_Source_Bit;
585 return G0_Next_Load_Source_Bit;
586}
587
588static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
589{
590 if (counter_index % 2)
591 return G1_Stale_Data_Bit;
592 return G0_Stale_Data_Bit;
593}
594
595static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
596{
597 if (counter_index % 2)
598 return G1_TC_Error_Bit;
599 return G0_TC_Error_Bit;
600}
601
602static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
603{
604 if (counter_index % 2)
605 return G1_Gate_Error_Bit;
606 return G0_Gate_Error_Bit;
607}
608
609
610static inline unsigned Gi_Reset_Bit(unsigned counter_index)
611{
612 return 0x1 << (2 + (counter_index % 2));
613}
614
615enum Gxx_Joint_Status2_Bits {
616 G0_Output_Bit = 0x1,
617 G1_Output_Bit = 0x2,
618 G0_HW_Save_Bit = 0x1000,
619 G1_HW_Save_Bit = 0x2000,
620 G0_Permanent_Stale_Bit = 0x4000,
621 G1_Permanent_Stale_Bit = 0x8000
622};
623static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
624 counter_index)
625{
626 if (counter_index % 2)
627 return G1_Permanent_Stale_Bit;
628 return G0_Permanent_Stale_Bit;
629}
630
631enum Gi_DMA_Config_Reg_Bits {
632 Gi_DMA_Enable_Bit = 0x1,
633 Gi_DMA_Write_Bit = 0x2,
634 Gi_DMA_Int_Bit = 0x4
635};
636
637enum Gi_DMA_Status_Reg_Bits {
638 Gi_DMA_Readbank_Bit = 0x2000,
639 Gi_DRQ_Error_Bit = 0x4000,
640 Gi_DRQ_Status_Bit = 0x8000
641};
642
643enum G02_Interrupt_Acknowledge_Bits {
644 G0_Gate_Error_Confirm_Bit = 0x20,
645 G0_TC_Error_Confirm_Bit = 0x40
646};
647enum G13_Interrupt_Acknowledge_Bits {
648 G1_Gate_Error_Confirm_Bit = 0x2,
649 G1_TC_Error_Confirm_Bit = 0x4
650};
651static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
652{
653 if (counter_index % 2)
654 return G1_Gate_Error_Confirm_Bit;
655 return G0_Gate_Error_Confirm_Bit;
656}
657
658static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
659{
660 if (counter_index % 2)
661 return G1_TC_Error_Confirm_Bit;
662 return G0_TC_Error_Confirm_Bit;
663}
664
665
666enum Gxx_Interrupt_Acknowledge_Bits {
667 Gi_TC_Interrupt_Ack_Bit = 0x4000,
668 Gi_Gate_Interrupt_Ack_Bit = 0x8000
669};
670
671enum Gi_Status_Bits {
672 Gi_Gate_Interrupt_Bit = 0x4,
673 Gi_TC_Bit = 0x8,
674 Gi_Interrupt_Bit = 0x8000
675};
676
677enum G02_Interrupt_Enable_Bits {
678 G0_TC_Interrupt_Enable_Bit = 0x40,
679 G0_Gate_Interrupt_Enable_Bit = 0x100
680};
681enum G13_Interrupt_Enable_Bits {
682 G1_TC_Interrupt_Enable_Bit = 0x200,
683 G1_Gate_Interrupt_Enable_Bit = 0x400
684};
685static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
686{
687 unsigned bit;
688
689 if (counter_index % 2) {
690 bit = G1_Gate_Interrupt_Enable_Bit;
691 } else {
692 bit = G0_Gate_Interrupt_Enable_Bit;
693 }
694 return bit;
695}
696
697static inline void write_register(struct ni_gpct *counter, unsigned bits,
698 enum ni_gpct_register reg)
699{
700 BUG_ON(reg >= NITIO_Num_Registers);
701 counter->counter_dev->write_register(counter, bits, reg);
702}
703
704static inline unsigned read_register(struct ni_gpct *counter,
705 enum ni_gpct_register reg)
706{
707 BUG_ON(reg >= NITIO_Num_Registers);
708 return counter->counter_dev->read_register(counter, reg);
709}
710
711static inline int ni_tio_counting_mode_registers_present(const struct
712 ni_gpct_device
713 *counter_dev)
714{
715 switch (counter_dev->variant) {
716 case ni_gpct_variant_e_series:
717 return 0;
718 break;
719 case ni_gpct_variant_m_series:
720 case ni_gpct_variant_660x:
721 return 1;
722 break;
723 default:
724 BUG();
725 break;
726 }
727 return 0;
728}
729
730static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
731 enum ni_gpct_register
732 register_index, unsigned bit_mask,
733 unsigned bit_values,
734 unsigned transient_bit_values)
735{
736 struct ni_gpct_device *counter_dev = counter->counter_dev;
737 unsigned long flags;
738
739 BUG_ON(register_index >= NITIO_Num_Registers);
740 spin_lock_irqsave(&counter_dev->regs_lock, flags);
741 counter_dev->regs[register_index] &= ~bit_mask;
742 counter_dev->regs[register_index] |= (bit_values & bit_mask);
743 write_register(counter,
744 counter_dev->regs[register_index] | transient_bit_values,
745 register_index);
746 mmiowb();
747 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
748}
749
750
751
752
753static inline void ni_tio_set_bits(struct ni_gpct *counter,
754 enum ni_gpct_register register_index,
755 unsigned bit_mask, unsigned bit_values)
756{
757 ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
758 0x0);
759}
760
761
762
763
764
765static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
766 enum ni_gpct_register
767 register_index)
768{
769 struct ni_gpct_device *counter_dev = counter->counter_dev;
770 unsigned long flags;
771 unsigned value;
772
773 BUG_ON(register_index >= NITIO_Num_Registers);
774 spin_lock_irqsave(&counter_dev->regs_lock, flags);
775 value = counter_dev->regs[register_index];
776 spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
777 return value;
778}
779
780int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
781int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
782 unsigned int gate_source);
783
784#endif
785
