LXR linux/drivers/staging/et131x/et1310_address

   1/*
   2 * Agere Systems Inc.
   3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
   4 *
   5 * Copyright © 2005 Agere Systems Inc.
   6 * All rights reserved.
   7 *   http://www.agere.com
   8 *
   9 *------------------------------------------------------------------------------
  10 *
  11 * et1310_address_map.h - Contains the register mapping for the ET1310
  12 *
  13 *------------------------------------------------------------------------------
  14 *
  15 * SOFTWARE LICENSE
  16 *
  17 * This software is provided subject to the following terms and conditions,
  18 * which you should read carefully before using the software.  Using this
  19 * software indicates your acceptance of these terms and conditions.  If you do
  20 * not agree with these terms and conditions, do not use the software.
  21 *
  22 * Copyright © 2005 Agere Systems Inc.
  23 * All rights reserved.
  24 *
  25 * Redistribution and use in source or binary forms, with or without
  26 * modifications, are permitted provided that the following conditions are met:
  27 *
  28 * . Redistributions of source code must retain the above copyright notice, this
  29 *    list of conditions and the following Disclaimer as comments in the code as
  30 *    well as in the documentation and/or other materials provided with the
  31 *    distribution.
  32 *
  33 * . Redistributions in binary form must reproduce the above copyright notice,
  34 *    this list of conditions and the following Disclaimer in the documentation
  35 *    and/or other materials provided with the distribution.
  36 *
  37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
  38 *    may be used to endorse or promote products derived from this software
  39 *    without specific prior written permission.
  40 *
  41 * Disclaimer
  42 *
  43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
  44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
  45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  ANY
  46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
  47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
  48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
  52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  54 * DAMAGE.
  55 *
  56 */
  57
  58#ifndef _ET1310_ADDRESS_MAP_H_
  59#define _ET1310_ADDRESS_MAP_H_
  60
  61
  62/* START OF GLOBAL REGISTER ADDRESS MAP */
  63
  64/*
  65 * 10bit registers
  66 *
  67 * Tx queue start address reg in global address map at address 0x0000
  68 * tx queue end address reg in global address map at address 0x0004
  69 * rx queue start address reg in global address map at address 0x0008
  70 * rx queue end address reg in global address map at address 0x000C
  71 */
  72
  73/*
  74 * structure for power management control status reg in global address map
  75 * located at address 0x0010
  76 *      jagcore_rx_rdy  bit 9
  77 *      jagcore_tx_rdy  bit 8
  78 *      phy_lped_en     bit 7
  79 *      phy_sw_coma     bit 6
  80 *      rxclk_gate      bit 5
  81 *      txclk_gate      bit 4
  82 *      sysclk_gate     bit 3
  83 *      jagcore_rx_en   bit 2
  84 *      jagcore_tx_en   bit 1
  85 *      gigephy_en      bit 0
  86 */
  87
  88#define ET_PM_PHY_SW_COMA               0x40
  89#define ET_PMCSR_INIT                   0x38
  90
  91/*
  92 * Interrupt status reg at address 0x0018
  93 */
  94
  95#define ET_INTR_TXDMA_ISR       0x00000008
  96#define ET_INTR_TXDMA_ERR       0x00000010
  97#define ET_INTR_RXDMA_XFR_DONE  0x00000020
  98#define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
  99#define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
 100#define ET_INTR_RXDMA_STAT_LOW  0x00000100
 101#define ET_INTR_RXDMA_ERR       0x00000200
 102#define ET_INTR_WATCHDOG        0x00004000
 103#define ET_INTR_WOL             0x00008000
 104#define ET_INTR_PHY             0x00010000
 105#define ET_INTR_TXMAC           0x00020000
 106#define ET_INTR_RXMAC           0x00040000
 107#define ET_INTR_MAC_STAT        0x00080000
 108#define ET_INTR_SLV_TIMEOUT     0x00100000
 109
 110/*
 111 * Interrupt mask register at address 0x001C
 112 * Interrupt alias clear mask reg at address 0x0020
 113 * Interrupt status alias reg at address 0x0024
 114 *
 115 * Same masks as above
 116 */
 117
 118/*
 119 * Software reset reg at address 0x0028
 120 * 0:   txdma_sw_reset
 121 * 1:   rxdma_sw_reset
 122 * 2:   txmac_sw_reset
 123 * 3:   rxmac_sw_reset
 124 * 4:   mac_sw_reset
 125 * 5:   mac_stat_sw_reset
 126 * 6:   mmc_sw_reset
 127 *31:   selfclr_disable
 128 */
 129
 130/*
 131 * SLV Timer reg at address 0x002C (low 24 bits)
 132 */
 133
 134/*
 135 * MSI Configuration reg at address 0x0030
 136 */
 137
 138#define ET_MSI_VECTOR   0x0000001F
 139#define ET_MSI_TC       0x00070000
 140
 141/*
 142 * Loopback reg located at address 0x0034
 143 */
 144
 145#define ET_LOOP_MAC     0x00000001
 146#define ET_LOOP_DMA     0x00000002
 147
 148/*
 149 * GLOBAL Module of JAGCore Address Mapping
 150 * Located at address 0x0000
 151 */
 152typedef struct _GLOBAL_t {                      /* Location: */
 153        u32 txq_start_addr;                     /*  0x0000 */
 154        u32 txq_end_addr;                       /*  0x0004 */
 155        u32 rxq_start_addr;                     /*  0x0008 */
 156        u32 rxq_end_addr;                       /*  0x000C */
 157        u32 pm_csr;                             /*  0x0010 */
 158        u32 unused;                             /*  0x0014 */
 159        u32 int_status;                         /*  0x0018 */
 160        u32 int_mask;                           /*  0x001C */
 161        u32 int_alias_clr_en;                   /*  0x0020 */
 162        u32 int_status_alias;                   /*  0x0024 */
 163        u32 sw_reset;                           /*  0x0028 */
 164        u32 slv_timer;                          /*  0x002C */
 165        u32 msi_config;                         /*  0x0030 */
 166        u32 loopback;                   /*  0x0034 */
 167        u32 watchdog_timer;                     /*  0x0038 */
 168} GLOBAL_t, *PGLOBAL_t;
 169
 170/* END OF GLOBAL REGISTER ADDRESS MAP */
 171
 172
 173/* START OF TXDMA REGISTER ADDRESS MAP */
 174
 175/*
 176 * txdma control status reg at address 0x1000
 177 */
 178
 179#define ET_TXDMA_CSR_HALT       0x00000001
 180#define ET_TXDMA_DROP_TLP       0x00000002
 181#define ET_TXDMA_CACHE_THRS     0x000000F0
 182#define ET_TXDMA_CACHE_SHIFT    4
 183#define ET_TXDMA_SNGL_EPKT      0x00000100
 184#define ET_TXDMA_CLASS          0x00001E00
 185
 186/*
 187 * structure for txdma packet ring base address hi reg in txdma address map
 188 * located at address 0x1004
 189 * Defined earlier (u32)
 190 */
 191
 192/*
 193 * structure for txdma packet ring base address low reg in txdma address map
 194 * located at address 0x1008
 195 * Defined earlier (u32)
 196 */
 197
 198/*
 199 * structure for txdma packet ring number of descriptor reg in txdma address
 200 * map.  Located at address 0x100C
 201 */
 202typedef union _TXDMA_PR_NUM_DES_t {
 203        u32 value;
 204        struct {
 205#ifdef _BIT_FIELDS_HTOL
 206                u32 unused:22;  /* bits 10-31 */
 207                u32 pr_ndes:10; /* bits 0-9 */
 208#else
 209                u32 pr_ndes:10; /* bits 0-9 */
 210                u32 unused:22;  /* bits 10-31 */
 211#endif
 212        } bits;
 213} TXDMA_PR_NUM_DES_t, *PTXDMA_PR_NUM_DES_t;
 214
 215
 216#define ET_DMA10_MASK           0x3FF   /* 10 bit mask for DMA10W types */
 217#define ET_DMA10_WRAP           0x400
 218#define ET_DMA4_MASK            0x00F   /* 4 bit mask for DMA4W types */
 219#define ET_DMA4_WRAP            0x010
 220
 221#define INDEX10(x)      ((x) & ET_DMA10_MASK)
 222#define INDEX4(x)       ((x) & ET_DMA4_MASK)
 223
 224extern inline void add_10bit(u32 *v, int n)
 225{
 226        *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
 227}
 228
 229/*
 230 * 10bit DMA with wrap
 231 * txdma tx queue write address reg in txdma address map at 0x1010
 232 * txdma tx queue write address external reg in txdma address map at 0x1014
 233 * txdma tx queue read address reg in txdma address map at 0x1018
 234 *
 235 * u32
 236 * txdma status writeback address hi reg in txdma address map at0x101C
 237 * txdma status writeback address lo reg in txdma address map at 0x1020
 238 *
 239 * 10bit DMA with wrap
 240 * txdma service request reg in txdma address map at 0x1024
 241 * structure for txdma service complete reg in txdma address map at 0x1028
 242 *
 243 * 4bit DMA with wrap
 244 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
 245 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
 246 *
 247 * txdma error reg in txdma address map at address 0x1034
 248 * 0: PyldResend
 249 * 1: PyldRewind
 250 * 4: DescrResend
 251 * 5: DescrRewind
 252 * 8: WrbkResend
 253 * 9: WrbkRewind
 254 */
 255
 256/*
 257 * Tx DMA Module of JAGCore Address Mapping
 258 * Located at address 0x1000
 259 */
 260typedef struct _TXDMA_t {               /* Location: */
 261        u32 csr;                        /*  0x1000 */
 262        u32 pr_base_hi;                 /*  0x1004 */
 263        u32 pr_base_lo;                 /*  0x1008 */
 264        TXDMA_PR_NUM_DES_t pr_num_des;  /*  0x100C */
 265        u32 txq_wr_addr;                /*  0x1010 */
 266        u32 txq_wr_addr_ext;            /*  0x1014 */
 267        u32 txq_rd_addr;                /*  0x1018 */
 268        u32 dma_wb_base_hi;             /*  0x101C */
 269        u32 dma_wb_base_lo;             /*  0x1020 */
 270        u32 service_request;            /*  0x1024 */
 271        u32 service_complete;           /*  0x1028 */
 272        u32 cache_rd_index;             /*  0x102C */
 273        u32 cache_wr_index;             /*  0x1030 */
 274        u32 TxDmaError;                 /*  0x1034 */
 275        u32 DescAbortCount;             /*  0x1038 */
 276        u32 PayloadAbortCnt;            /*  0x103c */
 277        u32 WriteBackAbortCnt;          /*  0x1040 */
 278        u32 DescTimeoutCnt;             /*  0x1044 */
 279        u32 PayloadTimeoutCnt;          /*  0x1048 */
 280        u32 WriteBackTimeoutCnt;        /*  0x104c */
 281        u32 DescErrorCount;             /*  0x1050 */
 282        u32 PayloadErrorCnt;            /*  0x1054 */
 283        u32 WriteBackErrorCnt;          /*  0x1058 */
 284        u32 DroppedTLPCount;            /*  0x105c */
 285        u32 NewServiceComplete;         /*  0x1060 */
 286        u32 EthernetPacketCount;        /*  0x1064 */
 287} TXDMA_t, *PTXDMA_t;
 288
 289/* END OF TXDMA REGISTER ADDRESS MAP */
 290
 291
 292/* START OF RXDMA REGISTER ADDRESS MAP */
 293
 294/*
 295 * structure for control status reg in rxdma address map
 296 * Located at address 0x2000
 297 */
 298typedef union _RXDMA_CSR_t {
 299        u32 value;
 300        struct {
 301#ifdef _BIT_FIELDS_HTOL
 302                u32 unused2:14;         /* bits 18-31 */
 303                u32 halt_status:1;      /* bit 17 */
 304                u32 pkt_done_flush:1;   /* bit 16 */
 305                u32 pkt_drop_disable:1; /* bit 15 */
 306                u32 unused1:1;          /* bit 14 */
 307                u32 fbr1_enable:1;      /* bit 13 */
 308                u32 fbr1_size:2;        /* bits 11-12 */
 309                u32 fbr0_enable:1;      /* bit 10 */
 310                u32 fbr0_size:2;        /* bits 8-9 */
 311                u32 dma_big_endian:1;   /* bit 7 */
 312                u32 pkt_big_endian:1;   /* bit 6 */
 313                u32 psr_big_endian:1;   /* bit 5 */
 314                u32 fbr_big_endian:1;   /* bit 4 */
 315                u32 tc:3;               /* bits 1-3 */
 316                u32 halt:1;             /* bit 0 */
 317#else
 318                u32 halt:1;             /* bit 0 */
 319                u32 tc:3;               /* bits 1-3 */
 320                u32 fbr_big_endian:1;   /* bit 4 */
 321                u32 psr_big_endian:1;   /* bit 5 */
 322                u32 pkt_big_endian:1;   /* bit 6 */
 323                u32 dma_big_endian:1;   /* bit 7 */
 324                u32 fbr0_size:2;        /* bits 8-9 */
 325                u32 fbr0_enable:1;      /* bit 10 */
 326                u32 fbr1_size:2;        /* bits 11-12 */
 327                u32 fbr1_enable:1;      /* bit 13 */
 328                u32 unused1:1;          /* bit 14 */
 329                u32 pkt_drop_disable:1; /* bit 15 */
 330                u32 pkt_done_flush:1;   /* bit 16 */
 331                u32 halt_status:1;      /* bit 17 */
 332                u32 unused2:14;         /* bits 18-31 */
 333#endif
 334        } bits;
 335} RXDMA_CSR_t, *PRXDMA_CSR_t;
 336
 337/*
 338 * structure for dma writeback lo reg in rxdma address map
 339 * located at address 0x2004
 340 * Defined earlier (u32)
 341 */
 342
 343/*
 344 * structure for dma writeback hi reg in rxdma address map
 345 * located at address 0x2008
 346 * Defined earlier (u32)
 347 */
 348
 349/*
 350 * structure for number of packets done reg in rxdma address map
 351 * located at address 0x200C
 352 */
 353typedef union _RXDMA_NUM_PKT_DONE_t {
 354        u32 value;
 355        struct {
 356#ifdef _BIT_FIELDS_HTOL
 357                u32 unused:24;  /* bits 8-31 */
 358                u32 num_done:8; /* bits 0-7 */
 359#else
 360                u32 num_done:8; /* bits 0-7 */
 361                u32 unused:24;  /* bits 8-31 */
 362#endif
 363        } bits;
 364} RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
 365
 366/*
 367 * structure for max packet time reg in rxdma address map
 368 * located at address 0x2010
 369 */
 370typedef union _RXDMA_MAX_PKT_TIME_t {
 371        u32 value;
 372        struct {
 373#ifdef _BIT_FIELDS_HTOL
 374                u32 unused:14;          /* bits 18-31 */
 375                u32 time_done:18;       /* bits 0-17 */
 376#else
 377                u32 time_done:18;       /* bits 0-17 */
 378                u32 unused:14;          /* bits 18-31 */
 379#endif
 380        } bits;
 381} RXDMA_MAX_PKT_TIME_t, *PRXDMA_MAX_PKT_TIME_t;
 382
 383/*
 384 * structure for rx queue read address reg in rxdma address map
 385 * located at address 0x2014
 386 * Defined earlier (u32)
 387 */
 388
 389/*
 390 * structure for rx queue read address external reg in rxdma address map
 391 * located at address 0x2018
 392 * Defined earlier (u32)
 393 */
 394
 395/*
 396 * structure for rx queue write address reg in rxdma address map
 397 * located at address 0x201C
 398 * Defined earlier (u32)
 399 */
 400
 401/*
 402 * structure for packet status ring base address lo reg in rxdma address map
 403 * located at address 0x2020
 404 * Defined earlier (u32)
 405 */
 406
 407/*
 408 * structure for packet status ring base address hi reg in rxdma address map
 409 * located at address 0x2024
 410 * Defined earlier (u32)
 411 */
 412
 413/*
 414 * structure for packet status ring number of descriptors reg in rxdma address
 415 * map.  Located at address 0x2028
 416 */
 417typedef union _RXDMA_PSR_NUM_DES_t {
 418        u32 value;
 419        struct {
 420#ifdef _BIT_FIELDS_HTOL
 421                u32 unused:20;          /* bits 12-31 */
 422                u32 psr_ndes:12;        /* bit 0-11 */
 423#else
 424                u32 psr_ndes:12;        /* bit 0-11 */
 425                u32 unused:20;          /* bits 12-31 */
 426#endif
 427        } bits;
 428} RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
 429
 430/*
 431 * structure for packet status ring available offset reg in rxdma address map
 432 * located at address 0x202C
 433 */
 434typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
 435        u32 value;
 436        struct {
 437#ifdef _BIT_FIELDS_HTOL
 438                u32 unused:19;          /* bits 13-31 */
 439                u32 psr_avail_wrap:1;   /* bit 12 */
 440                u32 psr_avail:12;       /* bit 0-11 */
 441#else
 442                u32 psr_avail:12;       /* bit 0-11 */
 443                u32 psr_avail_wrap:1;   /* bit 12 */
 444                u32 unused:19;          /* bits 13-31 */
 445#endif
 446        } bits;
 447} RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
 448
 449/*
 450 * structure for packet status ring full offset reg in rxdma address map
 451 * located at address 0x2030
 452 */
 453typedef union _RXDMA_PSR_FULL_OFFSET_t {
 454        u32 value;
 455        struct {
 456#ifdef _BIT_FIELDS_HTOL
 457                u32 unused:19;          /* bits 13-31 */
 458                u32 psr_full_wrap:1;    /* bit 12 */
 459                u32 psr_full:12;        /* bit 0-11 */
 460#else
 461                u32 psr_full:12;        /* bit 0-11 */
 462                u32 psr_full_wrap:1;    /* bit 12 */
 463                u32 unused:19;          /* bits 13-31 */
 464#endif
 465        } bits;
 466} RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
 467
 468/*
 469 * structure for packet status ring access index reg in rxdma address map
 470 * located at address 0x2034
 471 */
 472typedef union _RXDMA_PSR_ACCESS_INDEX_t {
 473        u32 value;
 474        struct {
 475#ifdef _BIT_FIELDS_HTOL
 476                u32 unused:27;  /* bits 5-31 */
 477                u32 psr_ai:5;   /* bits 0-4 */
 478#else
 479                u32 psr_ai:5;   /* bits 0-4 */
 480                u32 unused:27;  /* bits 5-31 */
 481#endif
 482        } bits;
 483} RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
 484
 485/*
 486 * structure for packet status ring minimum descriptors reg in rxdma address
 487 * map.  Located at address 0x2038
 488 */
 489typedef union _RXDMA_PSR_MIN_DES_t {
 490        u32 value;
 491        struct {
 492#ifdef _BIT_FIELDS_HTOL
 493                u32 unused:20;  /* bits 12-31 */
 494                u32 psr_min:12; /* bits 0-11 */
 495#else
 496                u32 psr_min:12; /* bits 0-11 */
 497                u32 unused:20;  /* bits 12-31 */
 498#endif
 499        } bits;
 500} RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
 501
 502/*
 503 * structure for free buffer ring base lo address reg in rxdma address map
 504 * located at address 0x203C
 505 * Defined earlier (u32)
 506 */
 507
 508/*
 509 * structure for free buffer ring base hi address reg in rxdma address map
 510 * located at address 0x2040
 511 * Defined earlier (u32)
 512 */
 513
 514/*
 515 * structure for free buffer ring number of descriptors reg in rxdma address
 516 * map.  Located at address 0x2044
 517 */
 518typedef union _RXDMA_FBR_NUM_DES_t {
 519        u32 value;
 520        struct {
 521#ifdef _BIT_FIELDS_HTOL
 522                u32 unused:22;          /* bits 10-31 */
 523                u32 fbr_ndesc:10;       /* bits 0-9 */
 524#else
 525                u32 fbr_ndesc:10;       /* bits 0-9 */
 526                u32 unused:22;          /* bits 10-31 */
 527#endif
 528        } bits;
 529} RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
 530
 531/*
 532 * structure for free buffer ring 0 available offset reg in rxdma address map
 533 * located at address 0x2048
 534 * Defined earlier (u32)
 535 */
 536
 537/*
 538 * structure for free buffer ring 0 full offset reg in rxdma address map
 539 * located at address 0x204C
 540 * Defined earlier (u32)
 541 */
 542
 543/*
 544 * structure for free buffer cache 0 full offset reg in rxdma address map
 545 * located at address 0x2050
 546 */
 547typedef union _RXDMA_FBC_RD_INDEX_t {
 548        u32 value;
 549        struct {
 550#ifdef _BIT_FIELDS_HTOL
 551                u32 unused:27;  /* bits 5-31 */
 552                u32 fbc_rdi:5;  /* bit 0-4 */
 553#else
 554                u32 fbc_rdi:5;  /* bit 0-4 */
 555                u32 unused:27;  /* bits 5-31 */
 556#endif
 557        } bits;
 558} RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
 559
 560/*
 561 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
 562 * located at address 0x2054
 563 */
 564typedef union _RXDMA_FBR_MIN_DES_t {
 565        u32 value;
 566        struct {
 567#ifdef _BIT_FIELDS_HTOL
 568                u32 unused:22;  /* bits 10-31 */
 569                u32 fbr_min:10; /* bits 0-9 */
 570#else
 571                u32 fbr_min:10; /* bits 0-9 */
 572                u32 unused:22;  /* bits 10-31 */
 573#endif
 574        } bits;
 575} RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
 576
 577/*
 578 * structure for free buffer ring 1 base address lo reg in rxdma address map
 579 * located at address 0x2058 - 0x205C
 580 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
 581 */
 582
 583/*
 584 * structure for free buffer ring 1 number of descriptors reg in rxdma address
 585 * map.  Located at address 0x2060
 586 * Defined earlier (RXDMA_FBR_NUM_DES_t)
 587 */
 588
 589/*
 590 * structure for free buffer ring 1 available offset reg in rxdma address map
 591 * located at address 0x2064
 592 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
 593 */
 594
 595/*
 596 * structure for free buffer ring 1 full offset reg in rxdma address map
 597 * located at address 0x2068
 598 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
 599 */
 600
 601/*
 602 * structure for free buffer cache 1 read index reg in rxdma address map
 603 * located at address 0x206C
 604 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
 605 */
 606
 607/*
 608 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
 609 * located at address 0x2070
 610 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
 611 */
 612
 613/*
 614 * Rx DMA Module of JAGCore Address Mapping
 615 * Located at address 0x2000
 616 */
 617typedef struct _RXDMA_t {                               /* Location: */
 618        RXDMA_CSR_t csr;                                /*  0x2000 */
 619        u32 dma_wb_base_lo;                             /*  0x2004 */
 620        u32 dma_wb_base_hi;                             /*  0x2008 */
 621        RXDMA_NUM_PKT_DONE_t num_pkt_done;              /*  0x200C */
 622        RXDMA_MAX_PKT_TIME_t max_pkt_time;              /*  0x2010 */
 623        u32 rxq_rd_addr;                                /*  0x2014 */
 624        u32 rxq_rd_addr_ext;                    /*  0x2018 */
 625        u32 rxq_wr_addr;                                /*  0x201C */
 626        u32 psr_base_lo;                                /*  0x2020 */
 627        u32 psr_base_hi;                                /*  0x2024 */
 628        RXDMA_PSR_NUM_DES_t psr_num_des;                /*  0x2028 */
 629        RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset;      /*  0x202C */
 630        RXDMA_PSR_FULL_OFFSET_t psr_full_offset;        /*  0x2030 */
 631        RXDMA_PSR_ACCESS_INDEX_t psr_access_index;      /*  0x2034 */
 632        RXDMA_PSR_MIN_DES_t psr_min_des;                /*  0x2038 */
 633        u32 fbr0_base_lo;                               /*  0x203C */
 634        u32 fbr0_base_hi;                               /*  0x2040 */
 635        RXDMA_FBR_NUM_DES_t fbr0_num_des;               /*  0x2044 */
 636        u32 fbr0_avail_offset;                  /*  0x2048 */
 637        u32 fbr0_full_offset;                   /*  0x204C */
 638        RXDMA_FBC_RD_INDEX_t fbr0_rd_index;             /*  0x2050 */
 639        RXDMA_FBR_MIN_DES_t fbr0_min_des;               /*  0x2054 */
 640        u32 fbr1_base_lo;                               /*  0x2058 */
 641        u32 fbr1_base_hi;                               /*  0x205C */
 642        RXDMA_FBR_NUM_DES_t fbr1_num_des;               /*  0x2060 */
 643        u32 fbr1_avail_offset;                  /*  0x2064 */
 644        u32 fbr1_full_offset;                   /*  0x2068 */
 645        RXDMA_FBC_RD_INDEX_t fbr1_rd_index;             /*  0x206C */
 646        RXDMA_FBR_MIN_DES_t fbr1_min_des;               /*  0x2070 */
 647} RXDMA_t, *PRXDMA_t;
 648
 649/* END OF RXDMA REGISTER ADDRESS MAP */
 650
 651
 652/* START OF TXMAC REGISTER ADDRESS MAP */
 653
 654/*
 655 * structure for control reg in txmac address map
 656 * located at address 0x3000
 657 */
 658typedef union _TXMAC_CTL_t {
 659        u32 value;
 660        struct {
 661#ifdef _BIT_FIELDS_HTOL
 662                u32 unused:24;          /* bits 8-31 */
 663                u32 cklseg_diable:1;    /* bit 7 */
 664                u32 ckbcnt_disable:1;   /* bit 6 */
 665                u32 cksegnum:1;         /* bit 5 */
 666                u32 async_disable:1;    /* bit 4 */
 667                u32 fc_disable:1;       /* bit 3 */
 668                u32 mcif_disable:1;     /* bit 2 */
 669                u32 mif_disable:1;      /* bit 1 */
 670                u32 txmac_en:1;         /* bit 0 */
 671#else
 672                u32 txmac_en:1;         /* bit 0 */
 673                u32 mif_disable:1;      /* bit 1 mac interface */
 674                u32 mcif_disable:1;     /* bit 2 mem. contr. interface */
 675                u32 fc_disable:1;       /* bit 3 */
 676                u32 async_disable:1;    /* bit 4 */
 677                u32 cksegnum:1;         /* bit 5 */
 678                u32 ckbcnt_disable:1;   /* bit 6 */
 679                u32 cklseg_diable:1;    /* bit 7 */
 680                u32 unused:24;          /* bits 8-31 */
 681#endif
 682        } bits;
 683} TXMAC_CTL_t, *PTXMAC_CTL_t;
 684
 685/*
 686 * structure for shadow pointer reg in txmac address map
 687 * located at address 0x3004
 688 */
 689typedef union _TXMAC_SHADOW_PTR_t {
 690        u32 value;
 691        struct {
 692#ifdef _BIT_FIELDS_HTOL
 693                u32 reserved2:5;        /* bits 27-31 */
 694                u32 txq_rd_ptr:11;      /* bits 16-26 */
 695                u32 reserved:5;         /* bits 11-15 */
 696                u32 txq_wr_ptr:11;      /* bits 0-10 */
 697#else
 698                u32 txq_wr_ptr:11;      /* bits 0-10 */
 699                u32 reserved:5;         /* bits 11-15 */
 700                u32 txq_rd_ptr:11;      /* bits 16-26 */
 701                u32 reserved2:5;        /* bits 27-31 */
 702#endif
 703        } bits;
 704} TXMAC_SHADOW_PTR_t, *PTXMAC_SHADOW_PTR_t;
 705
 706/*
 707 * structure for error count reg in txmac address map
 708 * located at address 0x3008
 709 */
 710typedef union _TXMAC_ERR_CNT_t {
 711        u32 value;
 712        struct {
 713#ifdef _BIT_FIELDS_HTOL
 714                u32 unused:20;          /* bits 12-31 */
 715                u32 reserved:4;         /* bits 8-11 */
 716                u32 txq_underrun:4;     /* bits 4-7 */
 717                u32 fifo_underrun:4;    /* bits 0-3 */
 718#else
 719                u32 fifo_underrun:4;    /* bits 0-3 */
 720                u32 txq_underrun:4;     /* bits 4-7 */
 721                u32 reserved:4;         /* bits 8-11 */
 722                u32 unused:20;          /* bits 12-31 */
 723#endif
 724        } bits;
 725} TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
 726
 727/*
 728 * structure for max fill reg in txmac address map
 729 * located at address 0x300C
 730 */
 731typedef union _TXMAC_MAX_FILL_t {
 732        u32 value;
 733        struct {
 734#ifdef _BIT_FIELDS_HTOL
 735                u32 unused:20;          /* bits 12-31 */
 736                u32 max_fill:12;        /* bits 0-11 */
 737#else
 738                u32 max_fill:12;        /* bits 0-11 */
 739                u32 unused:20;          /* bits 12-31 */
 740#endif
 741        } bits;
 742} TXMAC_MAX_FILL_t, *PTXMAC_MAX_FILL_t;
 743
 744/*
 745 * structure for cf parameter reg in txmac address map
 746 * located at address 0x3010
 747 */
 748typedef union _TXMAC_CF_PARAM_t {
 749        u32 value;
 750        struct {
 751#ifdef _BIT_FIELDS_HTOL
 752                u32 cfep:16;    /* bits 16-31 */
 753                u32 cfpt:16;    /* bits 0-15 */
 754#else
 755                u32 cfpt:16;    /* bits 0-15 */
 756                u32 cfep:16;    /* bits 16-31 */
 757#endif
 758        } bits;
 759} TXMAC_CF_PARAM_t, *PTXMAC_CF_PARAM_t;
 760
 761/*
 762 * structure for tx test reg in txmac address map
 763 * located at address 0x3014
 764 */
 765typedef union _TXMAC_TXTEST_t {
 766        u32 value;
 767        struct {
 768#ifdef _BIT_FIELDS_HTOL
 769                u32 unused2:15;         /* bits 17-31 */
 770                u32 reserved1:1;        /* bit 16 */
 771                u32 txtest_en:1;        /* bit 15 */
 772                u32 unused1:4;          /* bits 11-14 */
 773                u32 txqtest_ptr:11;     /* bits 0-11 */
 774#else
 775                u32 txqtest_ptr:11;     /* bits 0-10 */
 776                u32 unused1:4;          /* bits 11-14 */
 777                u32 txtest_en:1;        /* bit 15 */
 778                u32 reserved1:1;        /* bit 16 */
 779                u32 unused2:15;         /* bits 17-31 */
 780#endif
 781        } bits;
 782} TXMAC_TXTEST_t, *PTXMAC_TXTEST_t;
 783
 784/*
 785 * structure for error reg in txmac address map
 786 * located at address 0x3018
 787 */
 788typedef union _TXMAC_ERR_t {
 789        u32 value;
 790        struct {
 791#ifdef _BIT_FIELDS_HTOL
 792                u32 unused2:23;         /* bits 9-31 */
 793                u32 fifo_underrun:1;    /* bit 8 */
 794                u32 unused1:2;          /* bits 6-7 */
 795                u32 ctrl2_err:1;        /* bit 5 */
 796                u32 txq_underrun:1;     /* bit 4 */
 797                u32 bcnt_err:1;         /* bit 3 */
 798                u32 lseg_err:1;         /* bit 2 */
 799                u32 segnum_err:1;       /* bit 1 */
 800                u32 seg0_err:1;         /* bit 0 */
 801#else
 802                u32 seg0_err:1;         /* bit 0 */
 803                u32 segnum_err:1;       /* bit 1 */
 804                u32 lseg_err:1;         /* bit 2 */
 805                u32 bcnt_err:1;         /* bit 3 */
 806                u32 txq_underrun:1;     /* bit 4 */
 807                u32 ctrl2_err:1;        /* bit 5 */
 808                u32 unused1:2;          /* bits 6-7 */
 809                u32 fifo_underrun:1;    /* bit 8 */
 810                u32 unused2:23;         /* bits 9-31 */
 811#endif
 812        } bits;
 813} TXMAC_ERR_t, *PTXMAC_ERR_t;
 814
 815/*
 816 * structure for error interrupt reg in txmac address map
 817 * located at address 0x301C
 818 */
 819typedef union _TXMAC_ERR_INT_t {
 820        u32 value;
 821        struct {
 822#ifdef _BIT_FIELDS_HTOL
 823                u32 unused2:23;         /* bits 9-31 */
 824                u32 fifo_underrun:1;    /* bit 8 */
 825                u32 unused1:2;          /* bits 6-7 */
 826                u32 ctrl2_err:1;        /* bit 5 */
 827                u32 txq_underrun:1;     /* bit 4 */
 828                u32 bcnt_err:1;         /* bit 3 */
 829                u32 lseg_err:1;         /* bit 2 */
 830                u32 segnum_err:1;       /* bit 1 */
 831                u32 seg0_err:1;         /* bit 0 */
 832#else
 833                u32 seg0_err:1;         /* bit 0 */
 834                u32 segnum_err:1;       /* bit 1 */
 835                u32 lseg_err:1;         /* bit 2 */
 836                u32 bcnt_err:1;         /* bit 3 */
 837                u32 txq_underrun:1;     /* bit 4 */
 838                u32 ctrl2_err:1;        /* bit 5 */
 839                u32 unused1:2;          /* bits 6-7 */
 840                u32 fifo_underrun:1;    /* bit 8 */
 841                u32 unused2:23;         /* bits 9-31 */
 842#endif
 843        } bits;
 844} TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
 845
 846/*
 847 * structure for error interrupt reg in txmac address map
 848 * located at address 0x3020
 849 */
 850typedef union _TXMAC_CP_CTRL_t {
 851        u32 value;
 852        struct {
 853#ifdef _BIT_FIELDS_HTOL
 854                u32 unused:30;          /* bits 2-31 */
 855                u32 bp_req:1;           /* bit 1 */
 856                u32 bp_xonxoff:1;       /* bit 0 */
 857#else
 858                u32 bp_xonxoff:1;       /* bit 0 */
 859                u32 bp_req:1;           /* bit 1 */
 860                u32 unused:30;          /* bits 2-31 */
 861#endif
 862        } bits;
 863} TXMAC_BP_CTRL_t, *PTXMAC_BP_CTRL_t;
 864
 865/*
 866 * Tx MAC Module of JAGCore Address Mapping
 867 */
 868typedef struct _TXMAC_t {               /* Location: */
 869        TXMAC_CTL_t ctl;                /*  0x3000 */
 870        TXMAC_SHADOW_PTR_t shadow_ptr;  /*  0x3004 */
 871        TXMAC_ERR_CNT_t err_cnt;        /*  0x3008 */
 872        TXMAC_MAX_FILL_t max_fill;      /*  0x300C */
 873        TXMAC_CF_PARAM_t cf_param;      /*  0x3010 */
 874        TXMAC_TXTEST_t tx_test;         /*  0x3014 */
 875        TXMAC_ERR_t err;                /*  0x3018 */
 876        TXMAC_ERR_INT_t err_int;        /*  0x301C */
 877        TXMAC_BP_CTRL_t bp_ctrl;        /*  0x3020 */
 878} TXMAC_t, *PTXMAC_t;
 879
 880/* END OF TXMAC REGISTER ADDRESS MAP */
 881
 882/* START OF RXMAC REGISTER ADDRESS MAP */
 883
 884/*
 885 * structure for rxmac control reg in rxmac address map
 886 * located at address 0x4000
 887 */
 888typedef union _RXMAC_CTRL_t {
 889        u32 value;
 890        struct {
 891#ifdef _BIT_FIELDS_HTOL
 892                u32 reserved:25;                /* bits 7-31 */
 893                u32 rxmac_int_disable:1;        /* bit 6 */
 894                u32 async_disable:1;            /* bit 5 */
 895                u32 mif_disable:1;              /* bit 4 */
 896                u32 wol_disable:1;              /* bit 3 */
 897                u32 pkt_filter_disable:1;       /* bit 2 */
 898                u32 mcif_disable:1;             /* bit 1 */
 899                u32 rxmac_en:1;                 /* bit 0 */
 900#else
 901                u32 rxmac_en:1;                 /* bit 0 */
 902                u32 mcif_disable:1;             /* bit 1 */
 903                u32 pkt_filter_disable:1;       /* bit 2 */
 904                u32 wol_disable:1;              /* bit 3 */
 905                u32 mif_disable:1;              /* bit 4 */
 906                u32 async_disable:1;            /* bit 5 */
 907                u32 rxmac_int_disable:1;        /* bit 6 */
 908                u32 reserved:25;                /* bits 7-31 */
 909#endif
 910        } bits;
 911} RXMAC_CTRL_t, *PRXMAC_CTRL_t;
 912
 913/*
 914 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
 915 * located at address 0x4004
 916 */
 917typedef union _RXMAC_WOL_CTL_CRC0_t {
 918        u32 value;
 919        struct {
 920#ifdef _BIT_FIELDS_HTOL
 921                u32 crc0:16;            /* bits 16-31 */
 922                u32 reserve:4;          /* bits 12-15 */
 923                u32 ignore_pp:1;        /* bit 11 */
 924                u32 ignore_mp:1;        /* bit 10 */
 925                u32 clr_intr:1;         /* bit 9 */
 926                u32 ignore_link_chg:1;  /* bit 8 */
 927                u32 ignore_uni:1;       /* bit 7 */
 928                u32 ignore_multi:1;     /* bit 6 */
 929                u32 ignore_broad:1;     /* bit 5 */
 930                u32 valid_crc4:1;       /* bit 4 */
 931                u32 valid_crc3:1;       /* bit 3 */
 932                u32 valid_crc2:1;       /* bit 2 */
 933                u32 valid_crc1:1;       /* bit 1 */
 934                u32 valid_crc0:1;       /* bit 0 */
 935#else
 936                u32 valid_crc0:1;       /* bit 0 */
 937                u32 valid_crc1:1;       /* bit 1 */
 938                u32 valid_crc2:1;       /* bit 2 */
 939                u32 valid_crc3:1;       /* bit 3 */
 940                u32 valid_crc4:1;       /* bit 4 */
 941                u32 ignore_broad:1;     /* bit 5 */
 942                u32 ignore_multi:1;     /* bit 6 */
 943                u32 ignore_uni:1;       /* bit 7 */
 944                u32 ignore_link_chg:1;  /* bit 8 */
 945                u32 clr_intr:1;         /* bit 9 */
 946                u32 ignore_mp:1;        /* bit 10 */
 947                u32 ignore_pp:1;        /* bit 11 */
 948                u32 reserve:4;          /* bits 12-15 */
 949                u32 crc0:16;            /* bits 16-31 */
 950#endif
 951        } bits;
 952} RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
 953
 954/*
 955 * structure for CRC 1 and CRC 2 reg in rxmac address map
 956 * located at address 0x4008
 957 */
 958typedef union _RXMAC_WOL_CRC12_t {
 959        u32 value;
 960        struct {
 961#ifdef _BIT_FIELDS_HTOL
 962                u32 crc2:16;    /* bits 16-31 */
 963                u32 crc1:16;    /* bits 0-15 */
 964#else
 965                u32 crc1:16;    /* bits 0-15 */
 966                u32 crc2:16;    /* bits 16-31 */
 967#endif
 968        } bits;
 969} RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
 970
 971/*
 972 * structure for CRC 3 and CRC 4 reg in rxmac address map
 973 * located at address 0x400C
 974 */
 975typedef union _RXMAC_WOL_CRC34_t {
 976        u32 value;
 977        struct {
 978#ifdef _BIT_FIELDS_HTOL
 979                u32 crc4:16;    /* bits 16-31 */
 980                u32 crc3:16;    /* bits 0-15 */
 981#else
 982                u32 crc3:16;    /* bits 0-15 */
 983                u32 crc4:16;    /* bits 16-31 */
 984#endif
 985        } bits;
 986} RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
 987
 988/*
 989 * structure for Wake On Lan Source Address Lo reg in rxmac address map
 990 * located at address 0x4010
 991 */
 992typedef union _RXMAC_WOL_SA_LO_t {
 993        u32 value;
 994        struct {
 995#ifdef _BIT_FIELDS_HTOL
 996                u32 sa3:8;      /* bits 24-31 */
 997                u32 sa4:8;      /* bits 16-23 */
 998                u32 sa5:8;      /* bits 8-15 */
 999                u32 sa6:8;      /* bits 0-7 */
1000#else

1001                u32 sa6:8;      /* bits 0-7 */
1002                u32 sa5:8;      /* bits 8-15 */
1003                u32 sa4:8;      /* bits 16-23 */
1004                u32 sa3:8;      /* bits 24-31 */
1005#endif
1006        } bits;
1007} RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
1008
1009/*
1010 * structure for Wake On Lan Source Address Hi reg in rxmac address map
1011 * located at address 0x4014
1012 */
1013typedef union _RXMAC_WOL_SA_HI_t {
1014        u32 value;
1015        struct {
1016#ifdef _BIT_FIELDS_HTOL
1017                u32 reserved:16;        /* bits 16-31 */
1018                u32 sa1:8;              /* bits 8-15 */
1019                u32 sa2:8;              /* bits 0-7 */
1020#else
1021                u32 sa2:8;              /* bits 0-7 */
1022                u32 sa1:8;              /* bits 8-15 */
1023                u32 reserved:16;        /* bits 16-31 */
1024#endif
1025        } bits;
1026} RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
1027
1028/*
1029 * structure for Wake On Lan mask reg in rxmac address map
1030 * located at address 0x4018 - 0x4064
1031 * Defined earlier (u32)
1032 */
1033
1034/*
1035 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
1036 * located at address 0x4068
1037 */
1038typedef union _RXMAC_UNI_PF_ADDR1_t {
1039        u32 value;
1040        struct {
1041#ifdef _BIT_FIELDS_HTOL
1042                u32 addr1_3:8;  /* bits 24-31 */
1043                u32 addr1_4:8;  /* bits 16-23 */
1044                u32 addr1_5:8;  /* bits 8-15 */
1045                u32 addr1_6:8;  /* bits 0-7 */
1046#else
1047                u32 addr1_6:8;  /* bits 0-7 */
1048                u32 addr1_5:8;  /* bits 8-15 */
1049                u32 addr1_4:8;  /* bits 16-23 */
1050                u32 addr1_3:8;  /* bits 24-31 */
1051#endif
1052        } bits;
1053} RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
1054
1055/*
1056 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
1057 * located at address 0x406C
1058 */
1059typedef union _RXMAC_UNI_PF_ADDR2_t {
1060        u32 value;
1061        struct {
1062#ifdef _BIT_FIELDS_HTOL
1063                u32 addr2_3:8;  /* bits 24-31 */
1064                u32 addr2_4:8;  /* bits 16-23 */
1065                u32 addr2_5:8;  /* bits 8-15 */
1066                u32 addr2_6:8;  /* bits 0-7 */
1067#else
1068                u32 addr2_6:8;  /* bits 0-7 */
1069                u32 addr2_5:8;  /* bits 8-15 */
1070                u32 addr2_4:8;  /* bits 16-23 */
1071                u32 addr2_3:8;  /* bits 24-31 */
1072#endif
1073        } bits;
1074} RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
1075
1076/*
1077 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
1078 * located at address 0x4070
1079 */
1080typedef union _RXMAC_UNI_PF_ADDR3_t {
1081        u32 value;
1082        struct {
1083#ifdef _BIT_FIELDS_HTOL
1084                u32 addr2_1:8;  /* bits 24-31 */
1085                u32 addr2_2:8;  /* bits 16-23 */
1086                u32 addr1_1:8;  /* bits 8-15 */
1087                u32 addr1_2:8;  /* bits 0-7 */
1088#else
1089                u32 addr1_2:8;  /* bits 0-7 */
1090                u32 addr1_1:8;  /* bits 8-15 */
1091                u32 addr2_2:8;  /* bits 16-23 */
1092                u32 addr2_1:8;  /* bits 24-31 */
1093#endif
1094        } bits;
1095} RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
1096
1097/*
1098 * structure for Multicast Hash reg in rxmac address map
1099 * located at address 0x4074 - 0x4080
1100 * Defined earlier (u32)
1101 */
1102
1103/*
1104 * structure for Packet Filter Control reg in rxmac address map
1105 * located at address 0x4084
1106 */
1107typedef union _RXMAC_PF_CTRL_t {
1108        u32 value;
1109        struct {
1110#ifdef _BIT_FIELDS_HTOL
1111                u32 unused2:9;          /* bits 23-31 */
1112                u32 min_pkt_size:7;     /* bits 16-22 */
1113                u32 unused1:12;         /* bits 4-15 */
1114                u32 filter_frag_en:1;   /* bit 3 */
1115                u32 filter_uni_en:1;    /* bit 2 */
1116                u32 filter_multi_en:1;  /* bit 1 */
1117                u32 filter_broad_en:1;  /* bit 0 */
1118#else
1119                u32 filter_broad_en:1;  /* bit 0 */
1120                u32 filter_multi_en:1;  /* bit 1 */
1121                u32 filter_uni_en:1;    /* bit 2 */
1122                u32 filter_frag_en:1;   /* bit 3 */
1123                u32 unused1:12;         /* bits 4-15 */
1124                u32 min_pkt_size:7;     /* bits 16-22 */
1125                u32 unused2:9;          /* bits 23-31 */
1126#endif
1127        } bits;
1128} RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
1129
1130/*
1131 * structure for Memory Controller Interface Control Max Segment reg in rxmac
1132 * address map.  Located at address 0x4088
1133 */
1134typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
1135        u32 value;
1136        struct {
1137#ifdef _BIT_FIELDS_HTOL
1138                u32 reserved:22;        /* bits 10-31 */
1139                u32 max_size:8; /* bits 2-9 */
1140                u32 fc_en:1;    /* bit 1 */
1141                u32 seg_en:1;   /* bit 0 */
1142#else
1143                u32 seg_en:1;   /* bit 0 */
1144                u32 fc_en:1;    /* bit 1 */
1145                u32 max_size:8; /* bits 2-9 */
1146                u32 reserved:22;        /* bits 10-31 */
1147#endif
1148        } bits;
1149} RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1150
1151/*
1152 * structure for Memory Controller Interface Water Mark reg in rxmac address
1153 * map.  Located at address 0x408C
1154 */
1155typedef union _RXMAC_MCIF_WATER_MARK_t {
1156        u32 value;
1157        struct {
1158#ifdef _BIT_FIELDS_HTOL
1159                u32 reserved2:6;        /* bits 26-31 */
1160                u32 mark_hi:10; /* bits 16-25 */
1161                u32 reserved1:6;        /* bits 10-15 */
1162                u32 mark_lo:10; /* bits 0-9 */
1163#else
1164                u32 mark_lo:10; /* bits 0-9 */
1165                u32 reserved1:6;        /* bits 10-15 */
1166                u32 mark_hi:10; /* bits 16-25 */
1167                u32 reserved2:6;        /* bits 26-31 */
1168#endif
1169        } bits;
1170} RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1171
1172/*
1173 * structure for Rx Queue Dialog reg in rxmac address map.
1174 * located at address 0x4090
1175 */
1176typedef union _RXMAC_RXQ_DIAG_t {
1177        u32 value;
1178        struct {
1179#ifdef _BIT_FIELDS_HTOL
1180                u32 reserved2:6;        /* bits 26-31 */
1181                u32 rd_ptr:10;  /* bits 16-25 */
1182                u32 reserved1:6;        /* bits 10-15 */
1183                u32 wr_ptr:10;  /* bits 0-9 */
1184#else
1185                u32 wr_ptr:10;  /* bits 0-9 */
1186                u32 reserved1:6;        /* bits 10-15 */
1187                u32 rd_ptr:10;  /* bits 16-25 */
1188                u32 reserved2:6;        /* bits 26-31 */
1189#endif
1190        } bits;
1191} RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1192
1193/*
1194 * structure for space availiable reg in rxmac address map.
1195 * located at address 0x4094
1196 */
1197typedef union _RXMAC_SPACE_AVAIL_t {
1198        u32 value;
1199        struct {
1200#ifdef _BIT_FIELDS_HTOL
1201                u32 reserved2:15;               /* bits 17-31 */
1202                u32 space_avail_en:1;   /* bit 16 */
1203                u32 reserved1:6;                /* bits 10-15 */
1204                u32 space_avail:10;     /* bits 0-9 */
1205#else
1206                u32 space_avail:10;     /* bits 0-9 */
1207                u32 reserved1:6;                /* bits 10-15 */
1208                u32 space_avail_en:1;   /* bit 16 */
1209                u32 reserved2:15;               /* bits 17-31 */
1210#endif
1211        } bits;
1212} RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1213
1214/*
1215 * structure for management interface reg in rxmac address map.
1216 * located at address 0x4098
1217 */
1218typedef union _RXMAC_MIF_CTL_t {
1219        u32 value;
1220        struct {
1221#ifdef _BIT_FIELDS_HTOL
1222                u32 reserve:14;         /* bits 18-31 */
1223                u32 drop_pkt_en:1;              /* bit 17 */
1224                u32 drop_pkt_mask:17;   /* bits 0-16 */
1225#else
1226                u32 drop_pkt_mask:17;   /* bits 0-16 */
1227                u32 drop_pkt_en:1;              /* bit 17 */
1228                u32 reserve:14;         /* bits 18-31 */
1229#endif
1230        } bits;
1231} RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1232
1233/*
1234 * structure for Error reg in rxmac address map.
1235 * located at address 0x409C
1236 */
1237typedef union _RXMAC_ERROR_REG_t {
1238        u32 value;
1239        struct {
1240#ifdef _BIT_FIELDS_HTOL
1241                u32 reserve:28; /* bits 4-31 */
1242                u32 mif:1;              /* bit 3 */
1243                u32 async:1;    /* bit 2 */
1244                u32 pkt_filter:1;       /* bit 1 */
1245                u32 mcif:1;     /* bit 0 */
1246#else
1247                u32 mcif:1;     /* bit 0 */
1248                u32 pkt_filter:1;       /* bit 1 */
1249                u32 async:1;    /* bit 2 */
1250                u32 mif:1;              /* bit 3 */
1251                u32 reserve:28; /* bits 4-31 */
1252#endif
1253        } bits;
1254} RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1255
1256/*
1257 * Rx MAC Module of JAGCore Address Mapping
1258 */
1259typedef struct _RXMAC_t {                               /* Location: */
1260        RXMAC_CTRL_t ctrl;                              /*  0x4000 */
1261        RXMAC_WOL_CTL_CRC0_t crc0;                      /*  0x4004 */
1262        RXMAC_WOL_CRC12_t crc12;                        /*  0x4008 */
1263        RXMAC_WOL_CRC34_t crc34;                        /*  0x400C */
1264        RXMAC_WOL_SA_LO_t sa_lo;                        /*  0x4010 */
1265        RXMAC_WOL_SA_HI_t sa_hi;                        /*  0x4014 */
1266        u32 mask0_word0;                                /*  0x4018 */
1267        u32 mask0_word1;                                /*  0x401C */
1268        u32 mask0_word2;                                /*  0x4020 */
1269        u32 mask0_word3;                                /*  0x4024 */
1270        u32 mask1_word0;                                /*  0x4028 */
1271        u32 mask1_word1;                                /*  0x402C */
1272        u32 mask1_word2;                                /*  0x4030 */
1273        u32 mask1_word3;                                /*  0x4034 */
1274        u32 mask2_word0;                                /*  0x4038 */
1275        u32 mask2_word1;                                /*  0x403C */
1276        u32 mask2_word2;                                /*  0x4040 */
1277        u32 mask2_word3;                                /*  0x4044 */
1278        u32 mask3_word0;                                /*  0x4048 */
1279        u32 mask3_word1;                                /*  0x404C */
1280        u32 mask3_word2;                                /*  0x4050 */
1281        u32 mask3_word3;                                /*  0x4054 */
1282        u32 mask4_word0;                                /*  0x4058 */
1283        u32 mask4_word1;                                /*  0x405C */
1284        u32 mask4_word2;                                /*  0x4060 */
1285        u32 mask4_word3;                                /*  0x4064 */
1286        RXMAC_UNI_PF_ADDR1_t uni_pf_addr1;              /*  0x4068 */
1287        RXMAC_UNI_PF_ADDR2_t uni_pf_addr2;              /*  0x406C */
1288        RXMAC_UNI_PF_ADDR3_t uni_pf_addr3;              /*  0x4070 */
1289        u32 multi_hash1;                                /*  0x4074 */
1290        u32 multi_hash2;                                /*  0x4078 */
1291        u32 multi_hash3;                                /*  0x407C */
1292        u32 multi_hash4;                                /*  0x4080 */
1293        RXMAC_PF_CTRL_t pf_ctrl;                        /*  0x4084 */
1294        RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg;    /*  0x4088 */
1295        RXMAC_MCIF_WATER_MARK_t mcif_water_mark;        /*  0x408C */
1296        RXMAC_RXQ_DIAG_t rxq_diag;                      /*  0x4090 */
1297        RXMAC_SPACE_AVAIL_t space_avail;                /*  0x4094 */
1298
1299        RXMAC_MIF_CTL_t mif_ctrl;                       /*  0x4098 */
1300        RXMAC_ERROR_REG_t err_reg;                      /*  0x409C */
1301} RXMAC_t, *PRXMAC_t;
1302
1303/* END OF TXMAC REGISTER ADDRESS MAP */
1304
1305
1306/* START OF MAC REGISTER ADDRESS MAP */
1307
1308/*
1309 * structure for configuration #1 reg in mac address map.
1310 * located at address 0x5000
1311 */
1312typedef union _MAC_CFG1_t {
1313        u32 value;
1314        struct {
1315#ifdef _BIT_FIELDS_HTOL
1316                u32 soft_reset:1;               /* bit 31 */
1317                u32 sim_reset:1;                /* bit 30 */
1318                u32 reserved3:10;               /* bits 20-29 */
1319                u32 reset_rx_mc:1;              /* bit 19 */
1320                u32 reset_tx_mc:1;              /* bit 18 */
1321                u32 reset_rx_fun:1;     /* bit 17 */
1322                u32 reset_tx_fun:1;     /* bit 16 */
1323                u32 reserved2:7;                /* bits 9-15 */
1324                u32 loop_back:1;                /* bit 8 */
1325                u32 reserved1:2;                /* bits 6-7 */
1326                u32 rx_flow:1;          /* bit 5 */
1327                u32 tx_flow:1;          /* bit 4 */
1328                u32 syncd_rx_en:1;              /* bit 3 */
1329                u32 rx_enable:1;                /* bit 2 */
1330                u32 syncd_tx_en:1;              /* bit 1 */
1331                u32 tx_enable:1;                /* bit 0 */
1332#else
1333                u32 tx_enable:1;                /* bit 0 */
1334                u32 syncd_tx_en:1;              /* bit 1 */
1335                u32 rx_enable:1;                /* bit 2 */
1336                u32 syncd_rx_en:1;              /* bit 3 */
1337                u32 tx_flow:1;          /* bit 4 */
1338                u32 rx_flow:1;          /* bit 5 */
1339                u32 reserved1:2;                /* bits 6-7 */
1340                u32 loop_back:1;                /* bit 8 */
1341                u32 reserved2:7;                /* bits 9-15 */
1342                u32 reset_tx_fun:1;     /* bit 16 */
1343                u32 reset_rx_fun:1;     /* bit 17 */
1344                u32 reset_tx_mc:1;              /* bit 18 */
1345                u32 reset_rx_mc:1;              /* bit 19 */
1346                u32 reserved3:10;               /* bits 20-29 */
1347                u32 sim_reset:1;                /* bit 30 */
1348                u32 soft_reset:1;               /* bit 31 */
1349#endif
1350        } bits;
1351} MAC_CFG1_t, *PMAC_CFG1_t;
1352
1353/*
1354 * structure for configuration #2 reg in mac address map.
1355 * located at address 0x5004
1356 */
1357typedef union _MAC_CFG2_t {
1358        u32 value;
1359        struct {
1360#ifdef _BIT_FIELDS_HTOL
1361                u32 reserved3:16;               /* bits 16-31 */
1362                u32 preamble_len:4;     /* bits 12-15 */
1363                u32 reserved2:2;                /* bits 10-11 */
1364                u32 if_mode:2;          /* bits 8-9 */
1365                u32 reserved1:2;                /* bits 6-7 */
1366                u32 huge_frame:1;               /* bit 5 */
1367                u32 len_check:1;                /* bit 4 */
1368                u32 undefined:1;                /* bit 3 */
1369                u32 pad_crc:1;          /* bit 2 */
1370                u32 crc_enable:1;               /* bit 1 */
1371                u32 full_duplex:1;              /* bit 0 */
1372#else
1373                u32 full_duplex:1;              /* bit 0 */
1374                u32 crc_enable:1;               /* bit 1 */
1375                u32 pad_crc:1;          /* bit 2 */
1376                u32 undefined:1;                /* bit 3 */
1377                u32 len_check:1;                /* bit 4 */
1378                u32 huge_frame:1;               /* bit 5 */
1379                u32 reserved1:2;                /* bits 6-7 */
1380                u32 if_mode:2;          /* bits 8-9 */
1381                u32 reserved2:2;                /* bits 10-11 */
1382                u32 preamble_len:4;     /* bits 12-15 */
1383                u32 reserved3:16;               /* bits 16-31 */
1384#endif
1385        } bits;
1386} MAC_CFG2_t, *PMAC_CFG2_t;
1387
1388/*
1389 * structure for Interpacket gap reg in mac address map.
1390 * located at address 0x5008
1391 */
1392typedef union _MAC_IPG_t {
1393        u32 value;
1394        struct {
1395#ifdef _BIT_FIELDS_HTOL
1396                u32 reserved:1;         /* bit 31 */
1397                u32 non_B2B_ipg_1:7;    /* bits 24-30 */
1398                u32 undefined2:1;               /* bit 23 */
1399                u32 non_B2B_ipg_2:7;    /* bits 16-22 */
1400                u32 min_ifg_enforce:8;  /* bits 8-15 */
1401                u32 undefined1:1;               /* bit 7 */
1402                u32 B2B_ipg:7;          /* bits 0-6 */
1403#else
1404                u32 B2B_ipg:7;          /* bits 0-6 */
1405                u32 undefined1:1;               /* bit 7 */
1406                u32 min_ifg_enforce:8;  /* bits 8-15 */
1407                u32 non_B2B_ipg_2:7;    /* bits 16-22 */
1408                u32 undefined2:1;               /* bit 23 */
1409                u32 non_B2B_ipg_1:7;    /* bits 24-30 */
1410                u32 reserved:1;         /* bit 31 */
1411#endif
1412        } bits;
1413} MAC_IPG_t, *PMAC_IPG_t;
1414
1415/*
1416 * structure for half duplex reg in mac address map.
1417 * located at address 0x500C
1418 */
1419typedef union _MAC_HFDP_t {
1420        u32 value;
1421        struct {
1422#ifdef _BIT_FIELDS_HTOL
1423                u32 reserved2:8;                /* bits 24-31 */
1424                u32 alt_beb_trunc:4;    /* bits 23-20 */
1425                u32 alt_beb_enable:1;   /* bit 19 */
1426                u32 bp_no_backoff:1;    /* bit 18 */
1427                u32 no_backoff:1;               /* bit 17 */
1428                u32 excess_defer:1;     /* bit 16 */
1429                u32 rexmit_max:4;               /* bits 12-15 */
1430                u32 reserved1:2;                /* bits 10-11 */
1431                u32 coll_window:10;     /* bits 0-9 */
1432#else
1433                u32 coll_window:10;     /* bits 0-9 */
1434                u32 reserved1:2;                /* bits 10-11 */
1435                u32 rexmit_max:4;               /* bits 12-15 */
1436                u32 excess_defer:1;     /* bit 16 */
1437                u32 no_backoff:1;               /* bit 17 */
1438                u32 bp_no_backoff:1;    /* bit 18 */
1439                u32 alt_beb_enable:1;   /* bit 19 */
1440                u32 alt_beb_trunc:4;    /* bits 23-20 */
1441                u32 reserved2:8;                /* bits 24-31 */
1442#endif
1443        } bits;
1444} MAC_HFDP_t, *PMAC_HFDP_t;
1445
1446/*
1447 * structure for Maximum Frame Length reg in mac address map.
1448 * located at address 0x5010
1449 */
1450typedef union _MAC_MAX_FM_LEN_t {
1451        u32 value;
1452        struct {
1453#ifdef _BIT_FIELDS_HTOL
1454                u32 reserved:16;        /* bits 16-31 */
1455                u32 max_len:16; /* bits 0-15 */
1456#else
1457                u32 max_len:16; /* bits 0-15 */
1458                u32 reserved:16;        /* bits 16-31 */
1459#endif
1460        } bits;
1461} MAC_MAX_FM_LEN_t, *PMAC_MAX_FM_LEN_t;
1462
1463/*
1464 * structure for Reserve 1 reg in mac address map.
1465 * located at address 0x5014 - 0x5018
1466 * Defined earlier (u32)
1467 */
1468
1469/*
1470 * structure for Test reg in mac address map.
1471 * located at address 0x501C
1472 */
1473typedef union _MAC_TEST_t {
1474        u32 value;
1475        struct {
1476#ifdef _BIT_FIELDS_HTOL
1477                u32 unused:29;  /* bits 3-31 */
1478                u32 mac_test:3; /* bits 0-2 */
1479#else
1480                u32 mac_test:3; /* bits 0-2 */
1481                u32 unused:29;  /* bits 3-31 */
1482#endif
1483        } bits;
1484} MAC_TEST_t, *PMAC_TEST_t;
1485
1486/*
1487 * structure for MII Management Configuration reg in mac address map.
1488 * located at address 0x5020
1489 */
1490typedef union _MII_MGMT_CFG_t {
1491        u32 value;
1492        struct {
1493#ifdef _BIT_FIELDS_HTOL
1494                u32 reset_mii_mgmt:1;   /* bit 31 */
1495                u32 reserved:25;                /* bits 6-30 */
1496                u32 scan_auto_incremt:1;        /* bit 5 */
1497                u32 preamble_suppress:1;        /* bit 4 */
1498                u32 undefined:1;                /* bit 3 */
1499                u32 mgmt_clk_reset:3;   /* bits 0-2 */
1500#else
1501                u32 mgmt_clk_reset:3;   /* bits 0-2 */
1502                u32 undefined:1;                /* bit 3 */
1503                u32 preamble_suppress:1;        /* bit 4 */
1504                u32 scan_auto_incremt:1;        /* bit 5 */
1505                u32 reserved:25;                /* bits 6-30 */
1506                u32 reset_mii_mgmt:1;   /* bit 31 */
1507#endif
1508        } bits;
1509} MII_MGMT_CFG_t, *PMII_MGMT_CFG_t;
1510
1511/*
1512 * structure for MII Management Command reg in mac address map.
1513 * located at address 0x5024
1514 */
1515typedef union _MII_MGMT_CMD_t {
1516        u32 value;
1517        struct {
1518#ifdef _BIT_FIELDS_HTOL
1519                u32 reserved:30;        /* bits 2-31 */
1520                u32 scan_cycle:1;       /* bit 1 */
1521                u32 read_cycle:1;       /* bit 0 */
1522#else
1523                u32 read_cycle:1;       /* bit 0 */
1524                u32 scan_cycle:1;       /* bit 1 */
1525                u32 reserved:30;        /* bits 2-31 */
1526#endif
1527        } bits;
1528} MII_MGMT_CMD_t, *PMII_MGMT_CMD_t;
1529
1530/*
1531 * structure for MII Management Address reg in mac address map.
1532 * located at address 0x5028
1533 */
1534typedef union _MII_MGMT_ADDR_t {
1535        u32 value;
1536        struct {
1537#ifdef _BIT_FIELDS_HTOL
1538                u32 reserved2:19;       /* bit 13-31 */
1539                u32 phy_addr:5; /* bits 8-12 */
1540                u32 reserved1:3;        /* bits 5-7 */
1541                u32 reg_addr:5; /* bits 0-4 */
1542#else
1543                u32 reg_addr:5; /* bits 0-4 */
1544                u32 reserved1:3;        /* bits 5-7 */
1545                u32 phy_addr:5; /* bits 8-12 */
1546                u32 reserved2:19;       /* bit 13-31 */
1547#endif
1548        } bits;
1549} MII_MGMT_ADDR_t, *PMII_MGMT_ADDR_t;
1550
1551/*
1552 * structure for MII Management Control reg in mac address map.
1553 * located at address 0x502C
1554 */
1555typedef union _MII_MGMT_CTRL_t {
1556        u32 value;
1557        struct {
1558#ifdef _BIT_FIELDS_HTOL
1559                u32 reserved:16;        /* bits 16-31 */
1560                u32 phy_ctrl:16;        /* bits 0-15 */
1561#else
1562                u32 phy_ctrl:16;        /* bits 0-15 */
1563                u32 reserved:16;        /* bits 16-31 */
1564#endif
1565        } bits;
1566} MII_MGMT_CTRL_t, *PMII_MGMT_CTRL_t;
1567
1568/*
1569 * structure for MII Management Status reg in mac address map.
1570 * located at address 0x5030
1571 */
1572typedef union _MII_MGMT_STAT_t {
1573        u32 value;
1574        struct {
1575#ifdef _BIT_FIELDS_HTOL
1576                u32 reserved:16;        /* bits 16-31 */
1577                u32 phy_stat:16;        /* bits 0-15 */
1578#else
1579                u32 phy_stat:16;        /* bits 0-15 */
1580                u32 reserved:16;        /* bits 16-31 */
1581#endif
1582        } bits;
1583} MII_MGMT_STAT_t, *PMII_MGMT_STAT_t;
1584
1585/*
1586 * structure for MII Management Indicators reg in mac address map.
1587 * located at address 0x5034
1588 */
1589typedef union _MII_MGMT_INDICATOR_t {
1590        u32 value;
1591        struct {
1592#ifdef _BIT_FIELDS_HTOL
1593                u32 reserved:29;        /* bits 3-31 */
1594                u32 not_valid:1;        /* bit 2 */
1595                u32 scanning:1; /* bit 1 */
1596                u32 busy:1;     /* bit 0 */
1597#else
1598                u32 busy:1;     /* bit 0 */
1599                u32 scanning:1; /* bit 1 */
1600                u32 not_valid:1;        /* bit 2 */
1601                u32 reserved:29;        /* bits 3-31 */
1602#endif
1603        } bits;
1604} MII_MGMT_INDICATOR_t, *PMII_MGMT_INDICATOR_t;
1605
1606/*
1607 * structure for Interface Control reg in mac address map.
1608 * located at address 0x5038
1609 */
1610typedef union _MAC_IF_CTRL_t {
1611        u32 value;
1612        struct {
1613#ifdef _BIT_FIELDS_HTOL
1614                u32 reset_if_module:1;  /* bit 31 */
1615                u32 reserved4:3;                /* bit 28-30 */
1616                u32 tbi_mode:1;         /* bit 27 */
1617                u32 ghd_mode:1;         /* bit 26 */
1618                u32 lhd_mode:1;         /* bit 25 */
1619                u32 phy_mode:1;         /* bit 24 */
1620                u32 reset_per_mii:1;    /* bit 23 */
1621                u32 reserved3:6;                /* bits 17-22 */
1622                u32 speed:1;            /* bit 16 */
1623                u32 reset_pe100x:1;     /* bit 15 */
1624                u32 reserved2:4;                /* bits 11-14 */
1625                u32 force_quiet:1;              /* bit 10 */
1626                u32 no_cipher:1;                /* bit 9 */
1627                u32 disable_link_fail:1;        /* bit 8 */
1628                u32 reset_gpsi:1;               /* bit 7 */
1629                u32 reserved1:6;                /* bits 1-6 */
1630                u32 enab_jab_protect:1; /* bit 0 */
1631#else
1632                u32 enab_jab_protect:1; /* bit 0 */
1633                u32 reserved1:6;                /* bits 1-6 */
1634                u32 reset_gpsi:1;               /* bit 7 */
1635                u32 disable_link_fail:1;        /* bit 8 */
1636                u32 no_cipher:1;                /* bit 9 */
1637                u32 force_quiet:1;              /* bit 10 */
1638                u32 reserved2:4;                /* bits 11-14 */
1639                u32 reset_pe100x:1;     /* bit 15 */
1640                u32 speed:1;            /* bit 16 */
1641                u32 reserved3:6;                /* bits 17-22 */
1642                u32 reset_per_mii:1;    /* bit 23 */
1643                u32 phy_mode:1;         /* bit 24 */
1644                u32 lhd_mode:1;         /* bit 25 */
1645                u32 ghd_mode:1;         /* bit 26 */
1646                u32 tbi_mode:1;         /* bit 27 */
1647                u32 reserved4:3;                /* bit 28-30 */
1648                u32 reset_if_module:1;  /* bit 31 */
1649#endif
1650        } bits;
1651} MAC_IF_CTRL_t, *PMAC_IF_CTRL_t;
1652
1653/*
1654 * structure for Interface Status reg in mac address map.
1655 * located at address 0x503C
1656 */
1657typedef union _MAC_IF_STAT_t {
1658        u32 value;
1659        struct {
1660#ifdef _BIT_FIELDS_HTOL
1661                u32 reserved:22;                /* bits 10-31 */
1662                u32 excess_defer:1;     /* bit 9 */
1663                u32 clash:1;            /* bit 8 */
1664                u32 phy_jabber:1;               /* bit 7 */
1665                u32 phy_link_ok:1;              /* bit 6 */
1666                u32 phy_full_duplex:1;  /* bit 5 */
1667                u32 phy_speed:1;                /* bit 4 */
1668                u32 pe100x_link_fail:1; /* bit 3 */
1669                u32 pe10t_loss_carrie:1;        /* bit 2 */
1670                u32 pe10t_sqe_error:1;  /* bit 1 */
1671                u32 pe10t_jabber:1;     /* bit 0 */
1672#else
1673                u32 pe10t_jabber:1;     /* bit 0 */
1674                u32 pe10t_sqe_error:1;  /* bit 1 */
1675                u32 pe10t_loss_carrie:1;        /* bit 2 */
1676                u32 pe100x_link_fail:1; /* bit 3 */
1677                u32 phy_speed:1;                /* bit 4 */
1678                u32 phy_full_duplex:1;  /* bit 5 */
1679                u32 phy_link_ok:1;              /* bit 6 */
1680                u32 phy_jabber:1;               /* bit 7 */
1681                u32 clash:1;            /* bit 8 */
1682                u32 excess_defer:1;     /* bit 9 */
1683                u32 reserved:22;                /* bits 10-31 */
1684#endif
1685        } bits;
1686} MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1687
1688/*
1689 * structure for Mac Station Address, Part 1 reg in mac address map.
1690 * located at address 0x5040
1691 */
1692typedef union _MAC_STATION_ADDR1_t {
1693        u32 value;
1694        struct {
1695#ifdef _BIT_FIELDS_HTOL
1696                u32 Octet6:8;   /* bits 24-31 */
1697                u32 Octet5:8;   /* bits 16-23 */
1698                u32 Octet4:8;   /* bits 8-15 */
1699                u32 Octet3:8;   /* bits 0-7 */
1700#else
1701                u32 Octet3:8;   /* bits 0-7 */
1702                u32 Octet4:8;   /* bits 8-15 */
1703                u32 Octet5:8;   /* bits 16-23 */
1704                u32 Octet6:8;   /* bits 24-31 */
1705#endif
1706        } bits;
1707} MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1708
1709/*
1710 * structure for Mac Station Address, Part 2 reg in mac address map.
1711 * located at address 0x5044
1712 */
1713typedef union _MAC_STATION_ADDR2_t {
1714        u32 value;
1715        struct {
1716#ifdef _BIT_FIELDS_HTOL
1717                u32 Octet2:8;   /* bits 24-31 */
1718                u32 Octet1:8;   /* bits 16-23 */
1719                u32 reserved:16;        /* bits 0-15 */
1720#else
1721                u32 reserved:16;        /* bit 0-15 */
1722                u32 Octet1:8;   /* bits 16-23 */
1723                u32 Octet2:8;   /* bits 24-31 */
1724#endif
1725        } bits;
1726} MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1727
1728/*
1729 * MAC Module of JAGCore Address Mapping
1730 */
1731typedef struct _MAC_t {                                 /* Location: */
1732        MAC_CFG1_t cfg1;                                /*  0x5000 */
1733        MAC_CFG2_t cfg2;                                /*  0x5004 */
1734        MAC_IPG_t ipg;                                  /*  0x5008 */
1735        MAC_HFDP_t hfdp;                                /*  0x500C */
1736        MAC_MAX_FM_LEN_t max_fm_len;                    /*  0x5010 */
1737        u32 rsv1;                                       /*  0x5014 */
1738        u32 rsv2;                                       /*  0x5018 */
1739        MAC_TEST_t mac_test;                            /*  0x501C */
1740        MII_MGMT_CFG_t mii_mgmt_cfg;                    /*  0x5020 */
1741        MII_MGMT_CMD_t mii_mgmt_cmd;                    /*  0x5024 */
1742        MII_MGMT_ADDR_t mii_mgmt_addr;                  /*  0x5028 */
1743        MII_MGMT_CTRL_t mii_mgmt_ctrl;                  /*  0x502C */
1744        MII_MGMT_STAT_t mii_mgmt_stat;                  /*  0x5030 */
1745        MII_MGMT_INDICATOR_t mii_mgmt_indicator;        /*  0x5034 */
1746        MAC_IF_CTRL_t if_ctrl;                          /*  0x5038 */
1747        MAC_IF_STAT_t if_stat;                          /*  0x503C */
1748        MAC_STATION_ADDR1_t station_addr_1;             /*  0x5040 */
1749        MAC_STATION_ADDR2_t station_addr_2;             /*  0x5044 */
1750} MAC_t, *PMAC_t;
1751
1752/* END OF MAC REGISTER ADDRESS MAP */
1753
1754/* START OF MAC STAT REGISTER ADDRESS MAP */
1755
1756/*
1757 * structure for Carry Register One and it's Mask Register reg located in mac
1758 * stat address map address 0x6130 and 0x6138.
1759 */
1760typedef union _MAC_STAT_REG_1_t {
1761        u32 value;
1762        struct {
1763#ifdef _BIT_FIELDS_HTOL
1764                u32 tr64:1;     /* bit 31 */
1765                u32 tr127:1;    /* bit 30 */
1766                u32 tr255:1;    /* bit 29 */
1767                u32 tr511:1;    /* bit 28 */
1768                u32 tr1k:1;     /* bit 27 */
1769                u32 trmax:1;    /* bit 26 */
1770                u32 trmgv:1;    /* bit 25 */
1771                u32 unused:8;   /* bits 17-24 */
1772                u32 rbyt:1;     /* bit 16 */
1773                u32 rpkt:1;     /* bit 15 */
1774                u32 rfcs:1;     /* bit 14 */
1775                u32 rmca:1;     /* bit 13 */
1776                u32 rbca:1;     /* bit 12 */
1777                u32 rxcf:1;     /* bit 11 */
1778                u32 rxpf:1;     /* bit 10 */
1779                u32 rxuo:1;     /* bit 9 */
1780                u32 raln:1;     /* bit 8 */
1781                u32 rflr:1;     /* bit 7 */
1782                u32 rcde:1;     /* bit 6 */
1783                u32 rcse:1;     /* bit 5 */
1784                u32 rund:1;     /* bit 4 */
1785                u32 rovr:1;     /* bit 3 */
1786                u32 rfrg:1;     /* bit 2 */
1787                u32 rjbr:1;     /* bit 1 */
1788                u32 rdrp:1;     /* bit 0 */
1789#else
1790                u32 rdrp:1;     /* bit 0 */
1791                u32 rjbr:1;     /* bit 1 */
1792                u32 rfrg:1;     /* bit 2 */
1793                u32 rovr:1;     /* bit 3 */
1794                u32 rund:1;     /* bit 4 */
1795                u32 rcse:1;     /* bit 5 */
1796                u32 rcde:1;     /* bit 6 */
1797                u32 rflr:1;     /* bit 7 */
1798                u32 raln:1;     /* bit 8 */
1799                u32 rxuo:1;     /* bit 9 */
1800                u32 rxpf:1;     /* bit 10 */
1801                u32 rxcf:1;     /* bit 11 */
1802                u32 rbca:1;     /* bit 12 */
1803                u32 rmca:1;     /* bit 13 */
1804                u32 rfcs:1;     /* bit 14 */
1805                u32 rpkt:1;     /* bit 15 */
1806                u32 rbyt:1;     /* bit 16 */
1807                u32 unused:8;   /* bits 17-24 */
1808                u32 trmgv:1;    /* bit 25 */
1809                u32 trmax:1;    /* bit 26 */
1810                u32 tr1k:1;     /* bit 27 */
1811                u32 tr511:1;    /* bit 28 */
1812                u32 tr255:1;    /* bit 29 */
1813                u32 tr127:1;    /* bit 30 */
1814                u32 tr64:1;     /* bit 31 */
1815#endif
1816        } bits;
1817} MAC_STAT_REG_1_t, *PMAC_STAT_REG_1_t;
1818
1819/*
1820 * structure for Carry Register Two Mask Register reg in mac stat address map.
1821 * located at address 0x613C
1822 */
1823typedef union _MAC_STAT_REG_2_t {
1824        u32 value;
1825        struct {
1826#ifdef _BIT_FIELDS_HTOL
1827                u32 unused:12;  /* bit 20-31 */
1828                u32 tjbr:1;     /* bit 19 */
1829                u32 tfcs:1;     /* bit 18 */
1830                u32 txcf:1;     /* bit 17 */
1831                u32 tovr:1;     /* bit 16 */
1832                u32 tund:1;     /* bit 15 */
1833                u32 tfrg:1;     /* bit 14 */
1834                u32 tbyt:1;     /* bit 13 */
1835                u32 tpkt:1;     /* bit 12 */
1836                u32 tmca:1;     /* bit 11 */
1837                u32 tbca:1;     /* bit 10 */
1838                u32 txpf:1;     /* bit 9 */
1839                u32 tdfr:1;     /* bit 8 */
1840                u32 tedf:1;     /* bit 7 */
1841                u32 tscl:1;     /* bit 6 */
1842                u32 tmcl:1;     /* bit 5 */
1843                u32 tlcl:1;     /* bit 4 */
1844                u32 txcl:1;     /* bit 3 */
1845                u32 tncl:1;     /* bit 2 */
1846                u32 tpfh:1;     /* bit 1 */
1847                u32 tdrp:1;     /* bit 0 */
1848#else
1849                u32 tdrp:1;     /* bit 0 */
1850                u32 tpfh:1;     /* bit 1 */
1851                u32 tncl:1;     /* bit 2 */
1852                u32 txcl:1;     /* bit 3 */
1853                u32 tlcl:1;     /* bit 4 */
1854                u32 tmcl:1;     /* bit 5 */
1855                u32 tscl:1;     /* bit 6 */
1856                u32 tedf:1;     /* bit 7 */
1857                u32 tdfr:1;     /* bit 8 */
1858                u32 txpf:1;     /* bit 9 */
1859                u32 tbca:1;     /* bit 10 */
1860                u32 tmca:1;     /* bit 11 */
1861                u32 tpkt:1;     /* bit 12 */
1862                u32 tbyt:1;     /* bit 13 */
1863                u32 tfrg:1;     /* bit 14 */
1864                u32 tund:1;     /* bit 15 */
1865                u32 tovr:1;     /* bit 16 */
1866                u32 txcf:1;     /* bit 17 */
1867                u32 tfcs:1;     /* bit 18 */
1868                u32 tjbr:1;     /* bit 19 */
1869                u32 unused:12;  /* bit 20-31 */
1870#endif
1871        } bits;
1872} MAC_STAT_REG_2_t, *PMAC_STAT_REG_2_t;
1873
1874/*
1875 * MAC STATS Module of JAGCore Address Mapping
1876 */
1877typedef struct _MAC_STAT_t {            /* Location: */
1878        u32 pad[32];            /*  0x6000 - 607C */
1879
1880        /* Tx/Rx 0-64 Byte Frame Counter */
1881        u32 TR64;                       /*  0x6080 */
1882
1883        /* Tx/Rx 65-127 Byte Frame Counter */
1884        u32 TR127;                      /*  0x6084 */
1885
1886        /* Tx/Rx 128-255 Byte Frame Counter */
1887        u32 TR255;                      /*  0x6088 */
1888
1889        /* Tx/Rx 256-511 Byte Frame Counter */
1890        u32 TR511;                      /*  0x608C */
1891
1892        /* Tx/Rx 512-1023 Byte Frame Counter */
1893        u32 TR1K;                       /*  0x6090 */
1894
1895        /* Tx/Rx 1024-1518 Byte Frame Counter */
1896        u32 TRMax;                      /*  0x6094 */
1897
1898        /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1899        u32 TRMgv;                      /*  0x6098 */
1900
1901        /* Rx Byte Counter */
1902        u32 RByt;                       /*  0x609C */
1903
1904        /* Rx Packet Counter */
1905        u32 RPkt;                       /*  0x60A0 */
1906
1907        /* Rx FCS Error Counter */
1908        u32 RFcs;                       /*  0x60A4 */
1909
1910        /* Rx Multicast Packet Counter */
1911        u32 RMca;                       /*  0x60A8 */
1912
1913        /* Rx Broadcast Packet Counter */
1914        u32 RBca;                       /*  0x60AC */
1915
1916        /* Rx Control Frame Packet Counter */
1917        u32 RxCf;                       /*  0x60B0 */
1918
1919        /* Rx Pause Frame Packet Counter */
1920        u32 RxPf;                       /*  0x60B4 */
1921
1922        /* Rx Unknown OP Code Counter */
1923        u32 RxUo;                       /*  0x60B8 */
1924
1925        /* Rx Alignment Error Counter */
1926        u32 RAln;                       /*  0x60BC */
1927
1928        /* Rx Frame Length Error Counter */
1929        u32 RFlr;                       /*  0x60C0 */
1930
1931        /* Rx Code Error Counter */
1932        u32 RCde;                       /*  0x60C4 */
1933
1934        /* Rx Carrier Sense Error Counter */
1935        u32 RCse;                       /*  0x60C8 */
1936
1937        /* Rx Undersize Packet Counter */
1938        u32 RUnd;                       /*  0x60CC */
1939
1940        /* Rx Oversize Packet Counter */
1941        u32 ROvr;                       /*  0x60D0 */
1942
1943        /* Rx Fragment Counter */
1944        u32 RFrg;                       /*  0x60D4 */
1945
1946        /* Rx Jabber Counter */
1947        u32 RJbr;                       /*  0x60D8 */
1948
1949        /* Rx Drop */
1950        u32 RDrp;                       /*  0x60DC */
1951
1952        /* Tx Byte Counter */
1953        u32 TByt;                       /*  0x60E0 */
1954
1955        /* Tx Packet Counter */
1956        u32 TPkt;                       /*  0x60E4 */
1957
1958        /* Tx Multicast Packet Counter */
1959        u32 TMca;                       /*  0x60E8 */
1960
1961        /* Tx Broadcast Packet Counter */
1962        u32 TBca;                       /*  0x60EC */
1963
1964        /* Tx Pause Control Frame Counter */
1965        u32 TxPf;                       /*  0x60F0 */
1966
1967        /* Tx Deferral Packet Counter */
1968        u32 TDfr;                       /*  0x60F4 */
1969
1970        /* Tx Excessive Deferral Packet Counter */
1971        u32 TEdf;                       /*  0x60F8 */
1972
1973        /* Tx Single Collision Packet Counter */
1974        u32 TScl;                       /*  0x60FC */
1975
1976        /* Tx Multiple Collision Packet Counter */
1977        u32 TMcl;                       /*  0x6100 */
1978
1979        /* Tx Late Collision Packet Counter */
1980        u32 TLcl;                       /*  0x6104 */
1981
1982        /* Tx Excessive Collision Packet Counter */
1983        u32 TXcl;                       /*  0x6108 */
1984
1985        /* Tx Total Collision Packet Counter */
1986        u32 TNcl;                       /*  0x610C */
1987
1988        /* Tx Pause Frame Honored Counter */
1989        u32 TPfh;                       /*  0x6110 */
1990
1991        /* Tx Drop Frame Counter */
1992        u32 TDrp;                       /*  0x6114 */
1993
1994        /* Tx Jabber Frame Counter */
1995        u32 TJbr;                       /*  0x6118 */
1996
1997        /* Tx FCS Error Counter */
1998        u32 TFcs;                       /*  0x611C */
1999
2000        /* Tx Control Frame Counter */

2001        u32 TxCf;                       /*  0x6120 */
2002
2003        /* Tx Oversize Frame Counter */
2004        u32 TOvr;                       /*  0x6124 */
2005
2006        /* Tx Undersize Frame Counter */
2007        u32 TUnd;                       /*  0x6128 */
2008
2009        /* Tx Fragments Frame Counter */
2010        u32 TFrg;                       /*  0x612C */
2011
2012        /* Carry Register One Register */
2013        MAC_STAT_REG_1_t Carry1;        /*  0x6130 */
2014
2015        /* Carry Register Two Register */
2016        MAC_STAT_REG_2_t Carry2;        /*  0x6134 */
2017
2018        /* Carry Register One Mask Register */
2019        MAC_STAT_REG_1_t Carry1M;       /*  0x6138 */
2020
2021        /* Carry Register Two Mask Register */
2022        MAC_STAT_REG_2_t Carry2M;       /*  0x613C */
2023} MAC_STAT_t, *PMAC_STAT_t;
2024
2025/* END OF MAC STAT REGISTER ADDRESS MAP */
2026
2027
2028/* START OF MMC REGISTER ADDRESS MAP */
2029
2030/*
2031 * Main Memory Controller Control reg in mmc address map.
2032 * located at address 0x7000
2033 */
2034
2035#define ET_MMC_ENABLE           1
2036#define ET_MMC_ARB_DISABLE      2
2037#define ET_MMC_RXMAC_DISABLE    4
2038#define ET_MMC_TXMAC_DISABLE    8
2039#define ET_MMC_TXDMA_DISABLE    16
2040#define ET_MMC_RXDMA_DISABLE    32
2041#define ET_MMC_FORCE_CE         64
2042
2043/*
2044 * Main Memory Controller Host Memory Access Address reg in mmc
2045 * address map.  Located at address 0x7004. Top 16 bits hold the address bits
2046 */
2047
2048#define ET_SRAM_REQ_ACCESS      1
2049#define ET_SRAM_WR_ACCESS       2
2050#define ET_SRAM_IS_CTRL         4
2051
2052/*
2053 * structure for Main Memory Controller Host Memory Access Data reg in mmc
2054 * address map.  Located at address 0x7008 - 0x7014
2055 * Defined earlier (u32)
2056 */
2057
2058/*
2059 * Memory Control Module of JAGCore Address Mapping
2060 */
2061typedef struct _MMC_t {                 /* Location: */
2062        u32 mmc_ctrl;           /*  0x7000 */
2063        u32 sram_access;        /*  0x7004 */
2064        u32 sram_word1;         /*  0x7008 */
2065        u32 sram_word2;         /*  0x700C */
2066        u32 sram_word3;         /*  0x7010 */
2067        u32 sram_word4;         /*  0x7014 */
2068} MMC_t, *PMMC_t;
2069
2070/* END OF MMC REGISTER ADDRESS MAP */
2071
2072
2073/* START OF EXP ROM REGISTER ADDRESS MAP */
2074
2075/*
2076 * Expansion ROM Module of JAGCore Address Mapping
2077 */
2078
2079/* Take this out until it is not empty */
2080#if 0
2081typedef struct _EXP_ROM_t {
2082
2083} EXP_ROM_t, *PEXP_ROM_t;
2084#endif
2085
2086/* END OF EXP ROM REGISTER ADDRESS MAP */
2087
2088
2089/*
2090 * JAGCore Address Mapping
2091 */
2092typedef struct _ADDRESS_MAP_t {
2093        GLOBAL_t global;
2094        /* unused section of global address map */
2095        u8 unused_global[4096 - sizeof(GLOBAL_t)];
2096        TXDMA_t txdma;
2097        /* unused section of txdma address map */
2098        u8 unused_txdma[4096 - sizeof(TXDMA_t)];
2099        RXDMA_t rxdma;
2100        /* unused section of rxdma address map */
2101        u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
2102        TXMAC_t txmac;
2103        /* unused section of txmac address map */
2104        u8 unused_txmac[4096 - sizeof(TXMAC_t)];
2105        RXMAC_t rxmac;
2106        /* unused section of rxmac address map */
2107        u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
2108        MAC_t mac;
2109        /* unused section of mac address map */
2110        u8 unused_mac[4096 - sizeof(MAC_t)];
2111        MAC_STAT_t macStat;
2112        /* unused section of mac stat address map */
2113        u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
2114        MMC_t mmc;
2115        /* unused section of mmc address map */
2116        u8 unused_mmc[4096 - sizeof(MMC_t)];
2117        /* unused section of address map */
2118        u8 unused_[1015808];
2119
2120/* Take this out until it is not empty */
2121#if 0
2122        EXP_ROM_t exp_rom;
2123#endif
2124
2125        u8 unused_exp_rom[4096];        /* MGS-size TBD */
2126        u8 unused__[524288];    /* unused section of address map */
2127} ADDRESS_MAP_t, *PADDRESS_MAP_t;
2128
2129#endif /* _ET1310_ADDRESS_MAP_H_ */
2130