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59#ifndef __ET1310_RX_H__
60#define __ET1310_RX_H__
61
62#include "et1310_address_map.h"
63
64#define USE_FBR0 true
65
66#ifdef USE_FBR0
67
68#endif
69
70
71
72#define FBR_CHUNKS 32
73
74#define MAX_DESC_PER_RING_RX 1024
75
76
77#ifdef USE_FBR0
78#define RFD_LOW_WATER_MARK 40
79#define NIC_MIN_NUM_RFD 64
80#define NIC_DEFAULT_NUM_RFD 1024
81#else
82#define RFD_LOW_WATER_MARK 20
83#define NIC_MIN_NUM_RFD 64
84#define NIC_DEFAULT_NUM_RFD 256
85#endif
86
87#define NUM_PACKETS_HANDLED 256
88
89#define ALCATEL_BAD_STATUS 0xe47f0000
90#define ALCATEL_MULTICAST_PKT 0x01000000
91#define ALCATEL_BROADCAST_PKT 0x02000000
92
93
94typedef union _FBR_WORD2_t {
95 u32 value;
96 struct {
97#ifdef _BIT_FIELDS_HTOL
98 u32 reserved:22;
99 u32 bi:10;
100#else
101 u32 bi:10;
102 u32 reserved:22;
103#endif
104 } bits;
105} FBR_WORD2_t, *PFBR_WORD2_t;
106
107typedef struct _FBR_DESC_t {
108 u32 addr_lo;
109 u32 addr_hi;
110 FBR_WORD2_t word2;
111} FBR_DESC_t, *PFBR_DESC_t;
112
113
114typedef union _PKT_STAT_DESC_WORD0_t {
115 u32 value;
116 struct {
117#ifdef _BIT_FIELDS_HTOL
118
119
120#if 0
121 u32 asw_trunc:1;
122#endif
123 u32 asw_long_evt:1;
124 u32 asw_VLAN_tag:1;
125 u32 asw_unsupported_op:1;
126 u32 asw_pause_frame:1;
127 u32 asw_control_frame:1;
128 u32 asw_dribble_nibble:1;
129 u32 asw_broadcast:1;
130 u32 asw_multicast:1;
131 u32 asw_OK:1;
132 u32 asw_too_long:1;
133 u32 asw_len_chk_err:1;
134 u32 asw_CRC_err:1;
135 u32 asw_code_err:1;
136 u32 asw_false_carrier_event:1;
137 u32 asw_RX_DV_event:1;
138 u32 asw_prev_pkt_dropped:1;
139 u32 unused:5;
140 u32 vp:1;
141 u32 jp:1;
142 u32 ft:1;
143 u32 drop:1;
144 u32 rxmac_error:1;
145 u32 wol:1;
146 u32 tcpp:1;
147 u32 tcpa:1;
148 u32 ipp:1;
149 u32 ipa:1;
150 u32 hp:1;
151#else
152 u32 hp:1;
153 u32 ipa:1;
154 u32 ipp:1;
155 u32 tcpa:1;
156 u32 tcpp:1;
157 u32 wol:1;
158 u32 rxmac_error:1;
159 u32 drop:1;
160 u32 ft:1;
161 u32 jp:1;
162 u32 vp:1;
163 u32 unused:5;
164 u32 asw_prev_pkt_dropped:1;
165 u32 asw_RX_DV_event:1;
166 u32 asw_false_carrier_event:1;
167 u32 asw_code_err:1;
168 u32 asw_CRC_err:1;
169 u32 asw_len_chk_err:1;
170 u32 asw_too_long:1;
171 u32 asw_OK:1;
172 u32 asw_multicast:1;
173 u32 asw_broadcast:1;
174 u32 asw_dribble_nibble:1;
175 u32 asw_control_frame:1;
176 u32 asw_pause_frame:1;
177 u32 asw_unsupported_op:1;
178 u32 asw_VLAN_tag:1;
179 u32 asw_long_evt:1;
180#if 0
181 u32 asw_trunc:1;
182#endif
183#endif
184 } bits;
185} PKT_STAT_DESC_WORD0_t, *PPKT_STAT_WORD0_t;
186
187typedef union _PKT_STAT_DESC_WORD1_t {
188 u32 value;
189 struct {
190#ifdef _BIT_FIELDS_HTOL
191 u32 unused:4;
192 u32 ri:2;
193 u32 bi:10;
194 u32 length:16;
195#else
196 u32 length:16;
197 u32 bi:10;
198 u32 ri:2;
199 u32 unused:4;
200#endif
201 } bits;
202} PKT_STAT_DESC_WORD1_t, *PPKT_STAT_WORD1_t;
203
204typedef struct _PKT_STAT_DESC_t {
205 PKT_STAT_DESC_WORD0_t word0;
206 PKT_STAT_DESC_WORD1_t word1;
207} PKT_STAT_DESC_t, *PPKT_STAT_DESC_t;
208
209
210
211
212
213
214
215
216typedef union _rxstat_word0_t {
217 u32 value;
218 struct {
219#ifdef _BIT_FIELDS_HTOL
220 u32 FBR1unused:5;
221 u32 FBR1wrap:1;
222 u32 FBR1offset:10;
223 u32 FBR0unused:5;
224 u32 FBR0wrap:1;
225 u32 FBR0offset:10;
226#else
227 u32 FBR0offset:10;
228 u32 FBR0wrap:1;
229 u32 FBR0unused:5;
230 u32 FBR1offset:10;
231 u32 FBR1wrap:1;
232 u32 FBR1unused:5;
233#endif
234 } bits;
235} RXSTAT_WORD0_t, *PRXSTAT_WORD0_t;
236
237
238
239
240
241
242typedef union _rxstat_word1_t {
243 u32 value;
244 struct {
245#ifdef _BIT_FIELDS_HTOL
246 u32 PSRunused:3;
247 u32 PSRwrap:1;
248 u32 PSRoffset:12;
249 u32 reserved:16;
250#else
251 u32 reserved:16;
252 u32 PSRoffset:12;
253 u32 PSRwrap:1;
254 u32 PSRunused:3;
255#endif
256 } bits;
257} RXSTAT_WORD1_t, *PRXSTAT_WORD1_t;
258
259
260
261
262
263typedef struct _rx_status_block_t {
264 RXSTAT_WORD0_t Word0;
265 RXSTAT_WORD1_t Word1;
266} RX_STATUS_BLOCK_t, *PRX_STATUS_BLOCK_t;
267
268
269
270
271typedef struct _FbrLookupTable {
272 void *Va[MAX_DESC_PER_RING_RX];
273 void *Buffer1[MAX_DESC_PER_RING_RX];
274 void *Buffer2[MAX_DESC_PER_RING_RX];
275 u32 PAHigh[MAX_DESC_PER_RING_RX];
276 u32 PALow[MAX_DESC_PER_RING_RX];
277} FBRLOOKUPTABLE, *PFBRLOOKUPTABLE;
278
279typedef enum {
280 ONE_PACKET_INTERRUPT,
281 FOUR_PACKET_INTERRUPT
282} eRX_INTERRUPT_STATE_t, *PeRX_INTERRUPT_STATE_t;
283
284
285
286
287typedef struct rx_skb_list_elem {
288 struct list_head skb_list_elem;
289 dma_addr_t dma_addr;
290 struct sk_buff *skb;
291} RX_SKB_LIST_ELEM, *PRX_SKB_LIST_ELEM;
292
293
294
295
296
297typedef struct _rx_ring_t {
298#ifdef USE_FBR0
299 void *pFbr0RingVa;
300 dma_addr_t pFbr0RingPa;
301 void *Fbr0MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
302 dma_addr_t Fbr0MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
303 uint64_t Fbr0Realpa;
304 uint64_t Fbr0offset;
305 u32 local_Fbr0_full;
306 u32 Fbr0NumEntries;
307 u32 Fbr0BufferSize;
308#endif
309 void *pFbr1RingVa;
310 dma_addr_t pFbr1RingPa;
311 void *Fbr1MemVa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
312 dma_addr_t Fbr1MemPa[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
313 uint64_t Fbr1Realpa;
314 uint64_t Fbr1offset;
315 FBRLOOKUPTABLE *Fbr[2];
316 u32 local_Fbr1_full;
317 u32 Fbr1NumEntries;
318 u32 Fbr1BufferSize;
319
320 void *pPSRingVa;
321 dma_addr_t pPSRingPa;
322 uint64_t pPSRingRealPa;
323 uint64_t pPSRingOffset;
324 RXDMA_PSR_FULL_OFFSET_t local_psr_full;
325 u32 PsrNumEntries;
326
327 void *pRxStatusVa;
328 dma_addr_t pRxStatusPa;
329 uint64_t RxStatusRealPA;
330 uint64_t RxStatusOffset;
331
332 struct list_head RecvBufferPool;
333
334
335 struct list_head RecvList;
336 struct list_head RecvPendingList;
337 u32 nReadyRecv;
338
339 u32 NumRfd;
340
341 bool UnfinishedReceives;
342
343 struct list_head RecvPacketPool;
344
345
346 struct kmem_cache *RecvLookaside;
347} RX_RING_t, *PRX_RING_t;
348
349
350struct _MP_RFD;
351
352
353struct et131x_adapter;
354
355
356int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter);
357void et131x_rx_dma_memory_free(struct et131x_adapter *adapter);
358int et131x_rfd_resources_alloc(struct et131x_adapter *adapter,
359 struct _MP_RFD *pMpRfd);
360void et131x_rfd_resources_free(struct et131x_adapter *adapter,
361 struct _MP_RFD *pMpRfd);
362int et131x_init_recv(struct et131x_adapter *adapter);
363
364void ConfigRxDmaRegs(struct et131x_adapter *adapter);
365void SetRxDmaTimer(struct et131x_adapter *adapter);
366void et131x_rx_dma_disable(struct et131x_adapter *adapter);
367void et131x_rx_dma_enable(struct et131x_adapter *adapter);
368
369void et131x_reset_recv(struct et131x_adapter *adapter);
370
371void et131x_handle_recv_interrupt(struct et131x_adapter *adapter);
372
373#endif
374