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40#define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
41#define UDC_DRIVER_VERSION_STRING "01.00.0206 - $Revision: #3 $"
42
43
44#include <linux/module.h>
45#include <linux/pci.h>
46#include <linux/kernel.h>
47#include <linux/delay.h>
48#include <linux/ioport.h>
49#include <linux/sched.h>
50#include <linux/slab.h>
51#include <linux/errno.h>
52#include <linux/init.h>
53#include <linux/timer.h>
54#include <linux/list.h>
55#include <linux/interrupt.h>
56#include <linux/ioctl.h>
57#include <linux/fs.h>
58#include <linux/dmapool.h>
59#include <linux/moduleparam.h>
60#include <linux/device.h>
61#include <linux/io.h>
62#include <linux/irq.h>
63
64#include <asm/byteorder.h>
65#include <asm/system.h>
66#include <asm/unaligned.h>
67
68
69#include <linux/usb/ch9.h>
70#include <linux/usb/gadget.h>
71
72
73#include "amd5536udc.h"
74
75
76static void udc_tasklet_disconnect(unsigned long);
77static void empty_req_queue(struct udc_ep *);
78static int udc_probe(struct udc *dev);
79static void udc_basic_init(struct udc *dev);
80static void udc_setup_endpoints(struct udc *dev);
81static void udc_soft_reset(struct udc *dev);
82static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
83static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
84static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
85static int udc_create_dma_chain(struct udc_ep *ep, struct udc_request *req,
86 unsigned long buf_len, gfp_t gfp_flags);
87static int udc_remote_wakeup(struct udc *dev);
88static int udc_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id);
89static void udc_pci_remove(struct pci_dev *pdev);
90
91
92static const char mod_desc[] = UDC_MOD_DESCRIPTION;
93static const char name[] = "amd5536udc";
94
95
96static const struct usb_ep_ops udc_ep_ops;
97
98
99static union udc_setup_data setup_data;
100
101
102static struct udc *udc;
103
104
105static DEFINE_SPINLOCK(udc_irq_spinlock);
106
107static DEFINE_SPINLOCK(udc_stall_spinlock);
108
109
110
111
112
113static unsigned int udc_rxfifo_pending;
114
115
116static int soft_reset_occured;
117static int soft_reset_after_usbreset_occured;
118
119
120static struct timer_list udc_timer;
121static int stop_timer;
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137static int set_rde = -1;
138
139static DECLARE_COMPLETION(on_exit);
140static struct timer_list udc_pollstall_timer;
141static int stop_pollstall_timer;
142static DECLARE_COMPLETION(on_pollstall_exit);
143
144
145static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
146 (unsigned long) &udc);
147
148
149
150static const char ep0_string[] = "ep0in";
151static const char *ep_string[] = {
152 ep0_string,
153 "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
154 "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
155 "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
156 "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
157 "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
158 "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
159 "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
160};
161
162
163static int use_dma = 1;
164
165static int use_dma_ppb = 1;
166
167static int use_dma_ppb_du;
168
169static int use_dma_bufferfill_mode;
170
171static int use_fullspeed;
172
173static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
174
175
176module_param(use_dma, bool, S_IRUGO);
177MODULE_PARM_DESC(use_dma, "true for DMA");
178module_param(use_dma_ppb, bool, S_IRUGO);
179MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
180module_param(use_dma_ppb_du, bool, S_IRUGO);
181MODULE_PARM_DESC(use_dma_ppb_du,
182 "true for DMA in packet per buffer mode with descriptor update");
183module_param(use_fullspeed, bool, S_IRUGO);
184MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
185
186
187
188static void print_regs(struct udc *dev)
189{
190 DBG(dev, "------- Device registers -------\n");
191 DBG(dev, "dev config = %08x\n", readl(&dev->regs->cfg));
192 DBG(dev, "dev control = %08x\n", readl(&dev->regs->ctl));
193 DBG(dev, "dev status = %08x\n", readl(&dev->regs->sts));
194 DBG(dev, "\n");
195 DBG(dev, "dev int's = %08x\n", readl(&dev->regs->irqsts));
196 DBG(dev, "dev intmask = %08x\n", readl(&dev->regs->irqmsk));
197 DBG(dev, "\n");
198 DBG(dev, "dev ep int's = %08x\n", readl(&dev->regs->ep_irqsts));
199 DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
200 DBG(dev, "\n");
201 DBG(dev, "USE DMA = %d\n", use_dma);
202 if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
203 DBG(dev, "DMA mode = PPBNDU (packet per buffer "
204 "WITHOUT desc. update)\n");
205 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBNDU");
206 } else if (use_dma && use_dma_ppb_du && use_dma_ppb_du) {
207 DBG(dev, "DMA mode = PPBDU (packet per buffer "
208 "WITH desc. update)\n");
209 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "PPBDU");
210 }
211 if (use_dma && use_dma_bufferfill_mode) {
212 DBG(dev, "DMA mode = BF (buffer fill mode)\n");
213 dev_info(&dev->pdev->dev, "DMA mode (%s)\n", "BF");
214 }
215 if (!use_dma) {
216 dev_info(&dev->pdev->dev, "FIFO mode\n");
217 }
218 DBG(dev, "-------------------------------------------------------\n");
219}
220
221
222static int udc_mask_unused_interrupts(struct udc *dev)
223{
224 u32 tmp;
225
226
227 tmp = AMD_BIT(UDC_DEVINT_SVC) |
228 AMD_BIT(UDC_DEVINT_ENUM) |
229 AMD_BIT(UDC_DEVINT_US) |
230 AMD_BIT(UDC_DEVINT_UR) |
231 AMD_BIT(UDC_DEVINT_ES) |
232 AMD_BIT(UDC_DEVINT_SI) |
233 AMD_BIT(UDC_DEVINT_SOF)|
234 AMD_BIT(UDC_DEVINT_SC);
235 writel(tmp, &dev->regs->irqmsk);
236
237
238 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
239
240 return 0;
241}
242
243
244static int udc_enable_ep0_interrupts(struct udc *dev)
245{
246 u32 tmp;
247
248 DBG(dev, "udc_enable_ep0_interrupts()\n");
249
250
251 tmp = readl(&dev->regs->ep_irqmsk);
252
253 tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
254 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
255 writel(tmp, &dev->regs->ep_irqmsk);
256
257 return 0;
258}
259
260
261static int udc_enable_dev_setup_interrupts(struct udc *dev)
262{
263 u32 tmp;
264
265 DBG(dev, "enable device interrupts for setup data\n");
266
267
268 tmp = readl(&dev->regs->irqmsk);
269
270
271 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
272 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
273 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
274 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
275 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
276 writel(tmp, &dev->regs->irqmsk);
277
278 return 0;
279}
280
281
282static int udc_set_txfifo_addr(struct udc_ep *ep)
283{
284 struct udc *dev;
285 u32 tmp;
286 int i;
287
288 if (!ep || !(ep->in))
289 return -EINVAL;
290
291 dev = ep->dev;
292 ep->txfifo = dev->txfifo;
293
294
295 for (i = 0; i < ep->num; i++) {
296 if (dev->ep[i].regs) {
297
298 tmp = readl(&dev->ep[i].regs->bufin_framenum);
299 tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
300 ep->txfifo += tmp;
301 }
302 }
303 return 0;
304}
305
306
307static u32 cnak_pending;
308
309static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
310{
311 if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
312 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
313 cnak_pending |= 1 << (num);
314 ep->naking = 1;
315 } else
316 cnak_pending = cnak_pending & (~(1 << (num)));
317}
318
319
320
321static int
322udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
323{
324 struct udc_ep *ep;
325 struct udc *dev;
326 u32 tmp;
327 unsigned long iflags;
328 u8 udc_csr_epix;
329 unsigned maxpacket;
330
331 if (!usbep
332 || usbep->name == ep0_string
333 || !desc
334 || desc->bDescriptorType != USB_DT_ENDPOINT)
335 return -EINVAL;
336
337 ep = container_of(usbep, struct udc_ep, ep);
338 dev = ep->dev;
339
340 DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
341
342 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
343 return -ESHUTDOWN;
344
345 spin_lock_irqsave(&dev->lock, iflags);
346 ep->desc = desc;
347
348 ep->halted = 0;
349
350
351 tmp = readl(&dev->ep[ep->num].regs->ctl);
352 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
353 writel(tmp, &dev->ep[ep->num].regs->ctl);
354
355
356 maxpacket = le16_to_cpu(desc->wMaxPacketSize);
357 tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
358 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
359 ep->ep.maxpacket = maxpacket;
360 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
361
362
363 if (ep->in) {
364
365
366 udc_csr_epix = ep->num;
367
368
369 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
370
371 tmp = AMD_ADDBITS(
372 tmp,
373 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
374 / UDC_DWORD_BYTES,
375 UDC_EPIN_BUFF_SIZE);
376 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
377
378
379 udc_set_txfifo_addr(ep);
380
381
382 tmp = readl(&ep->regs->ctl);
383 tmp |= AMD_BIT(UDC_EPCTL_F);
384 writel(tmp, &ep->regs->ctl);
385
386
387 } else {
388
389 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
390
391
392 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
393 tmp = AMD_ADDBITS(tmp, maxpacket,
394 UDC_CSR_NE_MAX_PKT);
395 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
396
397 if (use_dma && !ep->in) {
398
399 ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
400 ep->bna_occurred = 0;
401 }
402
403 if (ep->num != UDC_EP0OUT_IX)
404 dev->data_ep_enabled = 1;
405 }
406
407
408 tmp = readl(&dev->csr->ne[udc_csr_epix]);
409
410 tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
411
412 tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
413
414 tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
415
416 tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
417
418 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
419
420 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
421
422 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
423
424 writel(tmp, &dev->csr->ne[udc_csr_epix]);
425
426
427 tmp = readl(&dev->regs->ep_irqmsk);
428 tmp &= AMD_UNMASK_BIT(ep->num);
429 writel(tmp, &dev->regs->ep_irqmsk);
430
431
432
433
434
435 if (!use_dma || ep->in) {
436 tmp = readl(&ep->regs->ctl);
437 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
438 writel(tmp, &ep->regs->ctl);
439 ep->naking = 0;
440 UDC_QUEUE_CNAK(ep, ep->num);
441 }
442 tmp = desc->bEndpointAddress;
443 DBG(dev, "%s enabled\n", usbep->name);
444
445 spin_unlock_irqrestore(&dev->lock, iflags);
446 return 0;
447}
448
449
450static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
451{
452 u32 tmp;
453
454 VDBG(ep->dev, "ep-%d reset\n", ep->num);
455 ep->desc = NULL;
456 ep->ep.ops = &udc_ep_ops;
457 INIT_LIST_HEAD(&ep->queue);
458
459 ep->ep.maxpacket = (u16) ~0;
460
461 tmp = readl(&ep->regs->ctl);
462 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
463 writel(tmp, &ep->regs->ctl);
464 ep->naking = 1;
465
466
467 tmp = readl(®s->ep_irqmsk);
468 tmp |= AMD_BIT(ep->num);
469 writel(tmp, ®s->ep_irqmsk);
470
471 if (ep->in) {
472
473 tmp = readl(&ep->regs->ctl);
474 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
475 writel(tmp, &ep->regs->ctl);
476
477 tmp = readl(&ep->regs->sts);
478 tmp |= AMD_BIT(UDC_EPSTS_IN);
479 writel(tmp, &ep->regs->sts);
480
481
482 tmp = readl(&ep->regs->ctl);
483 tmp |= AMD_BIT(UDC_EPCTL_F);
484 writel(tmp, &ep->regs->ctl);
485
486 }
487
488 writel(0, &ep->regs->desptr);
489}
490
491
492static int udc_ep_disable(struct usb_ep *usbep)
493{
494 struct udc_ep *ep = NULL;
495 unsigned long iflags;
496
497 if (!usbep)
498 return -EINVAL;
499
500 ep = container_of(usbep, struct udc_ep, ep);
501 if (usbep->name == ep0_string || !ep->desc)
502 return -EINVAL;
503
504 DBG(ep->dev, "Disable ep-%d\n", ep->num);
505
506 spin_lock_irqsave(&ep->dev->lock, iflags);
507 udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
508 empty_req_queue(ep);
509 ep_init(ep->dev->regs, ep);
510 spin_unlock_irqrestore(&ep->dev->lock, iflags);
511
512 return 0;
513}
514
515
516static struct usb_request *
517udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
518{
519 struct udc_request *req;
520 struct udc_data_dma *dma_desc;
521 struct udc_ep *ep;
522
523 if (!usbep)
524 return NULL;
525
526 ep = container_of(usbep, struct udc_ep, ep);
527
528 VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
529 req = kzalloc(sizeof(struct udc_request), gfp);
530 if (!req)
531 return NULL;
532
533 req->req.dma = DMA_DONT_USE;
534 INIT_LIST_HEAD(&req->queue);
535
536 if (ep->dma) {
537
538 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
539 &req->td_phys);
540 if (!dma_desc) {
541 kfree(req);
542 return NULL;
543 }
544
545 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
546 "td_phys = %lx\n",
547 req, dma_desc,
548 (unsigned long)req->td_phys);
549
550 dma_desc->status = AMD_ADDBITS(dma_desc->status,
551 UDC_DMA_STP_STS_BS_HOST_BUSY,
552 UDC_DMA_STP_STS_BS);
553 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
554 req->td_data = dma_desc;
555 req->td_data_last = NULL;
556 req->chain_len = 1;
557 }
558
559 return &req->req;
560}
561
562
563static void
564udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
565{
566 struct udc_ep *ep;
567 struct udc_request *req;
568
569 if (!usbep || !usbreq)
570 return;
571
572 ep = container_of(usbep, struct udc_ep, ep);
573 req = container_of(usbreq, struct udc_request, req);
574 VDBG(ep->dev, "free_req req=%p\n", req);
575 BUG_ON(!list_empty(&req->queue));
576 if (req->td_data) {
577 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
578
579
580 if (req->chain_len > 1) {
581 udc_free_dma_chain(ep->dev, req);
582 }
583
584 pci_pool_free(ep->dev->data_requests, req->td_data,
585 req->td_phys);
586 }
587 kfree(req);
588}
589
590
591static void udc_init_bna_dummy(struct udc_request *req)
592{
593 if (req) {
594
595 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
596
597 req->td_data->next = req->td_phys;
598
599 req->td_data->status
600 = AMD_ADDBITS(req->td_data->status,
601 UDC_DMA_STP_STS_BS_DMA_DONE,
602 UDC_DMA_STP_STS_BS);
603#ifdef UDC_VERBOSE
604 pr_debug("bna desc = %p, sts = %08x\n",
605 req->td_data, req->td_data->status);
606#endif
607 }
608}
609
610
611static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
612{
613 struct udc_request *req = NULL;
614 struct usb_request *_req = NULL;
615
616
617 _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
618 if (_req) {
619 req = container_of(_req, struct udc_request, req);
620 ep->bna_dummy_req = req;
621 udc_init_bna_dummy(req);
622 }
623 return req;
624}
625
626
627static void
628udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
629{
630 u8 *req_buf;
631 u32 *buf;
632 int i, j;
633 unsigned bytes = 0;
634 unsigned remaining = 0;
635
636 if (!req || !ep)
637 return;
638
639 req_buf = req->buf + req->actual;
640 prefetch(req_buf);
641 remaining = req->length - req->actual;
642
643 buf = (u32 *) req_buf;
644
645 bytes = ep->ep.maxpacket;
646 if (bytes > remaining)
647 bytes = remaining;
648
649
650 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
651 writel(*(buf + i), ep->txfifo);
652 }
653
654
655 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
656 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
657 ep->txfifo);
658 }
659
660
661 writel(0, &ep->regs->confirm);
662}
663
664
665static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
666{
667 int i;
668
669 VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
670
671 for (i = 0; i < dwords; i++) {
672 *(buf + i) = readl(dev->rxfifo);
673 }
674 return 0;
675}
676
677
678static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
679{
680 int i, j;
681 u32 tmp;
682
683 VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
684
685
686 for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) {
687 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
688 }
689
690
691 if (bytes % UDC_DWORD_BYTES) {
692 tmp = readl(dev->rxfifo);
693 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
694 *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
695 tmp = tmp >> UDC_BITS_PER_BYTE;
696 }
697 }
698
699 return 0;
700}
701
702
703static int
704udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
705{
706 u8 *buf;
707 unsigned buf_space;
708 unsigned bytes = 0;
709 unsigned finished = 0;
710
711
712 bytes = readl(&ep->regs->sts);
713 bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
714
715 buf_space = req->req.length - req->req.actual;
716 buf = req->req.buf + req->req.actual;
717 if (bytes > buf_space) {
718 if ((buf_space % ep->ep.maxpacket) != 0) {
719 DBG(ep->dev,
720 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
721 ep->ep.name, bytes, buf_space);
722 req->req.status = -EOVERFLOW;
723 }
724 bytes = buf_space;
725 }
726 req->req.actual += bytes;
727
728
729 if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
730 || ((req->req.actual == req->req.length) && !req->req.zero))
731 finished = 1;
732
733
734 VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
735 udc_rxfifo_read_bytes(ep->dev, buf, bytes);
736
737 return finished;
738}
739
740
741static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
742{
743 int retval = 0;
744 u32 tmp;
745
746 VDBG(ep->dev, "prep_dma\n");
747 VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
748 ep->num, req->td_data);
749
750
751 req->td_data->bufptr = req->req.dma;
752
753
754 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
755
756
757 if (use_dma_ppb) {
758
759 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
760 if (retval != 0) {
761 if (retval == -ENOMEM)
762 DBG(ep->dev, "Out of DMA memory\n");
763 return retval;
764 }
765 if (ep->in) {
766 if (req->req.length == ep->ep.maxpacket) {
767
768 req->td_data->status =
769 AMD_ADDBITS(req->td_data->status,
770 ep->ep.maxpacket,
771 UDC_DMA_IN_STS_TXBYTES);
772
773 }
774 }
775
776 }
777
778 if (ep->in) {
779 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
780 "maxpacket=%d ep%d\n",
781 use_dma_ppb, req->req.length,
782 ep->ep.maxpacket, ep->num);
783
784
785
786
787 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
788 || ep->num == UDC_EP0OUT_IX
789 || ep->num == UDC_EP0IN_IX) {
790
791 req->td_data->status =
792 AMD_ADDBITS(req->td_data->status,
793 req->req.length,
794 UDC_DMA_IN_STS_TXBYTES);
795
796 req->td_data->status =
797 AMD_ADDBITS(req->td_data->status,
798 0,
799 UDC_DMA_IN_STS_FRAMENUM);
800 }
801
802 req->td_data->status =
803 AMD_ADDBITS(req->td_data->status,
804 UDC_DMA_STP_STS_BS_HOST_BUSY,
805 UDC_DMA_STP_STS_BS);
806 } else {
807 VDBG(ep->dev, "OUT set host ready\n");
808
809 req->td_data->status =
810 AMD_ADDBITS(req->td_data->status,
811 UDC_DMA_STP_STS_BS_HOST_READY,
812 UDC_DMA_STP_STS_BS);
813
814
815
816 if (ep->naking) {
817 tmp = readl(&ep->regs->ctl);
818 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
819 writel(tmp, &ep->regs->ctl);
820 ep->naking = 0;
821 UDC_QUEUE_CNAK(ep, ep->num);
822 }
823
824 }
825
826 return retval;
827}
828
829
830static void
831complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
832__releases(ep->dev->lock)
833__acquires(ep->dev->lock)
834{
835 struct udc *dev;
836 unsigned halted;
837
838 VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
839
840 dev = ep->dev;
841
842 if (req->dma_mapping) {
843 if (ep->in)
844 pci_unmap_single(dev->pdev,
845 req->req.dma,
846 req->req.length,
847 PCI_DMA_TODEVICE);
848 else
849 pci_unmap_single(dev->pdev,
850 req->req.dma,
851 req->req.length,
852 PCI_DMA_FROMDEVICE);
853 req->dma_mapping = 0;
854 req->req.dma = DMA_DONT_USE;
855 }
856
857 halted = ep->halted;
858 ep->halted = 1;
859
860
861 if (req->req.status == -EINPROGRESS)
862 req->req.status = sts;
863
864
865 list_del_init(&req->queue);
866
867 VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
868 &req->req, req->req.length, ep->ep.name, sts);
869
870 spin_unlock(&dev->lock);
871 req->req.complete(&ep->ep, &req->req);
872 spin_lock(&dev->lock);
873 ep->halted = halted;
874}
875
876
877static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
878{
879
880 int ret_val = 0;
881 struct udc_data_dma *td;
882 struct udc_data_dma *td_last = NULL;
883 unsigned int i;
884
885 DBG(dev, "free chain req = %p\n", req);
886
887
888 td_last = req->td_data;
889 td = phys_to_virt(td_last->next);
890
891 for (i = 1; i < req->chain_len; i++) {
892
893 pci_pool_free(dev->data_requests, td,
894 (dma_addr_t) td_last->next);
895 td_last = td;
896 td = phys_to_virt(td_last->next);
897 }
898
899 return ret_val;
900}
901
902
903static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
904{
905 struct udc_data_dma *td;
906
907 td = req->td_data;
908 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
909 td = phys_to_virt(td->next);
910 }
911
912 return td;
913
914}
915
916
917static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
918{
919 struct udc_data_dma *td;
920 u32 count;
921
922 td = req->td_data;
923
924 count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
925
926 while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
927 td = phys_to_virt(td->next);
928
929 if (td) {
930 count += AMD_GETBITS(td->status,
931 UDC_DMA_OUT_STS_RXBYTES);
932 }
933 }
934
935 return count;
936
937}
938
939
940static int udc_create_dma_chain(
941 struct udc_ep *ep,
942 struct udc_request *req,
943 unsigned long buf_len, gfp_t gfp_flags
944)
945{
946 unsigned long bytes = req->req.length;
947 unsigned int i;
948 dma_addr_t dma_addr;
949 struct udc_data_dma *td = NULL;
950 struct udc_data_dma *last = NULL;
951 unsigned long txbytes;
952 unsigned create_new_chain = 0;
953 unsigned len;
954
955 VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
956 bytes, buf_len);
957 dma_addr = DMA_DONT_USE;
958
959
960 if (!ep->in) {
961 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
962 }
963
964
965 len = req->req.length / ep->ep.maxpacket;
966 if (req->req.length % ep->ep.maxpacket) {
967 len++;
968 }
969
970 if (len > req->chain_len) {
971
972 if (req->chain_len > 1) {
973 udc_free_dma_chain(ep->dev, req);
974 }
975 req->chain_len = len;
976 create_new_chain = 1;
977 }
978
979 td = req->td_data;
980
981 for (i = buf_len; i < bytes; i += buf_len) {
982
983 if (create_new_chain) {
984
985 td = pci_pool_alloc(ep->dev->data_requests,
986 gfp_flags, &dma_addr);
987 if (!td)
988 return -ENOMEM;
989
990 td->status = 0;
991 } else if (i == buf_len) {
992
993 td = (struct udc_data_dma *) phys_to_virt(
994 req->td_data->next);
995 td->status = 0;
996 } else {
997 td = (struct udc_data_dma *) phys_to_virt(last->next);
998 td->status = 0;
999 }
1000
1001
1002 if (td)
1003 td->bufptr = req->req.dma + i;
1004 else
1005 break;
1006
1007
1008 if ((bytes - i) >= buf_len) {
1009 txbytes = buf_len;
1010 } else {
1011
1012 txbytes = bytes - i;
1013 }
1014
1015
1016 if (i == buf_len) {
1017 if (create_new_chain) {
1018 req->td_data->next = dma_addr;
1019 } else {
1020
1021 }
1022
1023 if (ep->in) {
1024
1025 req->td_data->status =
1026 AMD_ADDBITS(req->td_data->status,
1027 ep->ep.maxpacket,
1028 UDC_DMA_IN_STS_TXBYTES);
1029
1030 td->status = AMD_ADDBITS(td->status,
1031 txbytes,
1032 UDC_DMA_IN_STS_TXBYTES);
1033 }
1034 } else {
1035 if (create_new_chain) {
1036 last->next = dma_addr;
1037 } else {
1038
1039 }
1040 if (ep->in) {
1041
1042 td->status = AMD_ADDBITS(td->status,
1043 txbytes,
1044 UDC_DMA_IN_STS_TXBYTES);
1045 }
1046 }
1047 last = td;
1048 }
1049
1050 if (td) {
1051 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
1052
1053 req->td_data_last = td;
1054 }
1055
1056 return 0;
1057}
1058
1059
1060static void udc_set_rde(struct udc *dev)
1061{
1062 u32 tmp;
1063
1064 VDBG(dev, "udc_set_rde()\n");
1065
1066 if (timer_pending(&udc_timer)) {
1067 set_rde = 0;
1068 mod_timer(&udc_timer, jiffies - 1);
1069 }
1070
1071 tmp = readl(&dev->regs->ctl);
1072 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1073 writel(tmp, &dev->regs->ctl);
1074}
1075
1076
1077static int
1078udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1079{
1080 int retval = 0;
1081 u8 open_rxfifo = 0;
1082 unsigned long iflags;
1083 struct udc_ep *ep;
1084 struct udc_request *req;
1085 struct udc *dev;
1086 u32 tmp;
1087
1088
1089 req = container_of(usbreq, struct udc_request, req);
1090
1091 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1092 || !list_empty(&req->queue))
1093 return -EINVAL;
1094
1095 ep = container_of(usbep, struct udc_ep, ep);
1096 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1097 return -EINVAL;
1098
1099 VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1100 dev = ep->dev;
1101
1102 if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1103 return -ESHUTDOWN;
1104
1105
1106 if (ep->dma && usbreq->length != 0
1107 && (usbreq->dma == DMA_DONT_USE || usbreq->dma == 0)) {
1108 VDBG(dev, "DMA map req %p\n", req);
1109 if (ep->in)
1110 usbreq->dma = pci_map_single(dev->pdev,
1111 usbreq->buf,
1112 usbreq->length,
1113 PCI_DMA_TODEVICE);
1114 else
1115 usbreq->dma = pci_map_single(dev->pdev,
1116 usbreq->buf,
1117 usbreq->length,
1118 PCI_DMA_FROMDEVICE);
1119 req->dma_mapping = 1;
1120 }
1121
1122 VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1123 usbep->name, usbreq, usbreq->length,
1124 req->td_data, usbreq->buf);
1125
1126 spin_lock_irqsave(&dev->lock, iflags);
1127 usbreq->actual = 0;
1128 usbreq->status = -EINPROGRESS;
1129 req->dma_done = 0;
1130
1131
1132 if (list_empty(&ep->queue)) {
1133
1134 if (usbreq->length == 0) {
1135
1136 complete_req(ep, req, 0);
1137 VDBG(dev, "%s: zlp\n", ep->ep.name);
1138
1139
1140
1141
1142 if (dev->set_cfg_not_acked) {
1143 tmp = readl(&dev->regs->ctl);
1144 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1145 writel(tmp, &dev->regs->ctl);
1146 dev->set_cfg_not_acked = 0;
1147 }
1148
1149 if (dev->waiting_zlp_ack_ep0in) {
1150
1151 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1152 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1153 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1154 dev->ep[UDC_EP0IN_IX].naking = 0;
1155 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1156 UDC_EP0IN_IX);
1157 dev->waiting_zlp_ack_ep0in = 0;
1158 }
1159 goto finished;
1160 }
1161 if (ep->dma) {
1162 retval = prep_dma(ep, req, gfp);
1163 if (retval != 0)
1164 goto finished;
1165
1166 if (ep->in) {
1167
1168 req->td_data->status =
1169 AMD_ADDBITS(req->td_data->status,
1170 UDC_DMA_IN_STS_BS_HOST_READY,
1171 UDC_DMA_IN_STS_BS);
1172 }
1173
1174
1175 if (!ep->in) {
1176
1177 if (timer_pending(&udc_timer)) {
1178 set_rde = 0;
1179 mod_timer(&udc_timer, jiffies - 1);
1180 }
1181
1182 tmp = readl(&dev->regs->ctl);
1183 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1184 writel(tmp, &dev->regs->ctl);
1185 open_rxfifo = 1;
1186
1187
1188
1189
1190
1191 if (ep->bna_occurred) {
1192 VDBG(dev, "copy to BNA dummy desc.\n");
1193 memcpy(ep->bna_dummy_req->td_data,
1194 req->td_data,
1195 sizeof(struct udc_data_dma));
1196 }
1197 }
1198
1199 writel(req->td_phys, &ep->regs->desptr);
1200
1201
1202 if (ep->naking) {
1203 tmp = readl(&ep->regs->ctl);
1204 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1205 writel(tmp, &ep->regs->ctl);
1206 ep->naking = 0;
1207 UDC_QUEUE_CNAK(ep, ep->num);
1208 }
1209
1210 if (ep->in) {
1211
1212 tmp = readl(&dev->regs->ep_irqmsk);
1213 tmp &= AMD_UNMASK_BIT(ep->num);
1214 writel(tmp, &dev->regs->ep_irqmsk);
1215 }
1216 } else if (ep->in) {
1217
1218 tmp = readl(&dev->regs->ep_irqmsk);
1219 tmp &= AMD_UNMASK_BIT(ep->num);
1220 writel(tmp, &dev->regs->ep_irqmsk);
1221 }
1222
1223 } else if (ep->dma) {
1224
1225
1226
1227
1228
1229 if (ep->in) {
1230 retval = prep_dma(ep, req, gfp);
1231 if (retval != 0)
1232 goto finished;
1233 }
1234 }
1235 VDBG(dev, "list_add\n");
1236
1237 if (req) {
1238
1239 list_add_tail(&req->queue, &ep->queue);
1240
1241
1242 if (open_rxfifo) {
1243
1244 req->dma_going = 1;
1245 udc_set_rde(dev);
1246 if (ep->num != UDC_EP0OUT_IX)
1247 dev->data_ep_queued = 1;
1248 }
1249
1250 if (!ep->in) {
1251 if (!use_dma && udc_rxfifo_pending) {
1252 DBG(dev, "udc_queue(): pending bytes in "
1253 "rxfifo after nyet\n");
1254
1255
1256
1257
1258 if (udc_rxfifo_read(ep, req)) {
1259
1260 complete_req(ep, req, 0);
1261 }
1262 udc_rxfifo_pending = 0;
1263
1264 }
1265 }
1266 }
1267
1268finished:
1269 spin_unlock_irqrestore(&dev->lock, iflags);
1270 return retval;
1271}
1272
1273
1274static void empty_req_queue(struct udc_ep *ep)
1275{
1276 struct udc_request *req;
1277
1278 ep->halted = 1;
1279 while (!list_empty(&ep->queue)) {
1280 req = list_entry(ep->queue.next,
1281 struct udc_request,
1282 queue);
1283 complete_req(ep, req, -ESHUTDOWN);
1284 }
1285}
1286
1287
1288static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1289{
1290 struct udc_ep *ep;
1291 struct udc_request *req;
1292 unsigned halted;
1293 unsigned long iflags;
1294
1295 ep = container_of(usbep, struct udc_ep, ep);
1296 if (!usbep || !usbreq || (!ep->desc && (ep->num != 0
1297 && ep->num != UDC_EP0OUT_IX)))
1298 return -EINVAL;
1299
1300 req = container_of(usbreq, struct udc_request, req);
1301
1302 spin_lock_irqsave(&ep->dev->lock, iflags);
1303 halted = ep->halted;
1304 ep->halted = 1;
1305
1306 if (ep->queue.next == &req->queue) {
1307 if (ep->dma && req->dma_going) {
1308 if (ep->in)
1309 ep->cancel_transfer = 1;
1310 else {
1311 u32 tmp;
1312 u32 dma_sts;
1313
1314 tmp = readl(&udc->regs->ctl);
1315 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1316 &udc->regs->ctl);
1317
1318
1319
1320
1321 dma_sts = AMD_GETBITS(req->td_data->status,
1322 UDC_DMA_OUT_STS_BS);
1323 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1324 ep->cancel_transfer = 1;
1325 else {
1326 udc_init_bna_dummy(ep->req);
1327 writel(ep->bna_dummy_req->td_phys,
1328 &ep->regs->desptr);
1329 }
1330 writel(tmp, &udc->regs->ctl);
1331 }
1332 }
1333 }
1334 complete_req(ep, req, -ECONNRESET);
1335 ep->halted = halted;
1336
1337 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1338 return 0;
1339}
1340
1341
1342static int
1343udc_set_halt(struct usb_ep *usbep, int halt)
1344{
1345 struct udc_ep *ep;
1346 u32 tmp;
1347 unsigned long iflags;
1348 int retval = 0;
1349
1350 if (!usbep)
1351 return -EINVAL;
1352
1353 pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1354
1355 ep = container_of(usbep, struct udc_ep, ep);
1356 if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1357 return -EINVAL;
1358 if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1359 return -ESHUTDOWN;
1360
1361 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1362
1363 if (halt) {
1364 if (ep->num == 0)
1365 ep->dev->stall_ep0in = 1;
1366 else {
1367
1368
1369
1370
1371 tmp = readl(&ep->regs->ctl);
1372 tmp |= AMD_BIT(UDC_EPCTL_S);
1373 writel(tmp, &ep->regs->ctl);
1374 ep->halted = 1;
1375
1376
1377 if (!timer_pending(&udc_pollstall_timer)) {
1378 udc_pollstall_timer.expires = jiffies +
1379 HZ * UDC_POLLSTALL_TIMER_USECONDS
1380 / (1000 * 1000);
1381 if (!stop_pollstall_timer) {
1382 DBG(ep->dev, "start polltimer\n");
1383 add_timer(&udc_pollstall_timer);
1384 }
1385 }
1386 }
1387 } else {
1388
1389 if (ep->halted) {
1390 tmp = readl(&ep->regs->ctl);
1391
1392 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1393
1394 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1395 writel(tmp, &ep->regs->ctl);
1396 ep->halted = 0;
1397 UDC_QUEUE_CNAK(ep, ep->num);
1398 }
1399 }
1400 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1401 return retval;
1402}
1403
1404
1405static const struct usb_ep_ops udc_ep_ops = {
1406 .enable = udc_ep_enable,
1407 .disable = udc_ep_disable,
1408
1409 .alloc_request = udc_alloc_request,
1410 .free_request = udc_free_request,
1411
1412 .queue = udc_queue,
1413 .dequeue = udc_dequeue,
1414
1415 .set_halt = udc_set_halt,
1416
1417};
1418
1419
1420
1421
1422static int udc_get_frame(struct usb_gadget *gadget)
1423{
1424 return -EOPNOTSUPP;
1425}
1426
1427
1428static int udc_wakeup(struct usb_gadget *gadget)
1429{
1430 struct udc *dev;
1431
1432 if (!gadget)
1433 return -EINVAL;
1434 dev = container_of(gadget, struct udc, gadget);
1435 udc_remote_wakeup(dev);
1436
1437 return 0;
1438}
1439
1440
1441static const struct usb_gadget_ops udc_ops = {
1442 .wakeup = udc_wakeup,
1443 .get_frame = udc_get_frame,
1444};
1445
1446
1447static void make_ep_lists(struct udc *dev)
1448{
1449
1450 INIT_LIST_HEAD(&dev->gadget.ep_list);
1451 list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1452 &dev->gadget.ep_list);
1453 list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1454 &dev->gadget.ep_list);
1455 list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1456 &dev->gadget.ep_list);
1457
1458
1459 dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1460 if (dev->gadget.speed == USB_SPEED_FULL)
1461 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1462 else if (dev->gadget.speed == USB_SPEED_HIGH)
1463 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1464 dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1465}
1466
1467
1468static int startup_registers(struct udc *dev)
1469{
1470 u32 tmp;
1471
1472
1473 udc_soft_reset(dev);
1474
1475
1476 udc_mask_unused_interrupts(dev);
1477
1478
1479 udc_basic_init(dev);
1480
1481 udc_setup_endpoints(dev);
1482
1483
1484 tmp = readl(&dev->regs->cfg);
1485 if (use_fullspeed) {
1486 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1487 } else {
1488 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1489 }
1490 writel(tmp, &dev->regs->cfg);
1491
1492 return 0;
1493}
1494
1495
1496static void udc_basic_init(struct udc *dev)
1497{
1498 u32 tmp;
1499
1500 DBG(dev, "udc_basic_init()\n");
1501
1502 dev->gadget.speed = USB_SPEED_UNKNOWN;
1503
1504
1505 if (timer_pending(&udc_timer)) {
1506 set_rde = 0;
1507 mod_timer(&udc_timer, jiffies - 1);
1508 }
1509
1510 if (timer_pending(&udc_pollstall_timer)) {
1511 mod_timer(&udc_pollstall_timer, jiffies - 1);
1512 }
1513
1514 tmp = readl(&dev->regs->ctl);
1515 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1516 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1517 writel(tmp, &dev->regs->ctl);
1518
1519
1520 tmp = readl(&dev->regs->cfg);
1521 tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1522
1523 tmp |= AMD_BIT(UDC_DEVCFG_SP);
1524
1525 tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1526 writel(tmp, &dev->regs->cfg);
1527
1528 make_ep_lists(dev);
1529
1530 dev->data_ep_enabled = 0;
1531 dev->data_ep_queued = 0;
1532}
1533
1534
1535static void udc_setup_endpoints(struct udc *dev)
1536{
1537 struct udc_ep *ep;
1538 u32 tmp;
1539 u32 reg;
1540
1541 DBG(dev, "udc_setup_endpoints()\n");
1542
1543
1544 tmp = readl(&dev->regs->sts);
1545 tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1546 if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) {
1547 dev->gadget.speed = USB_SPEED_HIGH;
1548 } else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) {
1549 dev->gadget.speed = USB_SPEED_FULL;
1550 }
1551
1552
1553 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1554 ep = &dev->ep[tmp];
1555 ep->dev = dev;
1556 ep->ep.name = ep_string[tmp];
1557 ep->num = tmp;
1558
1559 ep->txfifo = dev->txfifo;
1560
1561
1562 if (tmp < UDC_EPIN_NUM) {
1563 ep->fifo_depth = UDC_TXFIFO_SIZE;
1564 ep->in = 1;
1565 } else {
1566 ep->fifo_depth = UDC_RXFIFO_SIZE;
1567 ep->in = 0;
1568
1569 }
1570 ep->regs = &dev->ep_regs[tmp];
1571
1572
1573
1574
1575
1576 if (!ep->desc) {
1577 ep_init(dev->regs, ep);
1578 }
1579
1580 if (use_dma) {
1581
1582
1583
1584
1585
1586 ep->dma = &dev->regs->ctl;
1587
1588
1589 if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1590 && tmp > UDC_EPIN_NUM) {
1591
1592 reg = readl(&dev->ep[tmp].regs->ctl);
1593 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1594 writel(reg, &dev->ep[tmp].regs->ctl);
1595 dev->ep[tmp].naking = 1;
1596
1597 }
1598 }
1599 }
1600
1601 if (dev->gadget.speed == USB_SPEED_FULL) {
1602 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
1603 dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
1604 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1605 } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1606 dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
1607 dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
1608 }
1609
1610
1611
1612
1613
1614 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1615 dev->ep[UDC_EP0IN_IX].halted = 0;
1616 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1617
1618
1619 dev->cur_config = 0;
1620 dev->cur_intf = 0;
1621 dev->cur_alt = 0;
1622}
1623
1624
1625static void usb_connect(struct udc *dev)
1626{
1627
1628 dev_info(&dev->pdev->dev, "USB Connect\n");
1629
1630 dev->connected = 1;
1631
1632
1633 udc_basic_init(dev);
1634
1635
1636 udc_enable_dev_setup_interrupts(dev);
1637}
1638
1639
1640
1641
1642
1643static void usb_disconnect(struct udc *dev)
1644{
1645
1646 dev_info(&dev->pdev->dev, "USB Disconnect\n");
1647
1648 dev->connected = 0;
1649
1650
1651 udc_mask_unused_interrupts(dev);
1652
1653
1654
1655
1656
1657
1658 tasklet_schedule(&disconnect_tasklet);
1659}
1660
1661
1662static void udc_tasklet_disconnect(unsigned long par)
1663{
1664 struct udc *dev = (struct udc *)(*((struct udc **) par));
1665 u32 tmp;
1666
1667 DBG(dev, "Tasklet disconnect\n");
1668 spin_lock_irq(&dev->lock);
1669
1670 if (dev->driver) {
1671 spin_unlock(&dev->lock);
1672 dev->driver->disconnect(&dev->gadget);
1673 spin_lock(&dev->lock);
1674
1675
1676 for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1677 empty_req_queue(&dev->ep[tmp]);
1678 }
1679
1680 }
1681
1682
1683 ep_init(dev->regs,
1684 &dev->ep[UDC_EP0IN_IX]);
1685
1686
1687 if (!soft_reset_occured) {
1688
1689 udc_soft_reset(dev);
1690 soft_reset_occured++;
1691 }
1692
1693
1694 udc_enable_dev_setup_interrupts(dev);
1695
1696 if (use_fullspeed) {
1697 tmp = readl(&dev->regs->cfg);
1698 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1699 writel(tmp, &dev->regs->cfg);
1700 }
1701
1702 spin_unlock_irq(&dev->lock);
1703}
1704
1705
1706static void udc_soft_reset(struct udc *dev)
1707{
1708 unsigned long flags;
1709
1710 DBG(dev, "Soft reset\n");
1711
1712
1713
1714
1715
1716 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1717
1718 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1719
1720 spin_lock_irqsave(&udc_irq_spinlock, flags);
1721 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1722 readl(&dev->regs->cfg);
1723 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1724
1725}
1726
1727
1728static void udc_timer_function(unsigned long v)
1729{
1730 u32 tmp;
1731
1732 spin_lock_irq(&udc_irq_spinlock);
1733
1734 if (set_rde > 0) {
1735
1736
1737
1738
1739 if (set_rde > 1) {
1740
1741 tmp = readl(&udc->regs->ctl);
1742 tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1743 writel(tmp, &udc->regs->ctl);
1744 set_rde = -1;
1745 } else if (readl(&udc->regs->sts)
1746 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1747
1748
1749
1750
1751 udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1752 if (!stop_timer) {
1753 add_timer(&udc_timer);
1754 }
1755 } else {
1756
1757
1758
1759
1760
1761
1762
1763 set_rde++;
1764
1765 udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1766 if (!stop_timer) {
1767 add_timer(&udc_timer);
1768 }
1769 }
1770
1771 } else
1772 set_rde = -1;
1773 spin_unlock_irq(&udc_irq_spinlock);
1774 if (stop_timer)
1775 complete(&on_exit);
1776
1777}
1778
1779
1780static void udc_handle_halt_state(struct udc_ep *ep)
1781{
1782 u32 tmp;
1783
1784 if (ep->halted == 1) {
1785 tmp = readl(&ep->regs->ctl);
1786
1787 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1788
1789
1790
1791
1792
1793
1794
1795
1796
1797
1798
1799
1800
1801 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1802 writel(tmp, &ep->regs->ctl);
1803 ep->halted = 0;
1804 UDC_QUEUE_CNAK(ep, ep->num);
1805 }
1806 }
1807}
1808
1809
1810static void udc_pollstall_timer_function(unsigned long v)
1811{
1812 struct udc_ep *ep;
1813 int halted = 0;
1814
1815 spin_lock_irq(&udc_stall_spinlock);
1816
1817
1818
1819
1820 ep = &udc->ep[UDC_EPIN_IX];
1821 udc_handle_halt_state(ep);
1822 if (ep->halted)
1823 halted = 1;
1824
1825 ep = &udc->ep[UDC_EPOUT_IX];
1826 udc_handle_halt_state(ep);
1827 if (ep->halted)
1828 halted = 1;
1829
1830
1831 if (!stop_pollstall_timer && halted) {
1832 udc_pollstall_timer.expires = jiffies +
1833 HZ * UDC_POLLSTALL_TIMER_USECONDS
1834 / (1000 * 1000);
1835 add_timer(&udc_pollstall_timer);
1836 }
1837 spin_unlock_irq(&udc_stall_spinlock);
1838
1839 if (stop_pollstall_timer)
1840 complete(&on_pollstall_exit);
1841}
1842
1843
1844static void activate_control_endpoints(struct udc *dev)
1845{
1846 u32 tmp;
1847
1848 DBG(dev, "activate_control_endpoints\n");
1849
1850
1851 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1852 tmp |= AMD_BIT(UDC_EPCTL_F);
1853 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1854
1855
1856 dev->ep[UDC_EP0IN_IX].in = 1;
1857 dev->ep[UDC_EP0OUT_IX].in = 0;
1858
1859
1860 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1861 if (dev->gadget.speed == USB_SPEED_FULL)
1862 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1863 UDC_EPIN_BUFF_SIZE);
1864 else if (dev->gadget.speed == USB_SPEED_HIGH)
1865 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1866 UDC_EPIN_BUFF_SIZE);
1867 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1868
1869
1870 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1871 if (dev->gadget.speed == USB_SPEED_FULL)
1872 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1873 UDC_EP_MAX_PKT_SIZE);
1874 else if (dev->gadget.speed == USB_SPEED_HIGH)
1875 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1876 UDC_EP_MAX_PKT_SIZE);
1877 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1878
1879
1880 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1881 if (dev->gadget.speed == USB_SPEED_FULL)
1882 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1883 UDC_EP_MAX_PKT_SIZE);
1884 else if (dev->gadget.speed == USB_SPEED_HIGH)
1885 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1886 UDC_EP_MAX_PKT_SIZE);
1887 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1888
1889
1890 tmp = readl(&dev->csr->ne[0]);
1891 if (dev->gadget.speed == USB_SPEED_FULL)
1892 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1893 UDC_CSR_NE_MAX_PKT);
1894 else if (dev->gadget.speed == USB_SPEED_HIGH)
1895 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1896 UDC_CSR_NE_MAX_PKT);
1897 writel(tmp, &dev->csr->ne[0]);
1898
1899 if (use_dma) {
1900 dev->ep[UDC_EP0OUT_IX].td->status |=
1901 AMD_BIT(UDC_DMA_OUT_STS_L);
1902
1903 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1904 &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1905 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1906 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1907
1908 if (timer_pending(&udc_timer)) {
1909 set_rde = 0;
1910 mod_timer(&udc_timer, jiffies - 1);
1911 }
1912
1913 if (timer_pending(&udc_pollstall_timer)) {
1914 mod_timer(&udc_pollstall_timer, jiffies - 1);
1915 }
1916
1917 tmp = readl(&dev->regs->ctl);
1918 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1919 | AMD_BIT(UDC_DEVCTL_RDE)
1920 | AMD_BIT(UDC_DEVCTL_TDE);
1921 if (use_dma_bufferfill_mode) {
1922 tmp |= AMD_BIT(UDC_DEVCTL_BF);
1923 } else if (use_dma_ppb_du) {
1924 tmp |= AMD_BIT(UDC_DEVCTL_DU);
1925 }
1926 writel(tmp, &dev->regs->ctl);
1927 }
1928
1929
1930 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1931 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1932 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1933 dev->ep[UDC_EP0IN_IX].naking = 0;
1934 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1935
1936
1937 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1938 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1939 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1940 dev->ep[UDC_EP0OUT_IX].naking = 0;
1941 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1942}
1943
1944
1945static int setup_ep0(struct udc *dev)
1946{
1947 activate_control_endpoints(dev);
1948
1949 udc_enable_ep0_interrupts(dev);
1950
1951 udc_enable_dev_setup_interrupts(dev);
1952
1953 return 0;
1954}
1955
1956
1957int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1958{
1959 struct udc *dev = udc;
1960 int retval;
1961 u32 tmp;
1962
1963 if (!driver || !driver->bind || !driver->setup
1964 || driver->speed != USB_SPEED_HIGH)
1965 return -EINVAL;
1966 if (!dev)
1967 return -ENODEV;
1968 if (dev->driver)
1969 return -EBUSY;
1970
1971 driver->driver.bus = NULL;
1972 dev->driver = driver;
1973 dev->gadget.dev.driver = &driver->driver;
1974
1975 retval = driver->bind(&dev->gadget);
1976
1977
1978
1979
1980 dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1981 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1982
1983 if (retval) {
1984 DBG(dev, "binding to %s returning %d\n",
1985 driver->driver.name, retval);
1986 dev->driver = NULL;
1987 dev->gadget.dev.driver = NULL;
1988 return retval;
1989 }
1990
1991
1992 setup_ep0(dev);
1993
1994
1995 tmp = readl(&dev->regs->ctl);
1996 tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1997 writel(tmp, &dev->regs->ctl);
1998
1999 usb_connect(dev);
2000
2001 return 0;
2002}
2003EXPORT_SYMBOL(usb_gadget_register_driver);
2004
2005
2006static void
2007shutdown(struct udc *dev, struct usb_gadget_driver *driver)
2008__releases(dev->lock)
2009__acquires(dev->lock)
2010{
2011 int tmp;
2012
2013 if (dev->gadget.speed != USB_SPEED_UNKNOWN) {
2014 spin_unlock(&dev->lock);
2015 driver->disconnect(&dev->gadget);
2016 spin_lock(&dev->lock);
2017 }
2018
2019
2020 udc_basic_init(dev);
2021 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2022 empty_req_queue(&dev->ep[tmp]);
2023
2024 udc_setup_endpoints(dev);
2025}
2026
2027
2028int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
2029{
2030 struct udc *dev = udc;
2031 unsigned long flags;
2032 u32 tmp;
2033
2034 if (!dev)
2035 return -ENODEV;
2036 if (!driver || driver != dev->driver || !driver->unbind)
2037 return -EINVAL;
2038
2039 spin_lock_irqsave(&dev->lock, flags);
2040 udc_mask_unused_interrupts(dev);
2041 shutdown(dev, driver);
2042 spin_unlock_irqrestore(&dev->lock, flags);
2043
2044 driver->unbind(&dev->gadget);
2045 dev->gadget.dev.driver = NULL;
2046 dev->driver = NULL;
2047
2048
2049 tmp = readl(&dev->regs->ctl);
2050 tmp |= AMD_BIT(UDC_DEVCTL_SD);
2051 writel(tmp, &dev->regs->ctl);
2052
2053
2054 DBG(dev, "%s: unregistered\n", driver->driver.name);
2055
2056 return 0;
2057}
2058EXPORT_SYMBOL(usb_gadget_unregister_driver);
2059
2060
2061
2062static void udc_process_cnak_queue(struct udc *dev)
2063{
2064 u32 tmp;
2065 u32 reg;
2066
2067
2068 DBG(dev, "CNAK pending queue processing\n");
2069 for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2070 if (cnak_pending & (1 << tmp)) {
2071 DBG(dev, "CNAK pending for ep%d\n", tmp);
2072
2073 reg = readl(&dev->ep[tmp].regs->ctl);
2074 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2075 writel(reg, &dev->ep[tmp].regs->ctl);
2076 dev->ep[tmp].naking = 0;
2077 UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2078 }
2079 }
2080
2081 if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2082 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2083
2084 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2085 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2086 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2087 dev->ep[UDC_EP0OUT_IX].naking = 0;
2088 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2089 dev->ep[UDC_EP0OUT_IX].num);
2090 }
2091}
2092
2093
2094static void udc_ep0_set_rde(struct udc *dev)
2095{
2096 if (use_dma) {
2097
2098
2099
2100
2101 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2102 udc_set_rde(dev);
2103 } else {
2104
2105
2106
2107
2108 if (set_rde != 0 && !timer_pending(&udc_timer)) {
2109 udc_timer.expires =
2110 jiffies + HZ/UDC_RDE_TIMER_DIV;
2111 set_rde = 1;
2112 if (!stop_timer) {
2113 add_timer(&udc_timer);
2114 }
2115 }
2116 }
2117 }
2118}
2119
2120
2121
2122static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2123{
2124 irqreturn_t ret_val = IRQ_NONE;
2125 u32 tmp;
2126 struct udc_ep *ep;
2127 struct udc_request *req;
2128 unsigned int count;
2129 struct udc_data_dma *td = NULL;
2130 unsigned dma_done;
2131
2132 VDBG(dev, "ep%d irq\n", ep_ix);
2133 ep = &dev->ep[ep_ix];
2134
2135 tmp = readl(&ep->regs->sts);
2136 if (use_dma) {
2137
2138 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2139 DBG(dev, "BNA ep%dout occured - DESPTR = %x \n",
2140 ep->num, readl(&ep->regs->desptr));
2141
2142 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2143 if (!ep->cancel_transfer)
2144 ep->bna_occurred = 1;
2145 else
2146 ep->cancel_transfer = 0;
2147 ret_val = IRQ_HANDLED;
2148 goto finished;
2149 }
2150 }
2151
2152 if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2153 dev_err(&dev->pdev->dev, "HE ep%dout occured\n", ep->num);
2154
2155
2156 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2157 ret_val = IRQ_HANDLED;
2158 goto finished;
2159 }
2160
2161 if (!list_empty(&ep->queue)) {
2162
2163
2164 req = list_entry(ep->queue.next,
2165 struct udc_request, queue);
2166 } else {
2167 req = NULL;
2168 udc_rxfifo_pending = 1;
2169 }
2170 VDBG(dev, "req = %p\n", req);
2171
2172 if (!use_dma) {
2173
2174
2175 if (req && udc_rxfifo_read(ep, req)) {
2176 ret_val = IRQ_HANDLED;
2177
2178
2179 complete_req(ep, req, 0);
2180
2181 if (!list_empty(&ep->queue) && !ep->halted) {
2182 req = list_entry(ep->queue.next,
2183 struct udc_request, queue);
2184 } else
2185 req = NULL;
2186 }
2187
2188
2189 } else if (!ep->cancel_transfer && req != NULL) {
2190 ret_val = IRQ_HANDLED;
2191
2192
2193 if (!use_dma_ppb) {
2194 dma_done = AMD_GETBITS(req->td_data->status,
2195 UDC_DMA_OUT_STS_BS);
2196
2197 } else {
2198
2199
2200
2201
2202 if (ep->bna_occurred) {
2203 VDBG(dev, "Recover desc. from BNA dummy\n");
2204 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2205 sizeof(struct udc_data_dma));
2206 ep->bna_occurred = 0;
2207 udc_init_bna_dummy(ep->req);
2208 }
2209 td = udc_get_last_dma_desc(req);
2210 dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2211 }
2212 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2213
2214 if (!use_dma_ppb) {
2215
2216 count = AMD_GETBITS(req->td_data->status,
2217 UDC_DMA_OUT_STS_RXBYTES);
2218 VDBG(dev, "rx bytes=%u\n", count);
2219
2220 } else {
2221 VDBG(dev, "req->td_data=%p\n", req->td_data);
2222 VDBG(dev, "last desc = %p\n", td);
2223
2224 if (use_dma_ppb_du) {
2225
2226 count = udc_get_ppbdu_rxbytes(req);
2227 } else {
2228
2229 count = AMD_GETBITS(td->status,
2230 UDC_DMA_OUT_STS_RXBYTES);
2231 if (!count && req->req.length
2232 == UDC_DMA_MAXPACKET) {
2233
2234
2235
2236
2237 count = UDC_DMA_MAXPACKET;
2238 }
2239 }
2240 VDBG(dev, "last desc rx bytes=%u\n", count);
2241 }
2242
2243 tmp = req->req.length - req->req.actual;
2244 if (count > tmp) {
2245 if ((tmp % ep->ep.maxpacket) != 0) {
2246 DBG(dev, "%s: rx %db, space=%db\n",
2247 ep->ep.name, count, tmp);
2248 req->req.status = -EOVERFLOW;
2249 }
2250 count = tmp;
2251 }
2252 req->req.actual += count;
2253 req->dma_going = 0;
2254
2255 complete_req(ep, req, 0);
2256
2257
2258 if (!list_empty(&ep->queue) && !ep->halted) {
2259 req = list_entry(ep->queue.next,
2260 struct udc_request,
2261 queue);
2262
2263
2264
2265
2266
2267
2268 if (req->dma_going == 0) {
2269
2270 if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2271 goto finished;
2272
2273 writel(req->td_phys,
2274 &ep->regs->desptr);
2275 req->dma_going = 1;
2276
2277 udc_set_rde(dev);
2278 }
2279 } else {
2280
2281
2282
2283
2284 if (ep->bna_dummy_req) {
2285
2286 writel(ep->bna_dummy_req->td_phys,
2287 &ep->regs->desptr);
2288 ep->bna_occurred = 0;
2289 }
2290
2291
2292
2293
2294
2295
2296 if (set_rde != 0
2297 && !timer_pending(&udc_timer)) {
2298 udc_timer.expires =
2299 jiffies
2300 + HZ*UDC_RDE_TIMER_SECONDS;
2301 set_rde = 1;
2302 if (!stop_timer) {
2303 add_timer(&udc_timer);
2304 }
2305 }
2306 if (ep->num != UDC_EP0OUT_IX)
2307 dev->data_ep_queued = 0;
2308 }
2309
2310 } else {
2311
2312
2313
2314
2315 udc_set_rde(dev);
2316 }
2317
2318 } else if (ep->cancel_transfer) {
2319 ret_val = IRQ_HANDLED;
2320 ep->cancel_transfer = 0;
2321 }
2322
2323
2324 if (cnak_pending) {
2325
2326 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2327 udc_process_cnak_queue(dev);
2328 }
2329 }
2330
2331
2332 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2333finished:
2334 return ret_val;
2335}
2336
2337
2338static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2339{
2340 irqreturn_t ret_val = IRQ_NONE;
2341 u32 tmp;
2342 u32 epsts;
2343 struct udc_ep *ep;
2344 struct udc_request *req;
2345 struct udc_data_dma *td;
2346 unsigned dma_done;
2347 unsigned len;
2348
2349 ep = &dev->ep[ep_ix];
2350
2351 epsts = readl(&ep->regs->sts);
2352 if (use_dma) {
2353
2354 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2355 dev_err(&dev->pdev->dev,
2356 "BNA ep%din occured - DESPTR = %08lx \n",
2357 ep->num,
2358 (unsigned long) readl(&ep->regs->desptr));
2359
2360
2361 writel(epsts, &ep->regs->sts);
2362 ret_val = IRQ_HANDLED;
2363 goto finished;
2364 }
2365 }
2366
2367 if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2368 dev_err(&dev->pdev->dev,
2369 "HE ep%dn occured - DESPTR = %08lx \n",
2370 ep->num, (unsigned long) readl(&ep->regs->desptr));
2371
2372
2373 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2374 ret_val = IRQ_HANDLED;
2375 goto finished;
2376 }
2377
2378
2379 if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2380 VDBG(dev, "TDC set- completion\n");
2381 ret_val = IRQ_HANDLED;
2382 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2383 req = list_entry(ep->queue.next,
2384 struct udc_request, queue);
2385
2386
2387
2388
2389 if (use_dma_ppb_du) {
2390 td = udc_get_last_dma_desc(req);
2391 if (td) {
2392 dma_done =
2393 AMD_GETBITS(td->status,
2394 UDC_DMA_IN_STS_BS);
2395
2396 req->req.actual = req->req.length;
2397 }
2398 } else {
2399
2400 req->req.actual = req->req.length;
2401 }
2402
2403 if (req->req.actual == req->req.length) {
2404
2405 complete_req(ep, req, 0);
2406 req->dma_going = 0;
2407
2408 if (list_empty(&ep->queue)) {
2409
2410 tmp = readl(&dev->regs->ep_irqmsk);
2411 tmp |= AMD_BIT(ep->num);
2412 writel(tmp, &dev->regs->ep_irqmsk);
2413 }
2414 }
2415 }
2416 ep->cancel_transfer = 0;
2417
2418 }
2419
2420
2421
2422
2423 if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2424 && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2425 ret_val = IRQ_HANDLED;
2426 if (!list_empty(&ep->queue)) {
2427
2428 req = list_entry(ep->queue.next,
2429 struct udc_request, queue);
2430
2431 if (!use_dma) {
2432
2433 udc_txfifo_write(ep, &req->req);
2434 len = req->req.length - req->req.actual;
2435 if (len > ep->ep.maxpacket)
2436 len = ep->ep.maxpacket;
2437 req->req.actual += len;
2438 if (req->req.actual == req->req.length
2439 || (len != ep->ep.maxpacket)) {
2440
2441 complete_req(ep, req, 0);
2442 }
2443
2444 } else if (req && !req->dma_going) {
2445 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2446 req, req->td_data);
2447 if (req->td_data) {
2448
2449 req->dma_going = 1;
2450
2451
2452
2453
2454
2455 if (use_dma_ppb && req->req.length >
2456 ep->ep.maxpacket) {
2457 req->td_data->status &=
2458 AMD_CLEAR_BIT(
2459 UDC_DMA_IN_STS_L);
2460 }
2461
2462
2463 writel(req->td_phys, &ep->regs->desptr);
2464
2465
2466 req->td_data->status =
2467 AMD_ADDBITS(
2468 req->td_data->status,
2469 UDC_DMA_IN_STS_BS_HOST_READY,
2470 UDC_DMA_IN_STS_BS);
2471
2472
2473 tmp = readl(&ep->regs->ctl);
2474 tmp |= AMD_BIT(UDC_EPCTL_P);
2475 writel(tmp, &ep->regs->ctl);
2476 }
2477 }
2478
2479 } else if (!use_dma && ep->in) {
2480
2481 tmp = readl(
2482 &dev->regs->ep_irqmsk);
2483 tmp |= AMD_BIT(ep->num);
2484 writel(tmp,
2485 &dev->regs->ep_irqmsk);
2486 }
2487 }
2488
2489 writel(epsts, &ep->regs->sts);
2490
2491finished:
2492 return ret_val;
2493
2494}
2495
2496
2497static irqreturn_t udc_control_out_isr(struct udc *dev)
2498__releases(dev->lock)
2499__acquires(dev->lock)
2500{
2501 irqreturn_t ret_val = IRQ_NONE;
2502 u32 tmp;
2503 int setup_supported;
2504 u32 count;
2505 int set = 0;
2506 struct udc_ep *ep;
2507 struct udc_ep *ep_tmp;
2508
2509 ep = &dev->ep[UDC_EP0OUT_IX];
2510
2511
2512 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2513
2514 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2515
2516 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2517 VDBG(dev, "ep0: BNA set\n");
2518 writel(AMD_BIT(UDC_EPSTS_BNA),
2519 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2520 ep->bna_occurred = 1;
2521 ret_val = IRQ_HANDLED;
2522 goto finished;
2523 }
2524
2525
2526 tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2527 VDBG(dev, "data_typ = %x\n", tmp);
2528
2529
2530 if (tmp == UDC_EPSTS_OUT_SETUP) {
2531 ret_val = IRQ_HANDLED;
2532
2533 ep->dev->stall_ep0in = 0;
2534 dev->waiting_zlp_ack_ep0in = 0;
2535
2536
2537 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2538 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2539 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2540 dev->ep[UDC_EP0IN_IX].naking = 1;
2541
2542 if (use_dma) {
2543
2544
2545 writel(UDC_EPSTS_OUT_CLEAR,
2546 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2547
2548 setup_data.data[0] =
2549 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2550 setup_data.data[1] =
2551 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2552
2553 dev->ep[UDC_EP0OUT_IX].td_stp->status =
2554 UDC_DMA_STP_STS_BS_HOST_READY;
2555 } else {
2556
2557 udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2558 }
2559
2560
2561 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2562 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2563
2564 udc_ep0_set_rde(dev);
2565 set = 0;
2566 } else {
2567 dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2568
2569
2570
2571
2572 if (ep->bna_dummy_req) {
2573
2574 writel(ep->bna_dummy_req->td_phys,
2575 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2576 ep->bna_occurred = 0;
2577 }
2578
2579 set = 1;
2580 dev->ep[UDC_EP0OUT_IX].naking = 1;
2581
2582
2583
2584
2585 set_rde = 1;
2586 if (!timer_pending(&udc_timer)) {
2587 udc_timer.expires = jiffies +
2588 HZ/UDC_RDE_TIMER_DIV;
2589 if (!stop_timer) {
2590 add_timer(&udc_timer);
2591 }
2592 }
2593 }
2594
2595
2596
2597
2598
2599
2600
2601 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2602 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2603 DBG(dev, "MSC Reset\n");
2604
2605
2606
2607
2608 ep_tmp = &udc->ep[UDC_EPIN_IX];
2609 udc_set_halt(&ep_tmp->ep, 0);
2610 ep_tmp = &udc->ep[UDC_EPOUT_IX];
2611 udc_set_halt(&ep_tmp->ep, 0);
2612 }
2613
2614
2615 spin_unlock(&dev->lock);
2616 setup_supported = dev->driver->setup(&dev->gadget,
2617 &setup_data.request);
2618 spin_lock(&dev->lock);
2619
2620 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2621
2622 if (setup_supported >= 0 && setup_supported <
2623 UDC_EP0IN_MAXPACKET) {
2624
2625 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2626 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2627 dev->ep[UDC_EP0IN_IX].naking = 0;
2628 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2629
2630
2631 } else if (setup_supported < 0) {
2632 tmp |= AMD_BIT(UDC_EPCTL_S);
2633 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2634 } else
2635 dev->waiting_zlp_ack_ep0in = 1;
2636
2637
2638
2639 if (!set) {
2640 tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2641 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2642 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2643 dev->ep[UDC_EP0OUT_IX].naking = 0;
2644 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2645 }
2646
2647 if (!use_dma) {
2648
2649 writel(UDC_EPSTS_OUT_CLEAR,
2650 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2651 }
2652
2653
2654 } else if (tmp == UDC_EPSTS_OUT_DATA) {
2655
2656 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2657
2658
2659 if (use_dma) {
2660
2661 if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2662 VDBG(dev, "ZLP\n");
2663
2664
2665 dev->ep[UDC_EP0OUT_IX].td->status =
2666 AMD_ADDBITS(
2667 dev->ep[UDC_EP0OUT_IX].td->status,
2668 UDC_DMA_OUT_STS_BS_HOST_READY,
2669 UDC_DMA_OUT_STS_BS);
2670
2671 udc_ep0_set_rde(dev);
2672 ret_val = IRQ_HANDLED;
2673
2674 } else {
2675
2676 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2677
2678 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2679 &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2680
2681 udc_ep0_set_rde(dev);
2682 }
2683 } else {
2684
2685
2686 count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2687 count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2688
2689 count = 0;
2690
2691
2692 if (count != 0) {
2693 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2694 } else {
2695
2696 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2697 ret_val = IRQ_HANDLED;
2698 }
2699 }
2700 }
2701
2702
2703 if (cnak_pending) {
2704
2705 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
2706 udc_process_cnak_queue(dev);
2707 }
2708 }
2709
2710finished:
2711 return ret_val;
2712}
2713
2714
2715static irqreturn_t udc_control_in_isr(struct udc *dev)
2716{
2717 irqreturn_t ret_val = IRQ_NONE;
2718 u32 tmp;
2719 struct udc_ep *ep;
2720 struct udc_request *req;
2721 unsigned len;
2722
2723 ep = &dev->ep[UDC_EP0IN_IX];
2724
2725
2726 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2727
2728 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2729
2730 if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2731 VDBG(dev, "isr: TDC clear \n");
2732 ret_val = IRQ_HANDLED;
2733
2734
2735 writel(AMD_BIT(UDC_EPSTS_TDC),
2736 &dev->ep[UDC_EP0IN_IX].regs->sts);
2737
2738
2739 } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2740 ret_val = IRQ_HANDLED;
2741
2742 if (ep->dma) {
2743
2744 writel(AMD_BIT(UDC_EPSTS_IN),
2745 &dev->ep[UDC_EP0IN_IX].regs->sts);
2746 }
2747 if (dev->stall_ep0in) {
2748 DBG(dev, "stall ep0in\n");
2749
2750 tmp = readl(&ep->regs->ctl);
2751 tmp |= AMD_BIT(UDC_EPCTL_S);
2752 writel(tmp, &ep->regs->ctl);
2753 } else {
2754 if (!list_empty(&ep->queue)) {
2755
2756 req = list_entry(ep->queue.next,
2757 struct udc_request, queue);
2758
2759 if (ep->dma) {
2760
2761 writel(req->td_phys, &ep->regs->desptr);
2762
2763 req->td_data->status =
2764 AMD_ADDBITS(
2765 req->td_data->status,
2766 UDC_DMA_STP_STS_BS_HOST_READY,
2767 UDC_DMA_STP_STS_BS);
2768
2769
2770 tmp =
2771 readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2772 tmp |= AMD_BIT(UDC_EPCTL_P);
2773 writel(tmp,
2774 &dev->ep[UDC_EP0IN_IX].regs->ctl);
2775
2776
2777 req->req.actual = req->req.length;
2778
2779
2780 complete_req(ep, req, 0);
2781
2782 } else {
2783
2784 udc_txfifo_write(ep, &req->req);
2785
2786
2787 len = req->req.length - req->req.actual;
2788 if (len > ep->ep.maxpacket)
2789 len = ep->ep.maxpacket;
2790
2791 req->req.actual += len;
2792 if (req->req.actual == req->req.length
2793 || (len != ep->ep.maxpacket)) {
2794
2795 complete_req(ep, req, 0);
2796 }
2797 }
2798
2799 }
2800 }
2801 ep->halted = 0;
2802 dev->stall_ep0in = 0;
2803 if (!ep->dma) {
2804
2805 writel(AMD_BIT(UDC_EPSTS_IN),
2806 &dev->ep[UDC_EP0IN_IX].regs->sts);
2807 }
2808 }
2809
2810 return ret_val;
2811}
2812
2813
2814
2815static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2816__releases(dev->lock)
2817__acquires(dev->lock)
2818{
2819 irqreturn_t ret_val = IRQ_NONE;
2820 u32 tmp;
2821 u32 cfg;
2822 struct udc_ep *ep;
2823 u16 i;
2824 u8 udc_csr_epix;
2825
2826
2827 if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2828 ret_val = IRQ_HANDLED;
2829
2830
2831 tmp = readl(&dev->regs->sts);
2832 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2833 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2834 dev->cur_config = cfg;
2835 dev->set_cfg_not_acked = 1;
2836
2837
2838 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2839 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2840 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2841
2842
2843 for (i = 0; i < UDC_EP_NUM; i++) {
2844 ep = &dev->ep[i];
2845 if (ep->in) {
2846
2847
2848 udc_csr_epix = ep->num;
2849
2850
2851
2852 } else {
2853
2854 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2855 }
2856
2857 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2858
2859 tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2860 UDC_CSR_NE_CFG);
2861
2862 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2863
2864
2865 ep->halted = 0;
2866 tmp = readl(&ep->regs->ctl);
2867 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2868 writel(tmp, &ep->regs->ctl);
2869 }
2870
2871 spin_unlock(&dev->lock);
2872 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2873 spin_lock(&dev->lock);
2874
2875 }
2876 if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2877 ret_val = IRQ_HANDLED;
2878
2879 dev->set_cfg_not_acked = 1;
2880
2881 tmp = readl(&dev->regs->sts);
2882 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2883 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2884
2885
2886 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2887 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2888 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2889 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2890 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2891
2892 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2893 dev->cur_alt, dev->cur_intf);
2894
2895
2896 for (i = 0; i < UDC_EP_NUM; i++) {
2897 ep = &dev->ep[i];
2898 if (ep->in) {
2899
2900
2901 udc_csr_epix = ep->num;
2902
2903
2904
2905 } else {
2906
2907 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2908 }
2909
2910
2911
2912 tmp = readl(&dev->csr->ne[udc_csr_epix]);
2913
2914 tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2915 UDC_CSR_NE_INTF);
2916
2917
2918 tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2919 UDC_CSR_NE_ALT);
2920
2921 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2922
2923
2924 ep->halted = 0;
2925 tmp = readl(&ep->regs->ctl);
2926 tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2927 writel(tmp, &ep->regs->ctl);
2928 }
2929
2930
2931 spin_unlock(&dev->lock);
2932 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2933 spin_lock(&dev->lock);
2934
2935 }
2936 if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2937 DBG(dev, "USB Reset interrupt\n");
2938 ret_val = IRQ_HANDLED;
2939
2940
2941 soft_reset_occured = 0;
2942
2943 dev->waiting_zlp_ack_ep0in = 0;
2944 dev->set_cfg_not_acked = 0;
2945
2946
2947 udc_mask_unused_interrupts(dev);
2948
2949
2950 spin_unlock(&dev->lock);
2951 if (dev->sys_suspended && dev->driver->resume) {
2952 dev->driver->resume(&dev->gadget);
2953 dev->sys_suspended = 0;
2954 }
2955 dev->driver->disconnect(&dev->gadget);
2956 spin_lock(&dev->lock);
2957
2958
2959 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2960 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2961
2962
2963 tmp = readl(&dev->regs->sts);
2964 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2965 && !soft_reset_after_usbreset_occured) {
2966 udc_soft_reset(dev);
2967 soft_reset_after_usbreset_occured++;
2968 }
2969
2970
2971
2972
2973
2974
2975 DBG(dev, "DMA machine reset\n");
2976 tmp = readl(&dev->regs->cfg);
2977 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2978 writel(tmp, &dev->regs->cfg);
2979
2980
2981 udc_basic_init(dev);
2982
2983
2984 udc_enable_dev_setup_interrupts(dev);
2985
2986
2987 tmp = readl(&dev->regs->irqmsk);
2988 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2989 writel(tmp, &dev->regs->irqmsk);
2990
2991 }
2992 if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2993 DBG(dev, "USB Suspend interrupt\n");
2994 ret_val = IRQ_HANDLED;
2995 if (dev->driver->suspend) {
2996 spin_unlock(&dev->lock);
2997 dev->sys_suspended = 1;
2998 dev->driver->suspend(&dev->gadget);
2999 spin_lock(&dev->lock);
3000 }
3001 }
3002 if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
3003 DBG(dev, "ENUM interrupt\n");
3004 ret_val = IRQ_HANDLED;
3005 soft_reset_after_usbreset_occured = 0;
3006
3007
3008 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
3009 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
3010
3011
3012 udc_setup_endpoints(dev);
3013 if (dev->gadget.speed == USB_SPEED_HIGH) {
3014 dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3015 "high");
3016 } else if (dev->gadget.speed == USB_SPEED_FULL) {
3017 dev_info(&dev->pdev->dev, "Connect: speed = %s\n",
3018 "full");
3019 }
3020
3021
3022 activate_control_endpoints(dev);
3023
3024
3025 udc_enable_ep0_interrupts(dev);
3026 }
3027
3028 if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
3029 DBG(dev, "USB SVC interrupt\n");
3030 ret_val = IRQ_HANDLED;
3031
3032
3033 tmp = readl(&dev->regs->sts);
3034 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
3035
3036 tmp = readl(&dev->regs->irqmsk);
3037 tmp |= AMD_BIT(UDC_DEVINT_US);
3038 writel(tmp, &dev->regs->irqmsk);
3039 DBG(dev, "USB Disconnect (session valid low)\n");
3040
3041 usb_disconnect(udc);
3042 }
3043
3044 }
3045
3046 return ret_val;
3047}
3048
3049
3050static irqreturn_t udc_irq(int irq, void *pdev)
3051{
3052 struct udc *dev = pdev;
3053 u32 reg;
3054 u16 i;
3055 u32 ep_irq;
3056 irqreturn_t ret_val = IRQ_NONE;
3057
3058 spin_lock(&dev->lock);
3059
3060
3061 reg = readl(&dev->regs->ep_irqsts);
3062 if (reg) {
3063 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3064 ret_val |= udc_control_out_isr(dev);
3065 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3066 ret_val |= udc_control_in_isr(dev);
3067
3068
3069
3070
3071
3072 for (i = 1; i < UDC_EP_NUM; i++) {
3073 ep_irq = 1 << i;
3074 if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3075 continue;
3076
3077
3078 writel(ep_irq, &dev->regs->ep_irqsts);
3079
3080
3081 if (i > UDC_EPIN_NUM)
3082 ret_val |= udc_data_out_isr(dev, i);
3083 else
3084 ret_val |= udc_data_in_isr(dev, i);
3085 }
3086
3087 }
3088
3089
3090
3091 reg = readl(&dev->regs->irqsts);
3092 if (reg) {
3093
3094 writel(reg, &dev->regs->irqsts);
3095 ret_val |= udc_dev_isr(dev, reg);
3096 }
3097
3098
3099 spin_unlock(&dev->lock);
3100 return ret_val;
3101}
3102
3103
3104static void gadget_release(struct device *pdev)
3105{
3106 struct amd5536udc *dev = dev_get_drvdata(pdev);
3107 kfree(dev);
3108}
3109
3110
3111static void udc_remove(struct udc *dev)
3112{
3113
3114 stop_timer++;
3115 if (timer_pending(&udc_timer))
3116 wait_for_completion(&on_exit);
3117 if (udc_timer.data)
3118 del_timer_sync(&udc_timer);
3119
3120 stop_pollstall_timer++;
3121 if (timer_pending(&udc_pollstall_timer))
3122 wait_for_completion(&on_pollstall_exit);
3123 if (udc_pollstall_timer.data)
3124 del_timer_sync(&udc_pollstall_timer);
3125 udc = NULL;
3126}
3127
3128
3129static void udc_pci_remove(struct pci_dev *pdev)
3130{
3131 struct udc *dev;
3132
3133 dev = pci_get_drvdata(pdev);
3134
3135
3136 BUG_ON(dev->driver != NULL);
3137
3138
3139 if (dev->data_requests)
3140 pci_pool_destroy(dev->data_requests);
3141
3142 if (dev->stp_requests) {
3143
3144 pci_pool_free(dev->stp_requests,
3145 dev->ep[UDC_EP0OUT_IX].td_stp,
3146 dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3147 pci_pool_free(dev->stp_requests,
3148 dev->ep[UDC_EP0OUT_IX].td,
3149 dev->ep[UDC_EP0OUT_IX].td_phys);
3150
3151 pci_pool_destroy(dev->stp_requests);
3152 }
3153
3154
3155 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
3156 if (dev->irq_registered)
3157 free_irq(pdev->irq, dev);
3158 if (dev->regs)
3159 iounmap(dev->regs);
3160 if (dev->mem_region)
3161 release_mem_region(pci_resource_start(pdev, 0),
3162 pci_resource_len(pdev, 0));
3163 if (dev->active)
3164 pci_disable_device(pdev);
3165
3166 device_unregister(&dev->gadget.dev);
3167 pci_set_drvdata(pdev, NULL);
3168
3169 udc_remove(dev);
3170}
3171
3172
3173static int init_dma_pools(struct udc *dev)
3174{
3175 struct udc_stp_dma *td_stp;
3176 struct udc_data_dma *td_data;
3177 int retval;
3178
3179
3180 if (use_dma_ppb) {
3181 use_dma_bufferfill_mode = 0;
3182 } else {
3183 use_dma_ppb_du = 0;
3184 use_dma_bufferfill_mode = 1;
3185 }
3186
3187
3188 dev->data_requests = dma_pool_create("data_requests", NULL,
3189 sizeof(struct udc_data_dma), 0, 0);
3190 if (!dev->data_requests) {
3191 DBG(dev, "can't get request data pool\n");
3192 retval = -ENOMEM;
3193 goto finished;
3194 }
3195
3196
3197 dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3198
3199
3200 dev->stp_requests = dma_pool_create("setup requests", NULL,
3201 sizeof(struct udc_stp_dma), 0, 0);
3202 if (!dev->stp_requests) {
3203 DBG(dev, "can't get stp request pool\n");
3204 retval = -ENOMEM;
3205 goto finished;
3206 }
3207
3208 td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3209 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3210 if (td_stp == NULL) {
3211 retval = -ENOMEM;
3212 goto finished;
3213 }
3214 dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3215
3216
3217 td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3218 &dev->ep[UDC_EP0OUT_IX].td_phys);
3219 if (td_data == NULL) {
3220 retval = -ENOMEM;
3221 goto finished;
3222 }
3223 dev->ep[UDC_EP0OUT_IX].td = td_data;
3224 return 0;
3225
3226finished:
3227 return retval;
3228}
3229
3230
3231static int udc_pci_probe(
3232 struct pci_dev *pdev,
3233 const struct pci_device_id *id
3234)
3235{
3236 struct udc *dev;
3237 unsigned long resource;
3238 unsigned long len;
3239 int retval = 0;
3240
3241
3242 if (udc) {
3243 dev_dbg(&pdev->dev, "already probed\n");
3244 return -EBUSY;
3245 }
3246
3247
3248 dev = kzalloc(sizeof(struct udc), GFP_KERNEL);
3249 if (!dev) {
3250 retval = -ENOMEM;
3251 goto finished;
3252 }
3253
3254
3255 if (pci_enable_device(pdev) < 0) {
3256 kfree(dev);
3257 dev = NULL;
3258 retval = -ENODEV;
3259 goto finished;
3260 }
3261 dev->active = 1;
3262
3263
3264 resource = pci_resource_start(pdev, 0);
3265 len = pci_resource_len(pdev, 0);
3266
3267 if (!request_mem_region(resource, len, name)) {
3268 dev_dbg(&pdev->dev, "pci device used already\n");
3269 kfree(dev);
3270 dev = NULL;
3271 retval = -EBUSY;
3272 goto finished;
3273 }
3274 dev->mem_region = 1;
3275
3276 dev->virt_addr = ioremap_nocache(resource, len);
3277 if (dev->virt_addr == NULL) {
3278 dev_dbg(&pdev->dev, "start address cannot be mapped\n");
3279 kfree(dev);
3280 dev = NULL;
3281 retval = -EFAULT;
3282 goto finished;
3283 }
3284
3285 if (!pdev->irq) {
3286 dev_err(&dev->pdev->dev, "irq not set\n");
3287 kfree(dev);
3288 dev = NULL;
3289 retval = -ENODEV;
3290 goto finished;
3291 }
3292
3293 spin_lock_init(&dev->lock);
3294
3295 dev->csr = dev->virt_addr + UDC_CSR_ADDR;
3296
3297 dev->regs = dev->virt_addr + UDC_DEVCFG_ADDR;
3298
3299 dev->ep_regs = dev->virt_addr + UDC_EPREGS_ADDR;
3300
3301 dev->rxfifo = (u32 __iomem *)(dev->virt_addr + UDC_RXFIFO_ADDR);
3302 dev->txfifo = (u32 __iomem *)(dev->virt_addr + UDC_TXFIFO_ADDR);
3303
3304 if (request_irq(pdev->irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
3305 dev_dbg(&dev->pdev->dev, "request_irq(%d) fail\n", pdev->irq);
3306 kfree(dev);
3307 dev = NULL;
3308 retval = -EBUSY;
3309 goto finished;
3310 }
3311 dev->irq_registered = 1;
3312
3313 pci_set_drvdata(pdev, dev);
3314
3315
3316 dev->chiprev = pdev->revision;
3317
3318 pci_set_master(pdev);
3319 pci_try_set_mwi(pdev);
3320
3321
3322 if (use_dma) {
3323 retval = init_dma_pools(dev);
3324 if (retval != 0)
3325 goto finished;
3326 }
3327
3328 dev->phys_addr = resource;
3329 dev->irq = pdev->irq;
3330 dev->pdev = pdev;
3331 dev->gadget.dev.parent = &pdev->dev;
3332 dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
3333
3334
3335 if (udc_probe(dev) == 0)
3336 return 0;
3337
3338finished:
3339 if (dev)
3340 udc_pci_remove(pdev);
3341 return retval;
3342}
3343
3344
3345static int udc_probe(struct udc *dev)
3346{
3347 char tmp[128];
3348 u32 reg;
3349 int retval;
3350
3351
3352 udc_timer.data = 0;
3353 udc_pollstall_timer.data = 0;
3354
3355
3356 dev->gadget.ops = &udc_ops;
3357
3358 dev_set_name(&dev->gadget.dev, "gadget");
3359 dev->gadget.dev.release = gadget_release;
3360 dev->gadget.name = name;
3361 dev->gadget.name = name;
3362 dev->gadget.is_dualspeed = 1;
3363
3364
3365 startup_registers(dev);
3366
3367 dev_info(&dev->pdev->dev, "%s\n", mod_desc);
3368
3369 snprintf(tmp, sizeof tmp, "%d", dev->irq);
3370 dev_info(&dev->pdev->dev,
3371 "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3372 tmp, dev->phys_addr, dev->chiprev,
3373 (dev->chiprev == UDC_HSA0_REV) ? "A0" : "B1");
3374 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3375 if (dev->chiprev == UDC_HSA0_REV) {
3376 dev_err(&dev->pdev->dev, "chip revision is A0; too old\n");
3377 retval = -ENODEV;
3378 goto finished;
3379 }
3380 dev_info(&dev->pdev->dev,
3381 "driver version: %s(for Geode5536 B1)\n", tmp);
3382 udc = dev;
3383
3384 retval = device_register(&dev->gadget.dev);
3385 if (retval)
3386 goto finished;
3387
3388
3389 init_timer(&udc_timer);
3390 udc_timer.function = udc_timer_function;
3391 udc_timer.data = 1;
3392
3393 init_timer(&udc_pollstall_timer);
3394 udc_pollstall_timer.function = udc_pollstall_timer_function;
3395 udc_pollstall_timer.data = 1;
3396
3397
3398 reg = readl(&dev->regs->ctl);
3399 reg |= AMD_BIT(UDC_DEVCTL_SD);
3400 writel(reg, &dev->regs->ctl);
3401
3402
3403 print_regs(dev);
3404
3405 return 0;
3406
3407finished:
3408 return retval;
3409}
3410
3411
3412static int udc_remote_wakeup(struct udc *dev)
3413{
3414 unsigned long flags;
3415 u32 tmp;
3416
3417 DBG(dev, "UDC initiates remote wakeup\n");
3418
3419 spin_lock_irqsave(&dev->lock, flags);
3420
3421 tmp = readl(&dev->regs->ctl);
3422 tmp |= AMD_BIT(UDC_DEVCTL_RES);
3423 writel(tmp, &dev->regs->ctl);
3424 tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
3425 writel(tmp, &dev->regs->ctl);
3426
3427 spin_unlock_irqrestore(&dev->lock, flags);
3428 return 0;
3429}
3430
3431
3432static const struct pci_device_id pci_id[] = {
3433 {
3434 PCI_DEVICE(PCI_VENDOR_ID_AMD, 0x2096),
3435 .class = (PCI_CLASS_SERIAL_USB << 8) | 0xfe,
3436 .class_mask = 0xffffffff,
3437 },
3438 {},
3439};
3440MODULE_DEVICE_TABLE(pci, pci_id);
3441
3442
3443static struct pci_driver udc_pci_driver = {
3444 .name = (char *) name,
3445 .id_table = pci_id,
3446 .probe = udc_pci_probe,
3447 .remove = udc_pci_remove,
3448};
3449
3450
3451static int __init init(void)
3452{
3453 return pci_register_driver(&udc_pci_driver);
3454}
3455module_init(init);
3456
3457
3458static void __exit cleanup(void)
3459{
3460 pci_unregister_driver(&udc_pci_driver);
3461}
3462module_exit(cleanup);
3463
3464MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3465MODULE_AUTHOR("Thomas Dahlmann");
3466MODULE_LICENSE("GPL");
3467
3468
