LXR linux/drivers/usb/gadget/ci13xxx

   1/*
   2 * ci13xxx_udc.h - structures, registers, and macros MIPS USB IP core
   3 *
   4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
   5 *
   6 * Author: David Lopo
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 *
  12 * Description: MIPS USB IP core family device controller
  13 *              Structures, registers and logging macros
  14 */
  15
  16#ifndef _CI13XXX_h_
  17#define _CI13XXX_h_
  18
  19/******************************************************************************
  20 * DEFINE
  21 *****************************************************************************/
  22#define ENDPT_MAX          (16)
  23#define CTRL_PAYLOAD_MAX   (64)
  24#define RX        (0)  /* similar to USB_DIR_OUT but can be used as an index */
  25#define TX        (1)  /* similar to USB_DIR_IN  but can be used as an index */
  26
  27/******************************************************************************
  28 * STRUCTURES
  29 *****************************************************************************/
  30/* DMA layout of transfer descriptors */
  31struct ci13xxx_td {
  32        /* 0 */
  33        u32 next;
  34#define TD_TERMINATE          BIT(0)
  35        /* 1 */
  36        u32 token;
  37#define TD_STATUS             (0x00FFUL <<  0)
  38#define TD_STATUS_TR_ERR      BIT(3)
  39#define TD_STATUS_DT_ERR      BIT(5)
  40#define TD_STATUS_HALTED      BIT(6)
  41#define TD_STATUS_ACTIVE      BIT(7)
  42#define TD_MULTO              (0x0003UL << 10)
  43#define TD_IOC                BIT(15)
  44#define TD_TOTAL_BYTES        (0x7FFFUL << 16)
  45        /* 2 */
  46        u32 page[5];
  47#define TD_CURR_OFFSET        (0x0FFFUL <<  0)
  48#define TD_FRAME_NUM          (0x07FFUL <<  0)
  49#define TD_RESERVED_MASK      (0x0FFFUL <<  0)
  50} __attribute__ ((packed));
  51
  52/* DMA layout of queue heads */
  53struct ci13xxx_qh {
  54        /* 0 */
  55        u32 cap;
  56#define QH_IOS                BIT(15)
  57#define QH_MAX_PKT            (0x07FFUL << 16)
  58#define QH_ZLT                BIT(29)
  59#define QH_MULT               (0x0003UL << 30)
  60        /* 1 */
  61        u32 curr;
  62        /* 2 - 8 */
  63        struct ci13xxx_td        td;
  64        /* 9 */
  65        u32 RESERVED;
  66        struct usb_ctrlrequest   setup;
  67} __attribute__ ((packed));
  68
  69/* Extension of usb_request */
  70struct ci13xxx_req {
  71        struct usb_request   req;
  72        unsigned             map;
  73        struct list_head     queue;
  74        struct ci13xxx_td   *ptr;
  75        dma_addr_t           dma;
  76};
  77
  78/* Extension of usb_ep */
  79struct ci13xxx_ep {
  80        struct usb_ep                          ep;
  81        const struct usb_endpoint_descriptor  *desc;
  82        u8                                     dir;
  83        u8                                     num;
  84        u8                                     type;
  85        char                                   name[16];
  86        struct {
  87                struct list_head   queue;
  88                struct ci13xxx_qh *ptr;
  89                dma_addr_t         dma;
  90        }                                      qh[2];
  91        struct usb_request                    *status;
  92        int                                    wedge;
  93
  94        /* global resources */
  95        spinlock_t                            *lock;
  96        struct device                         *device;
  97        struct dma_pool                       *td_pool;
  98};
  99
 100/* CI13XXX UDC descriptor & global resources */
 101struct ci13xxx {
 102        spinlock_t                *lock;      /* ctrl register bank access */
 103
 104        struct dma_pool           *qh_pool;   /* DMA pool for queue heads */
 105        struct dma_pool           *td_pool;   /* DMA pool for transfer descs */
 106
 107        struct usb_gadget          gadget;     /* USB slave device */
 108        struct ci13xxx_ep          ci13xxx_ep[ENDPT_MAX]; /* extended endpts */
 109
 110        struct usb_gadget_driver  *driver;     /* 3rd party gadget driver */
 111};
 112
 113/******************************************************************************
 114 * REGISTERS
 115 *****************************************************************************/
 116/* register size */
 117#define REG_BITS   (32)
 118
 119/* HCCPARAMS */
 120#define HCCPARAMS_LEN         BIT(17)
 121
 122/* DCCPARAMS */
 123#define DCCPARAMS_DEN         (0x1F << 0)
 124#define DCCPARAMS_DC          BIT(7)
 125
 126/* TESTMODE */
 127#define TESTMODE_FORCE        BIT(0)
 128
 129/* USBCMD */
 130#define USBCMD_RS             BIT(0)
 131#define USBCMD_RST            BIT(1)
 132#define USBCMD_SUTW           BIT(13)
 133
 134/* USBSTS & USBINTR */
 135#define USBi_UI               BIT(0)
 136#define USBi_UEI              BIT(1)
 137#define USBi_PCI              BIT(2)
 138#define USBi_URI              BIT(6)
 139#define USBi_SLI              BIT(8)
 140
 141/* DEVICEADDR */
 142#define DEVICEADDR_USBADRA    BIT(24)
 143#define DEVICEADDR_USBADR     (0x7FUL << 25)
 144
 145/* PORTSC */
 146#define PORTSC_SUSP           BIT(7)
 147#define PORTSC_HSP            BIT(9)
 148#define PORTSC_PTC            (0x0FUL << 16)
 149
 150/* DEVLC */
 151#define DEVLC_PSPD            (0x03UL << 25)
 152#define    DEVLC_PSPD_HS      (0x02UL << 25)
 153
 154/* USBMODE */
 155#define USBMODE_CM            (0x03UL <<  0)
 156#define    USBMODE_CM_IDLE    (0x00UL <<  0)
 157#define    USBMODE_CM_DEVICE  (0x02UL <<  0)
 158#define    USBMODE_CM_HOST    (0x03UL <<  0)
 159#define USBMODE_SLOM          BIT(3)
 160
 161/* ENDPTCTRL */
 162#define ENDPTCTRL_RXS         BIT(0)
 163#define ENDPTCTRL_RXT         (0x03UL <<  2)
 164#define ENDPTCTRL_RXR         BIT(6)         /* reserved for port 0 */
 165#define ENDPTCTRL_RXE         BIT(7)
 166#define ENDPTCTRL_TXS         BIT(16)
 167#define ENDPTCTRL_TXT         (0x03UL << 18)
 168#define ENDPTCTRL_TXR         BIT(22)        /* reserved for port 0 */
 169#define ENDPTCTRL_TXE         BIT(23)
 170
 171/******************************************************************************
 172 * LOGGING
 173 *****************************************************************************/
 174#define ci13xxx_printk(level, format, args...) \
 175do { \
 176        if (_udc == NULL) \
 177                printk(level "[%s] " format "\n", __func__, ## args); \
 178        else \
 179                dev_printk(level, _udc->gadget.dev.parent, \
 180                           "[%s] " format "\n", __func__, ## args); \
 181} while (0)
 182
 183#define err(format, args...)    ci13xxx_printk(KERN_ERR, format, ## args)
 184#define warn(format, args...)   ci13xxx_printk(KERN_WARNING, format, ## args)
 185#define info(format, args...)   ci13xxx_printk(KERN_INFO, format, ## args)
 186
 187#ifdef TRACE
 188#define trace(format, args...)      ci13xxx_printk(KERN_DEBUG, format, ## args)
 189#define dbg_trace(format, args...)  dev_dbg(dev, format, ##args)
 190#else
 191#define trace(format, args...)      do {} while (0)
 192#define dbg_trace(format, args...)  do {} while (0)
 193#endif
 194
 195#endif  /* _CI13XXX_h_ */
 196