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23#include <linux/module.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/io.h>
27#include <linux/platform_device.h>
28#include <linux/err.h>
29#include <linux/usb/ch9.h>
30#include <linux/usb/gadget.h>
31
32#include "m66592-udc.h"
33
34MODULE_DESCRIPTION("M66592 USB gadget driver");
35MODULE_LICENSE("GPL");
36MODULE_AUTHOR("Yoshihiro Shimoda");
37MODULE_ALIAS("platform:m66592_udc");
38
39#define DRIVER_VERSION "21 July 2009"
40
41static const char udc_name[] = "m66592_udc";
42static const char *m66592_ep_name[] = {
43 "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
44};
45
46static void disable_controller(struct m66592 *m66592);
47static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
48static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
49static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
50 gfp_t gfp_flags);
51
52static void transfer_complete(struct m66592_ep *ep,
53 struct m66592_request *req, int status);
54
55
56static inline u16 get_usb_speed(struct m66592 *m66592)
57{
58 return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
59}
60
61static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
62 unsigned long reg)
63{
64 u16 tmp;
65
66 tmp = m66592_read(m66592, M66592_INTENB0);
67 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
68 M66592_INTENB0);
69 m66592_bset(m66592, (1 << pipenum), reg);
70 m66592_write(m66592, tmp, M66592_INTENB0);
71}
72
73static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
74 unsigned long reg)
75{
76 u16 tmp;
77
78 tmp = m66592_read(m66592, M66592_INTENB0);
79 m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
80 M66592_INTENB0);
81 m66592_bclr(m66592, (1 << pipenum), reg);
82 m66592_write(m66592, tmp, M66592_INTENB0);
83}
84
85static void m66592_usb_connect(struct m66592 *m66592)
86{
87 m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
88 m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
89 M66592_INTENB0);
90 m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
91
92 m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
93}
94
95static void m66592_usb_disconnect(struct m66592 *m66592)
96__releases(m66592->lock)
97__acquires(m66592->lock)
98{
99 m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
100 m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
101 M66592_INTENB0);
102 m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
103 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
104
105 m66592->gadget.speed = USB_SPEED_UNKNOWN;
106 spin_unlock(&m66592->lock);
107 m66592->driver->disconnect(&m66592->gadget);
108 spin_lock(&m66592->lock);
109
110 disable_controller(m66592);
111 INIT_LIST_HEAD(&m66592->ep[0].queue);
112}
113
114static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
115{
116 u16 pid = 0;
117 unsigned long offset;
118
119 if (pipenum == 0)
120 pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
121 else if (pipenum < M66592_MAX_NUM_PIPE) {
122 offset = get_pipectr_addr(pipenum);
123 pid = m66592_read(m66592, offset) & M66592_PID;
124 } else
125 pr_err("unexpect pipe num (%d)\n", pipenum);
126
127 return pid;
128}
129
130static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
131 u16 pid)
132{
133 unsigned long offset;
134
135 if (pipenum == 0)
136 m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
137 else if (pipenum < M66592_MAX_NUM_PIPE) {
138 offset = get_pipectr_addr(pipenum);
139 m66592_mdfy(m66592, pid, M66592_PID, offset);
140 } else
141 pr_err("unexpect pipe num (%d)\n", pipenum);
142}
143
144static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
145{
146 control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
147}
148
149static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
150{
151 control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
152}
153
154static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
155{
156 control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
157}
158
159static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
160{
161 u16 ret = 0;
162 unsigned long offset;
163
164 if (pipenum == 0)
165 ret = m66592_read(m66592, M66592_DCPCTR);
166 else if (pipenum < M66592_MAX_NUM_PIPE) {
167 offset = get_pipectr_addr(pipenum);
168 ret = m66592_read(m66592, offset);
169 } else
170 pr_err("unexpect pipe num (%d)\n", pipenum);
171
172 return ret;
173}
174
175static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
176{
177 unsigned long offset;
178
179 pipe_stop(m66592, pipenum);
180
181 if (pipenum == 0)
182 m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
183 else if (pipenum < M66592_MAX_NUM_PIPE) {
184 offset = get_pipectr_addr(pipenum);
185 m66592_bset(m66592, M66592_SQCLR, offset);
186 } else
187 pr_err("unexpect pipe num(%d)\n", pipenum);
188}
189
190static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
191{
192 u16 tmp;
193 int size;
194
195 if (pipenum == 0) {
196 tmp = m66592_read(m66592, M66592_DCPCFG);
197 if ((tmp & M66592_CNTMD) != 0)
198 size = 256;
199 else {
200 tmp = m66592_read(m66592, M66592_DCPMAXP);
201 size = tmp & M66592_MAXP;
202 }
203 } else {
204 m66592_write(m66592, pipenum, M66592_PIPESEL);
205 tmp = m66592_read(m66592, M66592_PIPECFG);
206 if ((tmp & M66592_CNTMD) != 0) {
207 tmp = m66592_read(m66592, M66592_PIPEBUF);
208 size = ((tmp >> 10) + 1) * 64;
209 } else {
210 tmp = m66592_read(m66592, M66592_PIPEMAXP);
211 size = tmp & M66592_MXPS;
212 }
213 }
214
215 return size;
216}
217
218static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
219{
220 struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
221 unsigned short mbw;
222
223 if (ep->use_dma)
224 return;
225
226 m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
227
228 ndelay(450);
229
230 if (m66592->pdata->on_chip)
231 mbw = M66592_MBW_32;
232 else
233 mbw = M66592_MBW_16;
234
235 m66592_bset(m66592, mbw, ep->fifosel);
236}
237
238static int pipe_buffer_setting(struct m66592 *m66592,
239 struct m66592_pipe_info *info)
240{
241 u16 bufnum = 0, buf_bsize = 0;
242 u16 pipecfg = 0;
243
244 if (info->pipe == 0)
245 return -EINVAL;
246
247 m66592_write(m66592, info->pipe, M66592_PIPESEL);
248
249 if (info->dir_in)
250 pipecfg |= M66592_DIR;
251 pipecfg |= info->type;
252 pipecfg |= info->epnum;
253 switch (info->type) {
254 case M66592_INT:
255 bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
256 buf_bsize = 0;
257 break;
258 case M66592_BULK:
259
260 if (info->pipe > M66592_BASE_PIPENUM_BULK)
261 bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
262 else
263 bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
264
265 bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
266 buf_bsize = 7;
267 pipecfg |= M66592_DBLB;
268 if (!info->dir_in)
269 pipecfg |= M66592_SHTNAK;
270 break;
271 case M66592_ISO:
272 bufnum = M66592_BASE_BUFNUM +
273 (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
274 buf_bsize = 7;
275 break;
276 }
277
278 if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
279 pr_err("m66592 pipe memory is insufficient\n");
280 return -ENOMEM;
281 }
282
283 m66592_write(m66592, pipecfg, M66592_PIPECFG);
284 m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
285 m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
286 if (info->interval)
287 info->interval--;
288 m66592_write(m66592, info->interval, M66592_PIPEPERI);
289
290 return 0;
291}
292
293static void pipe_buffer_release(struct m66592 *m66592,
294 struct m66592_pipe_info *info)
295{
296 if (info->pipe == 0)
297 return;
298
299 if (is_bulk_pipe(info->pipe)) {
300 m66592->bulk--;
301 } else if (is_interrupt_pipe(info->pipe))
302 m66592->interrupt--;
303 else if (is_isoc_pipe(info->pipe)) {
304 m66592->isochronous--;
305 if (info->type == M66592_BULK)
306 m66592->bulk--;
307 } else
308 pr_err("ep_release: unexpect pipenum (%d)\n",
309 info->pipe);
310}
311
312static void pipe_initialize(struct m66592_ep *ep)
313{
314 struct m66592 *m66592 = ep->m66592;
315 unsigned short mbw;
316
317 m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
318
319 m66592_write(m66592, M66592_ACLRM, ep->pipectr);
320 m66592_write(m66592, 0, ep->pipectr);
321 m66592_write(m66592, M66592_SQCLR, ep->pipectr);
322 if (ep->use_dma) {
323 m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
324
325 ndelay(450);
326
327 if (m66592->pdata->on_chip)
328 mbw = M66592_MBW_32;
329 else
330 mbw = M66592_MBW_16;
331
332 m66592_bset(m66592, mbw, ep->fifosel);
333 }
334}
335
336static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
337 const struct usb_endpoint_descriptor *desc,
338 u16 pipenum, int dma)
339{
340 if ((pipenum != 0) && dma) {
341 if (m66592->num_dma == 0) {
342 m66592->num_dma++;
343 ep->use_dma = 1;
344 ep->fifoaddr = M66592_D0FIFO;
345 ep->fifosel = M66592_D0FIFOSEL;
346 ep->fifoctr = M66592_D0FIFOCTR;
347 ep->fifotrn = M66592_D0FIFOTRN;
348 } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
349 m66592->num_dma++;
350 ep->use_dma = 1;
351 ep->fifoaddr = M66592_D1FIFO;
352 ep->fifosel = M66592_D1FIFOSEL;
353 ep->fifoctr = M66592_D1FIFOCTR;
354 ep->fifotrn = M66592_D1FIFOTRN;
355 } else {
356 ep->use_dma = 0;
357 ep->fifoaddr = M66592_CFIFO;
358 ep->fifosel = M66592_CFIFOSEL;
359 ep->fifoctr = M66592_CFIFOCTR;
360 ep->fifotrn = 0;
361 }
362 } else {
363 ep->use_dma = 0;
364 ep->fifoaddr = M66592_CFIFO;
365 ep->fifosel = M66592_CFIFOSEL;
366 ep->fifoctr = M66592_CFIFOCTR;
367 ep->fifotrn = 0;
368 }
369
370 ep->pipectr = get_pipectr_addr(pipenum);
371 ep->pipenum = pipenum;
372 ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
373 m66592->pipenum2ep[pipenum] = ep;
374 m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
375 INIT_LIST_HEAD(&ep->queue);
376}
377
378static void m66592_ep_release(struct m66592_ep *ep)
379{
380 struct m66592 *m66592 = ep->m66592;
381 u16 pipenum = ep->pipenum;
382
383 if (pipenum == 0)
384 return;
385
386 if (ep->use_dma)
387 m66592->num_dma--;
388 ep->pipenum = 0;
389 ep->busy = 0;
390 ep->use_dma = 0;
391}
392
393static int alloc_pipe_config(struct m66592_ep *ep,
394 const struct usb_endpoint_descriptor *desc)
395{
396 struct m66592 *m66592 = ep->m66592;
397 struct m66592_pipe_info info;
398 int dma = 0;
399 int *counter;
400 int ret;
401
402 ep->desc = desc;
403
404 BUG_ON(ep->pipenum);
405
406 switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
407 case USB_ENDPOINT_XFER_BULK:
408 if (m66592->bulk >= M66592_MAX_NUM_BULK) {
409 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
410 pr_err("bulk pipe is insufficient\n");
411 return -ENODEV;
412 } else {
413 info.pipe = M66592_BASE_PIPENUM_ISOC
414 + m66592->isochronous;
415 counter = &m66592->isochronous;
416 }
417 } else {
418 info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
419 counter = &m66592->bulk;
420 }
421 info.type = M66592_BULK;
422 dma = 1;
423 break;
424 case USB_ENDPOINT_XFER_INT:
425 if (m66592->interrupt >= M66592_MAX_NUM_INT) {
426 pr_err("interrupt pipe is insufficient\n");
427 return -ENODEV;
428 }
429 info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
430 info.type = M66592_INT;
431 counter = &m66592->interrupt;
432 break;
433 case USB_ENDPOINT_XFER_ISOC:
434 if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
435 pr_err("isochronous pipe is insufficient\n");
436 return -ENODEV;
437 }
438 info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
439 info.type = M66592_ISO;
440 counter = &m66592->isochronous;
441 break;
442 default:
443 pr_err("unexpect xfer type\n");
444 return -EINVAL;
445 }
446 ep->type = info.type;
447
448 info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
449 info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
450 info.interval = desc->bInterval;
451 if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
452 info.dir_in = 1;
453 else
454 info.dir_in = 0;
455
456 ret = pipe_buffer_setting(m66592, &info);
457 if (ret < 0) {
458 pr_err("pipe_buffer_setting fail\n");
459 return ret;
460 }
461
462 (*counter)++;
463 if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
464 m66592->bulk++;
465
466 m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
467 pipe_initialize(ep);
468
469 return 0;
470}
471
472static int free_pipe_config(struct m66592_ep *ep)
473{
474 struct m66592 *m66592 = ep->m66592;
475 struct m66592_pipe_info info;
476
477 info.pipe = ep->pipenum;
478 info.type = ep->type;
479 pipe_buffer_release(m66592, &info);
480 m66592_ep_release(ep);
481
482 return 0;
483}
484
485
486static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
487{
488 enable_irq_ready(m66592, pipenum);
489 enable_irq_nrdy(m66592, pipenum);
490}
491
492static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
493{
494 disable_irq_ready(m66592, pipenum);
495 disable_irq_nrdy(m66592, pipenum);
496}
497
498
499static void control_end(struct m66592 *m66592, unsigned ccpl)
500{
501 m66592->ep[0].internal_ccpl = ccpl;
502 pipe_start(m66592, 0);
503 m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
504}
505
506static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
507{
508 struct m66592 *m66592 = ep->m66592;
509
510 pipe_change(m66592, ep->pipenum);
511 m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
512 (M66592_ISEL | M66592_CURPIPE),
513 M66592_CFIFOSEL);
514 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
515 if (req->req.length == 0) {
516 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
517 pipe_start(m66592, 0);
518 transfer_complete(ep, req, 0);
519 } else {
520 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
521 irq_ep0_write(ep, req);
522 }
523}
524
525static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
526{
527 struct m66592 *m66592 = ep->m66592;
528 u16 tmp;
529
530 pipe_change(m66592, ep->pipenum);
531 disable_irq_empty(m66592, ep->pipenum);
532 pipe_start(m66592, ep->pipenum);
533
534 tmp = m66592_read(m66592, ep->fifoctr);
535 if (unlikely((tmp & M66592_FRDY) == 0))
536 pipe_irq_enable(m66592, ep->pipenum);
537 else
538 irq_packet_write(ep, req);
539}
540
541static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
542{
543 struct m66592 *m66592 = ep->m66592;
544 u16 pipenum = ep->pipenum;
545
546 if (ep->pipenum == 0) {
547 m66592_mdfy(m66592, M66592_PIPE0,
548 (M66592_ISEL | M66592_CURPIPE),
549 M66592_CFIFOSEL);
550 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
551 pipe_start(m66592, pipenum);
552 pipe_irq_enable(m66592, pipenum);
553 } else {
554 if (ep->use_dma) {
555 m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
556 pipe_change(m66592, pipenum);
557 m66592_bset(m66592, M66592_TRENB, ep->fifosel);
558 m66592_write(m66592,
559 (req->req.length + ep->ep.maxpacket - 1)
560 / ep->ep.maxpacket,
561 ep->fifotrn);
562 }
563 pipe_start(m66592, pipenum);
564 pipe_irq_enable(m66592, pipenum);
565 }
566}
567
568static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
569{
570 if (ep->desc->bEndpointAddress & USB_DIR_IN)
571 start_packet_write(ep, req);
572 else
573 start_packet_read(ep, req);
574}
575
576static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
577{
578 u16 ctsq;
579
580 ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
581
582 switch (ctsq) {
583 case M66592_CS_RDDS:
584 start_ep0_write(ep, req);
585 break;
586 case M66592_CS_WRDS:
587 start_packet_read(ep, req);
588 break;
589
590 case M66592_CS_WRND:
591 control_end(ep->m66592, 0);
592 break;
593 default:
594 pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
595 break;
596 }
597}
598
599static void init_controller(struct m66592 *m66592)
600{
601 unsigned int endian;
602
603 if (m66592->pdata->on_chip) {
604 if (m66592->pdata->endian)
605 endian = 0;
606 else
607 endian = M66592_LITTLE;
608
609 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG);
610 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
611 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
612 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
613
614
615 m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
616 m66592_bset(m66592, 0x1000, M66592_TESTMODE);
617 m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
618
619 m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
620
621 m66592_write(m66592, 0, M66592_CFBCFG);
622 m66592_write(m66592, 0, M66592_D0FBCFG);
623 m66592_bset(m66592, endian, M66592_CFBCFG);
624 m66592_bset(m66592, endian, M66592_D0FBCFG);
625 } else {
626 unsigned int clock, vif, irq_sense;
627
628 if (m66592->pdata->endian)
629 endian = M66592_BIGEND;
630 else
631 endian = 0;
632
633 if (m66592->pdata->vif)
634 vif = M66592_LDRV;
635 else
636 vif = 0;
637
638 switch (m66592->pdata->xtal) {
639 case M66592_PLATDATA_XTAL_12MHZ:
640 clock = M66592_XTAL12;
641 break;
642 case M66592_PLATDATA_XTAL_24MHZ:
643 clock = M66592_XTAL24;
644 break;
645 case M66592_PLATDATA_XTAL_48MHZ:
646 clock = M66592_XTAL48;
647 break;
648 default:
649 pr_warning("m66592-udc: xtal configuration error\n");
650 clock = 0;
651 }
652
653 switch (m66592->irq_trigger) {
654 case IRQF_TRIGGER_LOW:
655 irq_sense = M66592_INTL;
656 break;
657 case IRQF_TRIGGER_FALLING:
658 irq_sense = 0;
659 break;
660 default:
661 pr_warning("m66592-udc: irq trigger config error\n");
662 irq_sense = 0;
663 }
664
665 m66592_bset(m66592,
666 (vif & M66592_LDRV) | (endian & M66592_BIGEND),
667 M66592_PINCFG);
668 m66592_bset(m66592, M66592_HSE, M66592_SYSCFG);
669 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
670 M66592_SYSCFG);
671 m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
672 m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
673 m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
674
675 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
676
677 msleep(3);
678
679 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
680
681 msleep(1);
682
683 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
684
685 m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
686 m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
687 M66592_DMA0CFG);
688 }
689}
690
691static void disable_controller(struct m66592 *m66592)
692{
693 if (!m66592->pdata->on_chip) {
694 m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
695 udelay(1);
696 m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
697 udelay(1);
698 m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
699 udelay(1);
700 m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
701 }
702}
703
704static void m66592_start_xclock(struct m66592 *m66592)
705{
706 u16 tmp;
707
708 if (!m66592->pdata->on_chip) {
709 tmp = m66592_read(m66592, M66592_SYSCFG);
710 if (!(tmp & M66592_XCKE))
711 m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
712 }
713}
714
715
716static void transfer_complete(struct m66592_ep *ep,
717 struct m66592_request *req, int status)
718__releases(m66592->lock)
719__acquires(m66592->lock)
720{
721 int restart = 0;
722
723 if (unlikely(ep->pipenum == 0)) {
724 if (ep->internal_ccpl) {
725 ep->internal_ccpl = 0;
726 return;
727 }
728 }
729
730 list_del_init(&req->queue);
731 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
732 req->req.status = -ESHUTDOWN;
733 else
734 req->req.status = status;
735
736 if (!list_empty(&ep->queue))
737 restart = 1;
738
739 spin_unlock(&ep->m66592->lock);
740 req->req.complete(&ep->ep, &req->req);
741 spin_lock(&ep->m66592->lock);
742
743 if (restart) {
744 req = list_entry(ep->queue.next, struct m66592_request, queue);
745 if (ep->desc)
746 start_packet(ep, req);
747 }
748}
749
750static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
751{
752 int i;
753 u16 tmp;
754 unsigned bufsize;
755 size_t size;
756 void *buf;
757 u16 pipenum = ep->pipenum;
758 struct m66592 *m66592 = ep->m66592;
759
760 pipe_change(m66592, pipenum);
761 m66592_bset(m66592, M66592_ISEL, ep->fifosel);
762
763 i = 0;
764 do {
765 tmp = m66592_read(m66592, ep->fifoctr);
766 if (i++ > 100000) {
767 pr_err("pipe0 is busy. maybe cpu i/o bus "
768 "conflict. please power off this controller.");
769 return;
770 }
771 ndelay(1);
772 } while ((tmp & M66592_FRDY) == 0);
773
774
775 bufsize = get_buffer_size(m66592, pipenum);
776 buf = req->req.buf + req->req.actual;
777 size = min(bufsize, req->req.length - req->req.actual);
778
779
780 if (req->req.buf) {
781 if (size > 0)
782 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
783 if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
784 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
785 }
786
787
788 req->req.actual += size;
789
790
791 if ((!req->req.zero && (req->req.actual == req->req.length))
792 || (size % ep->ep.maxpacket)
793 || (size == 0)) {
794 disable_irq_ready(m66592, pipenum);
795 disable_irq_empty(m66592, pipenum);
796 } else {
797 disable_irq_ready(m66592, pipenum);
798 enable_irq_empty(m66592, pipenum);
799 }
800 pipe_start(m66592, pipenum);
801}
802
803static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
804{
805 u16 tmp;
806 unsigned bufsize;
807 size_t size;
808 void *buf;
809 u16 pipenum = ep->pipenum;
810 struct m66592 *m66592 = ep->m66592;
811
812 pipe_change(m66592, pipenum);
813 tmp = m66592_read(m66592, ep->fifoctr);
814 if (unlikely((tmp & M66592_FRDY) == 0)) {
815 pipe_stop(m66592, pipenum);
816 pipe_irq_disable(m66592, pipenum);
817 pr_err("write fifo not ready. pipnum=%d\n", pipenum);
818 return;
819 }
820
821
822 bufsize = get_buffer_size(m66592, pipenum);
823 buf = req->req.buf + req->req.actual;
824 size = min(bufsize, req->req.length - req->req.actual);
825
826
827 if (req->req.buf) {
828 m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
829 if ((size == 0)
830 || ((size % ep->ep.maxpacket) != 0)
831 || ((bufsize != ep->ep.maxpacket)
832 && (bufsize > size)))
833 m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
834 }
835
836
837 req->req.actual += size;
838
839 if ((!req->req.zero && (req->req.actual == req->req.length))
840 || (size % ep->ep.maxpacket)
841 || (size == 0)) {
842 disable_irq_ready(m66592, pipenum);
843 enable_irq_empty(m66592, pipenum);
844 } else {
845 disable_irq_empty(m66592, pipenum);
846 pipe_irq_enable(m66592, pipenum);
847 }
848}
849
850static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
851{
852 u16 tmp;
853 int rcv_len, bufsize, req_len;
854 int size;
855 void *buf;
856 u16 pipenum = ep->pipenum;
857 struct m66592 *m66592 = ep->m66592;
858 int finish = 0;
859
860 pipe_change(m66592, pipenum);
861 tmp = m66592_read(m66592, ep->fifoctr);
862 if (unlikely((tmp & M66592_FRDY) == 0)) {
863 req->req.status = -EPIPE;
864 pipe_stop(m66592, pipenum);
865 pipe_irq_disable(m66592, pipenum);
866 pr_err("read fifo not ready");
867 return;
868 }
869
870
871 rcv_len = tmp & M66592_DTLN;
872 bufsize = get_buffer_size(m66592, pipenum);
873
874 buf = req->req.buf + req->req.actual;
875 req_len = req->req.length - req->req.actual;
876 if (rcv_len < bufsize)
877 size = min(rcv_len, req_len);
878 else
879 size = min(bufsize, req_len);
880
881
882 req->req.actual += size;
883
884
885 if ((!req->req.zero && (req->req.actual == req->req.length))
886 || (size % ep->ep.maxpacket)
887 || (size == 0)) {
888 pipe_stop(m66592, pipenum);
889 pipe_irq_disable(m66592, pipenum);
890 finish = 1;
891 }
892
893
894 if (req->req.buf) {
895 if (size == 0)
896 m66592_write(m66592, M66592_BCLR, ep->fifoctr);
897 else
898 m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
899 }
900
901 if ((ep->pipenum != 0) && finish)
902 transfer_complete(ep, req, 0);
903}
904
905static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
906{
907 u16 check;
908 u16 pipenum;
909 struct m66592_ep *ep;
910 struct m66592_request *req;
911
912 if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
913 m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
914 m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
915 M66592_CFIFOSEL);
916
917 ep = &m66592->ep[0];
918 req = list_entry(ep->queue.next, struct m66592_request, queue);
919 irq_packet_read(ep, req);
920 } else {
921 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
922 check = 1 << pipenum;
923 if ((status & check) && (enb & check)) {
924 m66592_write(m66592, ~check, M66592_BRDYSTS);
925 ep = m66592->pipenum2ep[pipenum];
926 req = list_entry(ep->queue.next,
927 struct m66592_request, queue);
928 if (ep->desc->bEndpointAddress & USB_DIR_IN)
929 irq_packet_write(ep, req);
930 else
931 irq_packet_read(ep, req);
932 }
933 }
934 }
935}
936
937static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
938{
939 u16 tmp;
940 u16 check;
941 u16 pipenum;
942 struct m66592_ep *ep;
943 struct m66592_request *req;
944
945 if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
946 m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
947
948 ep = &m66592->ep[0];
949 req = list_entry(ep->queue.next, struct m66592_request, queue);
950 irq_ep0_write(ep, req);
951 } else {
952 for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
953 check = 1 << pipenum;
954 if ((status & check) && (enb & check)) {
955 m66592_write(m66592, ~check, M66592_BEMPSTS);
956 tmp = control_reg_get(m66592, pipenum);
957 if ((tmp & M66592_INBUFM) == 0) {
958 disable_irq_empty(m66592, pipenum);
959 pipe_irq_disable(m66592, pipenum);
960 pipe_stop(m66592, pipenum);
961 ep = m66592->pipenum2ep[pipenum];
962 req = list_entry(ep->queue.next,
963 struct m66592_request,
964 queue);
965 if (!list_empty(&ep->queue))
966 transfer_complete(ep, req, 0);
967 }
968 }
969 }
970 }
971}
972
973static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
974__releases(m66592->lock)
975__acquires(m66592->lock)
976{
977 struct m66592_ep *ep;
978 u16 pid;
979 u16 status = 0;
980 u16 w_index = le16_to_cpu(ctrl->wIndex);
981
982 switch (ctrl->bRequestType & USB_RECIP_MASK) {
983 case USB_RECIP_DEVICE:
984 status = 1 << USB_DEVICE_SELF_POWERED;
985 break;
986 case USB_RECIP_INTERFACE:
987 status = 0;
988 break;
989 case USB_RECIP_ENDPOINT:
990 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
991 pid = control_reg_get_pid(m66592, ep->pipenum);
992 if (pid == M66592_PID_STALL)
993 status = 1 << USB_ENDPOINT_HALT;
994 else
995 status = 0;
996 break;
997 default:
998 pipe_stall(m66592, 0);
999 return;
1000 }
1001
1002 m66592->ep0_data = cpu_to_le16(status);
1003 m66592->ep0_req->buf = &m66592->ep0_data;
1004 m66592->ep0_req->length = 2;
1005
1006 spin_unlock(&m66592->lock);
1007 m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
1008 spin_lock(&m66592->lock);
1009}
1010
1011static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1012{
1013 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1014 case USB_RECIP_DEVICE:
1015 control_end(m66592, 1);
1016 break;
1017 case USB_RECIP_INTERFACE:
1018 control_end(m66592, 1);
1019 break;
1020 case USB_RECIP_ENDPOINT: {
1021 struct m66592_ep *ep;
1022 struct m66592_request *req;
1023 u16 w_index = le16_to_cpu(ctrl->wIndex);
1024
1025 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1026 pipe_stop(m66592, ep->pipenum);
1027 control_reg_sqclr(m66592, ep->pipenum);
1028
1029 control_end(m66592, 1);
1030
1031 req = list_entry(ep->queue.next,
1032 struct m66592_request, queue);
1033 if (ep->busy) {
1034 ep->busy = 0;
1035 if (list_empty(&ep->queue))
1036 break;
1037 start_packet(ep, req);
1038 } else if (!list_empty(&ep->queue))
1039 pipe_start(m66592, ep->pipenum);
1040 }
1041 break;
1042 default:
1043 pipe_stall(m66592, 0);
1044 break;
1045 }
1046}
1047
1048static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1049{
1050
1051 switch (ctrl->bRequestType & USB_RECIP_MASK) {
1052 case USB_RECIP_DEVICE:
1053 control_end(m66592, 1);
1054 break;
1055 case USB_RECIP_INTERFACE:
1056 control_end(m66592, 1);
1057 break;
1058 case USB_RECIP_ENDPOINT: {
1059 struct m66592_ep *ep;
1060 u16 w_index = le16_to_cpu(ctrl->wIndex);
1061
1062 ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
1063 pipe_stall(m66592, ep->pipenum);
1064
1065 control_end(m66592, 1);
1066 }
1067 break;
1068 default:
1069 pipe_stall(m66592, 0);
1070 break;
1071 }
1072}
1073
1074
1075static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
1076{
1077 u16 *p = (u16 *)ctrl;
1078 unsigned long offset = M66592_USBREQ;
1079 int i, ret = 0;
1080
1081
1082 m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
1083
1084 for (i = 0; i < 4; i++)
1085 p[i] = m66592_read(m66592, offset + i*2);
1086
1087
1088 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1089 switch (ctrl->bRequest) {
1090 case USB_REQ_GET_STATUS:
1091 get_status(m66592, ctrl);
1092 break;
1093 case USB_REQ_CLEAR_FEATURE:
1094 clear_feature(m66592, ctrl);
1095 break;
1096 case USB_REQ_SET_FEATURE:
1097 set_feature(m66592, ctrl);
1098 break;
1099 default:
1100 ret = 1;
1101 break;
1102 }
1103 } else
1104 ret = 1;
1105 return ret;
1106}
1107
1108static void m66592_update_usb_speed(struct m66592 *m66592)
1109{
1110 u16 speed = get_usb_speed(m66592);
1111
1112 switch (speed) {
1113 case M66592_HSMODE:
1114 m66592->gadget.speed = USB_SPEED_HIGH;
1115 break;
1116 case M66592_FSMODE:
1117 m66592->gadget.speed = USB_SPEED_FULL;
1118 break;
1119 default:
1120 m66592->gadget.speed = USB_SPEED_UNKNOWN;
1121 pr_err("USB speed unknown\n");
1122 }
1123}
1124
1125static void irq_device_state(struct m66592 *m66592)
1126{
1127 u16 dvsq;
1128
1129 dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
1130 m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
1131
1132 if (dvsq == M66592_DS_DFLT) {
1133 m66592->driver->disconnect(&m66592->gadget);
1134 m66592_update_usb_speed(m66592);
1135 }
1136 if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
1137 m66592_update_usb_speed(m66592);
1138 if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
1139 && m66592->gadget.speed == USB_SPEED_UNKNOWN)
1140 m66592_update_usb_speed(m66592);
1141
1142 m66592->old_dvsq = dvsq;
1143}
1144
1145static void irq_control_stage(struct m66592 *m66592)
1146__releases(m66592->lock)
1147__acquires(m66592->lock)
1148{
1149 struct usb_ctrlrequest ctrl;
1150 u16 ctsq;
1151
1152 ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
1153 m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
1154
1155 switch (ctsq) {
1156 case M66592_CS_IDST: {
1157 struct m66592_ep *ep;
1158 struct m66592_request *req;
1159 ep = &m66592->ep[0];
1160 req = list_entry(ep->queue.next, struct m66592_request, queue);
1161 transfer_complete(ep, req, 0);
1162 }
1163 break;
1164
1165 case M66592_CS_RDDS:
1166 case M66592_CS_WRDS:
1167 case M66592_CS_WRND:
1168 if (setup_packet(m66592, &ctrl)) {
1169 spin_unlock(&m66592->lock);
1170 if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
1171 pipe_stall(m66592, 0);
1172 spin_lock(&m66592->lock);
1173 }
1174 break;
1175 case M66592_CS_RDSS:
1176 case M66592_CS_WRSS:
1177 control_end(m66592, 0);
1178 break;
1179 default:
1180 pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
1181 break;
1182 }
1183}
1184
1185static irqreturn_t m66592_irq(int irq, void *_m66592)
1186{
1187 struct m66592 *m66592 = _m66592;
1188 u16 intsts0;
1189 u16 intenb0;
1190 u16 brdysts, nrdysts, bempsts;
1191 u16 brdyenb, nrdyenb, bempenb;
1192 u16 savepipe;
1193 u16 mask0;
1194
1195 spin_lock(&m66592->lock);
1196
1197 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1198 intenb0 = m66592_read(m66592, M66592_INTENB0);
1199
1200 if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
1201
1202
1203
1204
1205
1206 m66592_start_xclock(m66592);
1207 intsts0 = m66592_read(m66592, M66592_INTSTS0);
1208 intenb0 = m66592_read(m66592, M66592_INTENB0);
1209 }
1210
1211 savepipe = m66592_read(m66592, M66592_CFIFOSEL);
1212
1213 mask0 = intsts0 & intenb0;
1214 if (mask0) {
1215 brdysts = m66592_read(m66592, M66592_BRDYSTS);
1216 nrdysts = m66592_read(m66592, M66592_NRDYSTS);
1217 bempsts = m66592_read(m66592, M66592_BEMPSTS);
1218 brdyenb = m66592_read(m66592, M66592_BRDYENB);
1219 nrdyenb = m66592_read(m66592, M66592_NRDYENB);
1220 bempenb = m66592_read(m66592, M66592_BEMPENB);
1221
1222 if (mask0 & M66592_VBINT) {
1223 m66592_write(m66592, 0xffff & ~M66592_VBINT,
1224 M66592_INTSTS0);
1225 m66592_start_xclock(m66592);
1226
1227
1228 m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
1229 & M66592_VBSTS;
1230 m66592->scount = M66592_MAX_SAMPLING;
1231
1232 mod_timer(&m66592->timer,
1233 jiffies + msecs_to_jiffies(50));
1234 }
1235 if (intsts0 & M66592_DVSQ)
1236 irq_device_state(m66592);
1237
1238 if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
1239 && (brdysts & brdyenb)) {
1240 irq_pipe_ready(m66592, brdysts, brdyenb);
1241 }
1242 if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
1243 && (bempsts & bempenb)) {
1244 irq_pipe_empty(m66592, bempsts, bempenb);
1245 }
1246
1247 if (intsts0 & M66592_CTRT)
1248 irq_control_stage(m66592);
1249 }
1250
1251 m66592_write(m66592, savepipe, M66592_CFIFOSEL);
1252
1253 spin_unlock(&m66592->lock);
1254 return IRQ_HANDLED;
1255}
1256
1257static void m66592_timer(unsigned long _m66592)
1258{
1259 struct m66592 *m66592 = (struct m66592 *)_m66592;
1260 unsigned long flags;
1261 u16 tmp;
1262
1263 spin_lock_irqsave(&m66592->lock, flags);
1264 tmp = m66592_read(m66592, M66592_SYSCFG);
1265 if (!(tmp & M66592_RCKE)) {
1266 m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
1267 udelay(10);
1268 m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
1269 }
1270 if (m66592->scount > 0) {
1271 tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
1272 if (tmp == m66592->old_vbus) {
1273 m66592->scount--;
1274 if (m66592->scount == 0) {
1275 if (tmp == M66592_VBSTS)
1276 m66592_usb_connect(m66592);
1277 else
1278 m66592_usb_disconnect(m66592);
1279 } else {
1280 mod_timer(&m66592->timer,
1281 jiffies + msecs_to_jiffies(50));
1282 }
1283 } else {
1284 m66592->scount = M66592_MAX_SAMPLING;
1285 m66592->old_vbus = tmp;
1286 mod_timer(&m66592->timer,
1287 jiffies + msecs_to_jiffies(50));
1288 }
1289 }
1290 spin_unlock_irqrestore(&m66592->lock, flags);
1291}
1292
1293
1294static int m66592_enable(struct usb_ep *_ep,
1295 const struct usb_endpoint_descriptor *desc)
1296{
1297 struct m66592_ep *ep;
1298
1299 ep = container_of(_ep, struct m66592_ep, ep);
1300 return alloc_pipe_config(ep, desc);
1301}
1302
1303static int m66592_disable(struct usb_ep *_ep)
1304{
1305 struct m66592_ep *ep;
1306 struct m66592_request *req;
1307 unsigned long flags;
1308
1309 ep = container_of(_ep, struct m66592_ep, ep);
1310 BUG_ON(!ep);
1311
1312 while (!list_empty(&ep->queue)) {
1313 req = list_entry(ep->queue.next, struct m66592_request, queue);
1314 spin_lock_irqsave(&ep->m66592->lock, flags);
1315 transfer_complete(ep, req, -ECONNRESET);
1316 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1317 }
1318
1319 pipe_irq_disable(ep->m66592, ep->pipenum);
1320 return free_pipe_config(ep);
1321}
1322
1323static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
1324 gfp_t gfp_flags)
1325{
1326 struct m66592_request *req;
1327
1328 req = kzalloc(sizeof(struct m66592_request), gfp_flags);
1329 if (!req)
1330 return NULL;
1331
1332 INIT_LIST_HEAD(&req->queue);
1333
1334 return &req->req;
1335}
1336
1337static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
1338{
1339 struct m66592_request *req;
1340
1341 req = container_of(_req, struct m66592_request, req);
1342 kfree(req);
1343}
1344
1345static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
1346 gfp_t gfp_flags)
1347{
1348 struct m66592_ep *ep;
1349 struct m66592_request *req;
1350 unsigned long flags;
1351 int request = 0;
1352
1353 ep = container_of(_ep, struct m66592_ep, ep);
1354 req = container_of(_req, struct m66592_request, req);
1355
1356 if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
1357 return -ESHUTDOWN;
1358
1359 spin_lock_irqsave(&ep->m66592->lock, flags);
1360
1361 if (list_empty(&ep->queue))
1362 request = 1;
1363
1364 list_add_tail(&req->queue, &ep->queue);
1365 req->req.actual = 0;
1366 req->req.status = -EINPROGRESS;
1367
1368 if (ep->desc == NULL)
1369 start_ep0(ep, req);
1370 else {
1371 if (request && !ep->busy)
1372 start_packet(ep, req);
1373 }
1374
1375 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1376
1377 return 0;
1378}
1379
1380static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1381{
1382 struct m66592_ep *ep;
1383 struct m66592_request *req;
1384 unsigned long flags;
1385
1386 ep = container_of(_ep, struct m66592_ep, ep);
1387 req = container_of(_req, struct m66592_request, req);
1388
1389 spin_lock_irqsave(&ep->m66592->lock, flags);
1390 if (!list_empty(&ep->queue))
1391 transfer_complete(ep, req, -ECONNRESET);
1392 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1393
1394 return 0;
1395}
1396
1397static int m66592_set_halt(struct usb_ep *_ep, int value)
1398{
1399 struct m66592_ep *ep;
1400 struct m66592_request *req;
1401 unsigned long flags;
1402 int ret = 0;
1403
1404 ep = container_of(_ep, struct m66592_ep, ep);
1405 req = list_entry(ep->queue.next, struct m66592_request, queue);
1406
1407 spin_lock_irqsave(&ep->m66592->lock, flags);
1408 if (!list_empty(&ep->queue)) {
1409 ret = -EAGAIN;
1410 goto out;
1411 }
1412 if (value) {
1413 ep->busy = 1;
1414 pipe_stall(ep->m66592, ep->pipenum);
1415 } else {
1416 ep->busy = 0;
1417 pipe_stop(ep->m66592, ep->pipenum);
1418 }
1419
1420out:
1421 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1422 return ret;
1423}
1424
1425static void m66592_fifo_flush(struct usb_ep *_ep)
1426{
1427 struct m66592_ep *ep;
1428 unsigned long flags;
1429
1430 ep = container_of(_ep, struct m66592_ep, ep);
1431 spin_lock_irqsave(&ep->m66592->lock, flags);
1432 if (list_empty(&ep->queue) && !ep->busy) {
1433 pipe_stop(ep->m66592, ep->pipenum);
1434 m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
1435 }
1436 spin_unlock_irqrestore(&ep->m66592->lock, flags);
1437}
1438
1439static struct usb_ep_ops m66592_ep_ops = {
1440 .enable = m66592_enable,
1441 .disable = m66592_disable,
1442
1443 .alloc_request = m66592_alloc_request,
1444 .free_request = m66592_free_request,
1445
1446 .queue = m66592_queue,
1447 .dequeue = m66592_dequeue,
1448
1449 .set_halt = m66592_set_halt,
1450 .fifo_flush = m66592_fifo_flush,
1451};
1452
1453
1454static struct m66592 *the_controller;
1455
1456int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1457{
1458 struct m66592 *m66592 = the_controller;
1459 int retval;
1460
1461 if (!driver
1462 || driver->speed != USB_SPEED_HIGH
1463 || !driver->bind
1464 || !driver->setup)
1465 return -EINVAL;
1466 if (!m66592)
1467 return -ENODEV;
1468 if (m66592->driver)
1469 return -EBUSY;
1470
1471
1472 driver->driver.bus = NULL;
1473 m66592->driver = driver;
1474 m66592->gadget.dev.driver = &driver->driver;
1475
1476 retval = device_add(&m66592->gadget.dev);
1477 if (retval) {
1478 pr_err("device_add error (%d)\n", retval);
1479 goto error;
1480 }
1481
1482 retval = driver->bind (&m66592->gadget);
1483 if (retval) {
1484 pr_err("bind to driver error (%d)\n", retval);
1485 device_del(&m66592->gadget.dev);
1486 goto error;
1487 }
1488
1489 m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1490 if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
1491 m66592_start_xclock(m66592);
1492
1493 m66592->old_vbus = m66592_read(m66592,
1494 M66592_INTSTS0) & M66592_VBSTS;
1495 m66592->scount = M66592_MAX_SAMPLING;
1496 mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
1497 }
1498
1499 return 0;
1500
1501error:
1502 m66592->driver = NULL;
1503 m66592->gadget.dev.driver = NULL;
1504
1505 return retval;
1506}
1507EXPORT_SYMBOL(usb_gadget_register_driver);
1508
1509int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1510{
1511 struct m66592 *m66592 = the_controller;
1512 unsigned long flags;
1513
1514 if (driver != m66592->driver || !driver->unbind)
1515 return -EINVAL;
1516
1517 spin_lock_irqsave(&m66592->lock, flags);
1518 if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
1519 m66592_usb_disconnect(m66592);
1520 spin_unlock_irqrestore(&m66592->lock, flags);
1521
1522 m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
1523
1524 driver->unbind(&m66592->gadget);
1525 m66592->gadget.dev.driver = NULL;
1526
1527 init_controller(m66592);
1528 disable_controller(m66592);
1529
1530 device_del(&m66592->gadget.dev);
1531 m66592->driver = NULL;
1532 return 0;
1533}
1534EXPORT_SYMBOL(usb_gadget_unregister_driver);
1535
1536
1537static int m66592_get_frame(struct usb_gadget *_gadget)
1538{
1539 struct m66592 *m66592 = gadget_to_m66592(_gadget);
1540 return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
1541}
1542
1543static struct usb_gadget_ops m66592_gadget_ops = {
1544 .get_frame = m66592_get_frame,
1545};
1546
1547static int __exit m66592_remove(struct platform_device *pdev)
1548{
1549 struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
1550
1551 del_timer_sync(&m66592->timer);
1552 iounmap(m66592->reg);
1553 free_irq(platform_get_irq(pdev, 0), m66592);
1554 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1555#ifdef CONFIG_HAVE_CLK
1556 if (m66592->pdata->on_chip) {
1557 clk_disable(m66592->clk);
1558 clk_put(m66592->clk);
1559 }
1560#endif
1561 kfree(m66592);
1562 return 0;
1563}
1564
1565static void nop_completion(struct usb_ep *ep, struct usb_request *r)
1566{
1567}
1568
1569static int __init m66592_probe(struct platform_device *pdev)
1570{
1571 struct resource *res, *ires;
1572 void __iomem *reg = NULL;
1573 struct m66592 *m66592 = NULL;
1574#ifdef CONFIG_HAVE_CLK
1575 char clk_name[8];
1576#endif
1577 int ret = 0;
1578 int i;
1579
1580 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1581 if (!res) {
1582 ret = -ENODEV;
1583 pr_err("platform_get_resource error.\n");
1584 goto clean_up;
1585 }
1586
1587 ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1588 if (!ires) {
1589 ret = -ENODEV;
1590 dev_err(&pdev->dev,
1591 "platform_get_resource IORESOURCE_IRQ error.\n");
1592 goto clean_up;
1593 }
1594
1595 reg = ioremap(res->start, resource_size(res));
1596 if (reg == NULL) {
1597 ret = -ENOMEM;
1598 pr_err("ioremap error.\n");
1599 goto clean_up;
1600 }
1601
1602 if (pdev->dev.platform_data == NULL) {
1603 dev_err(&pdev->dev, "no platform data\n");
1604 ret = -ENODEV;
1605 goto clean_up;
1606 }
1607
1608
1609 m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
1610 if (m66592 == NULL) {
1611 pr_err("kzalloc error\n");
1612 goto clean_up;
1613 }
1614
1615 m66592->pdata = pdev->dev.platform_data;
1616 m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
1617
1618 spin_lock_init(&m66592->lock);
1619 dev_set_drvdata(&pdev->dev, m66592);
1620
1621 m66592->gadget.ops = &m66592_gadget_ops;
1622 device_initialize(&m66592->gadget.dev);
1623 dev_set_name(&m66592->gadget.dev, "gadget");
1624 m66592->gadget.is_dualspeed = 1;
1625 m66592->gadget.dev.parent = &pdev->dev;
1626 m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
1627 m66592->gadget.dev.release = pdev->dev.release;
1628 m66592->gadget.name = udc_name;
1629
1630 init_timer(&m66592->timer);
1631 m66592->timer.function = m66592_timer;
1632 m66592->timer.data = (unsigned long)m66592;
1633 m66592->reg = reg;
1634
1635 ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
1636 udc_name, m66592);
1637 if (ret < 0) {
1638 pr_err("request_irq error (%d)\n", ret);
1639 goto clean_up;
1640 }
1641
1642#ifdef CONFIG_HAVE_CLK
1643 if (m66592->pdata->on_chip) {
1644 snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
1645 m66592->clk = clk_get(&pdev->dev, clk_name);
1646 if (IS_ERR(m66592->clk)) {
1647 dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
1648 clk_name);
1649 ret = PTR_ERR(m66592->clk);
1650 goto clean_up2;
1651 }
1652 clk_enable(m66592->clk);
1653 }
1654#endif
1655 INIT_LIST_HEAD(&m66592->gadget.ep_list);
1656 m66592->gadget.ep0 = &m66592->ep[0].ep;
1657 INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
1658 for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
1659 struct m66592_ep *ep = &m66592->ep[i];
1660
1661 if (i != 0) {
1662 INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
1663 list_add_tail(&m66592->ep[i].ep.ep_list,
1664 &m66592->gadget.ep_list);
1665 }
1666 ep->m66592 = m66592;
1667 INIT_LIST_HEAD(&ep->queue);
1668 ep->ep.name = m66592_ep_name[i];
1669 ep->ep.ops = &m66592_ep_ops;
1670 ep->ep.maxpacket = 512;
1671 }
1672 m66592->ep[0].ep.maxpacket = 64;
1673 m66592->ep[0].pipenum = 0;
1674 m66592->ep[0].fifoaddr = M66592_CFIFO;
1675 m66592->ep[0].fifosel = M66592_CFIFOSEL;
1676 m66592->ep[0].fifoctr = M66592_CFIFOCTR;
1677 m66592->ep[0].fifotrn = 0;
1678 m66592->ep[0].pipectr = get_pipectr_addr(0);
1679 m66592->pipenum2ep[0] = &m66592->ep[0];
1680 m66592->epaddr2ep[0] = &m66592->ep[0];
1681
1682 the_controller = m66592;
1683
1684 m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
1685 if (m66592->ep0_req == NULL)
1686 goto clean_up3;
1687 m66592->ep0_req->complete = nop_completion;
1688
1689 init_controller(m66592);
1690
1691 dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
1692 return 0;
1693
1694clean_up3:
1695#ifdef CONFIG_HAVE_CLK
1696 if (m66592->pdata->on_chip) {
1697 clk_disable(m66592->clk);
1698 clk_put(m66592->clk);
1699 }
1700clean_up2:
1701#endif
1702 free_irq(ires->start, m66592);
1703clean_up:
1704 if (m66592) {
1705 if (m66592->ep0_req)
1706 m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
1707 kfree(m66592);
1708 }
1709 if (reg)
1710 iounmap(reg);
1711
1712 return ret;
1713}
1714
1715
1716static struct platform_driver m66592_driver = {
1717 .remove = __exit_p(m66592_remove),
1718 .driver = {
1719 .name = (char *) udc_name,
1720 .owner = THIS_MODULE,
1721 },
1722};
1723
1724static int __init m66592_udc_init(void)
1725{
1726 return platform_driver_probe(&m66592_driver, m66592_probe);
1727}
1728module_init(m66592_udc_init);
1729
1730static void __exit m66592_udc_cleanup(void)
1731{
1732 platform_driver_unregister(&m66592_driver);
1733}
1734module_exit(m66592_udc_cleanup);
1735
