LXR linux/drivers/usb/gadget/pxa27x

   1/*
   2 * linux/drivers/usb/gadget/pxa27x_udc.h
   3 * Intel PXA27x on-chip full speed USB device controller
   4 *
   5 * Inspired by original driver by Frank Becker, David Brownell, and others.
   6 * Copyright (C) 2008 Robert Jarzmik
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23#ifndef __LINUX_USB_GADGET_PXA27X_H
  24#define __LINUX_USB_GADGET_PXA27X_H
  25
  26#include <linux/types.h>
  27#include <linux/spinlock.h>
  28#include <linux/io.h>
  29#include <linux/usb/otg.h>
  30
  31/*
  32 * Register definitions
  33 */
  34/* Offsets */
  35#define UDCCR           0x0000          /* UDC Control Register */
  36#define UDCICR0         0x0004          /* UDC Interrupt Control Register0 */
  37#define UDCICR1         0x0008          /* UDC Interrupt Control Register1 */
  38#define UDCISR0         0x000C          /* UDC Interrupt Status Register 0 */
  39#define UDCISR1         0x0010          /* UDC Interrupt Status Register 1 */
  40#define UDCFNR          0x0014          /* UDC Frame Number Register */
  41#define UDCOTGICR       0x0018          /* UDC On-The-Go interrupt control */
  42#define UP2OCR          0x0020          /* USB Port 2 Output Control register */
  43#define UP3OCR          0x0024          /* USB Port 3 Output Control register */
  44#define UDCCSRn(x)      (0x0100 + ((x)<<2)) /* UDC Control/Status register */
  45#define UDCBCRn(x)      (0x0200 + ((x)<<2)) /* UDC Byte Count Register */
  46#define UDCDRn(x)       (0x0300 + ((x)<<2)) /* UDC Data Register  */
  47#define UDCCRn(x)       (0x0400 + ((x)<<2)) /* UDC Control Register */
  48
  49#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
  50#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
  51                                           Protocol Port Support */
  52#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
  53                                           Support */
  54#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
  55                                           Enable */
  56#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
  57#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
  58#define UDCCR_ACN_S     11
  59#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
  60#define UDCCR_AIN_S     8
  61#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
  62                                           Setting Number */
  63#define UDCCR_AAISN_S   5
  64#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
  65                                           Configuration */
  66#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
  67                                           Error */
  68#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
  69#define UDCCR_UDA       (1 << 1)        /* UDC Active */
  70#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
  71
  72#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
  73#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
  74#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
  75#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
  76#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
  77#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
  78#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
  79#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
  80#define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
  81
  82#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
  83#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
  84#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
  85#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
  86#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
  87#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
  88#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
  89
  90#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
  91#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
  92                                           Rising Edge Interrupt Enable */
  93#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
  94                                           Falling Edge Interrupt Enable */
  95#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
  96                                           Interrupt Enable */
  97#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
  98                                           Interrupt Enable */
  99#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
 100                                           Interrupt Enable */
 101#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
 102                                           Interrupt Enable */
 103#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
 104                                           Interrupt Enable */
 105#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
 106                                           Interrupt Enable */
 107#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
 108                                           Edge Interrupt Enable */
 109#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
 110                                           Edge Interrupt Enable */
 111#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
 112                                           Interrupt Enable */
 113#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
 114                                           Interrupt Enable */
 115
 116/* Host Port 2 field bits */
 117#define UP2OCR_CPVEN    (1 << 0)        /* Charge Pump Vbus Enable */
 118#define UP2OCR_CPVPE    (1 << 1)        /* Charge Pump Vbus Pulse Enable */
 119                                        /* Transceiver enablers */
 120#define UP2OCR_DPPDE    (1 << 2)        /*   D+ Pull Down Enable */
 121#define UP2OCR_DMPDE    (1 << 3)        /*   D- Pull Down Enable */
 122#define UP2OCR_DPPUE    (1 << 4)        /*   D+ Pull Up Enable */
 123#define UP2OCR_DMPUE    (1 << 5)        /*   D- Pull Up Enable */
 124#define UP2OCR_DPPUBE   (1 << 6)        /*   D+ Pull Up Bypass Enable */
 125#define UP2OCR_DMPUBE   (1 << 7)        /*   D- Pull Up Bypass Enable */
 126#define UP2OCR_EXSP     (1 << 8)        /* External Transceiver Speed Control */
 127#define UP2OCR_EXSUS    (1 << 9)        /* External Transceiver Speed Enable */
 128#define UP2OCR_IDON     (1 << 10)       /* OTG ID Read Enable */
 129#define UP2OCR_HXS      (1 << 16)       /* Transceiver Output Select */
 130#define UP2OCR_HXOE     (1 << 17)       /* Transceiver Output Enable */
 131#define UP2OCR_SEOS     (1 << 24)       /* Single-Ended Output Select */
 132
 133#define UDCCSR0_ACM     (1 << 9)        /* Ack Control Mode */
 134#define UDCCSR0_AREN    (1 << 8)        /* Ack Response Enable */
 135#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
 136#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
 137#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
 138#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
 139#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
 140#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
 141#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
 142#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
 143
 144#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
 145#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
 146#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
 147#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
 148#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
 149#define UDCCSR_FST      (1 << 5)        /* Force STALL */
 150#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
 151#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
 152#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
 153#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
 154#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
 155
 156#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
 157#define UDCCONR_CN_S    25
 158#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
 159#define UDCCONR_IN_S    22
 160#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
 161#define UDCCONR_AISN_S  19
 162#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
 163#define UDCCONR_EN_S    15
 164#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
 165#define UDCCONR_ET_S    13
 166#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
 167#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
 168#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
 169#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
 170#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
 171#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
 172#define UDCCONR_MPS_S   2
 173#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
 174#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
 175
 176#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)
 177#define UDCCSR_WR_MASK  (UDCCSR_DME | UDCCSR_FST)
 178#define UDC_FNR_MASK    (0x7ff)
 179#define UDC_BCR_MASK    (0x3ff)
 180
 181/*
 182 * UDCCR = UDC Endpoint Configuration Registers
 183 * UDCCSR = UDC Control/Status Register for this EP
 184 * UDCBCR = UDC Byte Count Remaining (contents of OUT fifo)
 185 * UDCDR = UDC Endpoint Data Register (the fifo)
 186 */
 187#define ofs_UDCCR(ep)   (UDCCRn(ep->idx))
 188#define ofs_UDCCSR(ep)  (UDCCSRn(ep->idx))
 189#define ofs_UDCBCR(ep)  (UDCBCRn(ep->idx))
 190#define ofs_UDCDR(ep)   (UDCDRn(ep->idx))
 191
 192/* Register access macros */
 193#define udc_ep_readl(ep, reg)   \
 194        __raw_readl((ep)->dev->regs + ofs_##reg(ep))
 195#define udc_ep_writel(ep, reg, value)   \
 196        __raw_writel((value), ep->dev->regs + ofs_##reg(ep))
 197#define udc_ep_readb(ep, reg)   \
 198        __raw_readb((ep)->dev->regs + ofs_##reg(ep))
 199#define udc_ep_writeb(ep, reg, value)   \
 200        __raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
 201#define udc_readl(dev, reg)     \
 202        __raw_readl((dev)->regs + (reg))
 203#define udc_writel(udc, reg, value)     \
 204        __raw_writel((value), (udc)->regs + (reg))
 205
 206#define UDCCSR_MASK             (UDCCSR_FST | UDCCSR_DME)
 207#define UDCCISR0_EP_MASK        ~0
 208#define UDCCISR1_EP_MASK        0xffff
 209#define UDCCSR0_CTRL_REQ_MASK   (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)
 210
 211#define EPIDX(ep)       (ep->idx)
 212#define EPADDR(ep)      (ep->addr)
 213#define EPXFERTYPE(ep)  (ep->type)
 214#define EPNAME(ep)      (ep->name)
 215#define is_ep0(ep)      (!ep->idx)
 216#define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)
 217
 218/*
 219 * Endpoint definitions
 220 *
 221 * Once enabled, pxa endpoint configuration is freezed, and cannot change
 222 * unless a reset happens or the udc is disabled.
 223 * Therefore, we must define all pxa potential endpoint definitions needed for
 224 * all gadget and set them up before the udc is enabled.
 225 *
 226 * As the architecture chosen is fully static, meaning the pxa endpoint
 227 * configurations are set up once and for all, we must provide a way to match
 228 * one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget
 229 * layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt)
 230 * criteria, while the pxa architecture requires that.
 231 *
 232 * The solution is to define several pxa endpoints matching one usb_ep. Ex:
 233 *   - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when
 234 *     the udc talks on (config=3, interface=0, alt=0)
 235 *   - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when
 236 *     the udc talks on (config=3, interface=0, alt=1)
 237 *   - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when
 238 *     the udc talks on (config=2, interface=0, alt=0)
 239 *
 240 * We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...)
 241 */
 242
 243/*
 244 * Endpoint definition helpers
 245 */
 246#define USB_EP_DEF(addr, bname, dir, type, maxpkt) \
 247{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \
 248  .desc = {     .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
 249                .bmAttributes = type, \
 250                .wMaxPacketSize = maxpkt, }, \
 251  .dev = &memory \
 252}
 253#define USB_EP_BULK(addr, bname, dir) \
 254  USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)
 255#define USB_EP_ISO(addr, bname, dir) \
 256  USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)
 257#define USB_EP_INT(addr, bname, dir) \
 258  USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)
 259#define USB_EP_IN_BULK(n)       USB_EP_BULK(n, "ep" #n "in-bulk", 1)
 260#define USB_EP_OUT_BULK(n)      USB_EP_BULK(n, "ep" #n "out-bulk", 0)
 261#define USB_EP_IN_ISO(n)        USB_EP_ISO(n,  "ep" #n "in-iso", 1)
 262#define USB_EP_OUT_ISO(n)       USB_EP_ISO(n,  "ep" #n "out-iso", 0)
 263#define USB_EP_IN_INT(n)        USB_EP_INT(n,  "ep" #n "in-int", 1)
 264#define USB_EP_CTRL             USB_EP_DEF(0,  "ep0", 0, 0, EP0_FIFO_SIZE)
 265
 266#define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \
 267{ \
 268        .dev = &memory, \
 269        .name = "ep" #_idx, \
 270        .idx = _idx, .enabled = 0, \
 271        .dir_in = dir, .addr = _addr, \
 272        .config = _config, .interface = iface, .alternate = altset, \
 273        .type = _type, .fifo_size = maxpkt, \
 274}
 275#define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \
 276  PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
 277                config, iface, alt)
 278#define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \
 279  PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
 280                config, iface, alt)
 281#define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \
 282  PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
 283                config, iface, alt)
 284#define PXA_EP_IN_BULK(i, adr, c, f, a)         PXA_EP_BULK(i, adr, 1, c, f, a)
 285#define PXA_EP_OUT_BULK(i, adr, c, f, a)        PXA_EP_BULK(i, adr, 0, c, f, a)
 286#define PXA_EP_IN_ISO(i, adr, c, f, a)          PXA_EP_ISO(i, adr, 1, c, f, a)
 287#define PXA_EP_OUT_ISO(i, adr, c, f, a)         PXA_EP_ISO(i, adr, 0, c, f, a)
 288#define PXA_EP_IN_INT(i, adr, c, f, a)          PXA_EP_INT(i, adr, 1, c, f, a)
 289#define PXA_EP_CTRL     PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)
 290
 291struct pxa27x_udc;
 292
 293struct stats {
 294        unsigned long in_ops;
 295        unsigned long out_ops;
 296        unsigned long in_bytes;
 297        unsigned long out_bytes;
 298        unsigned long irqs;
 299};
 300
 301/**
 302 * struct udc_usb_ep - container of each usb_ep structure
 303 * @usb_ep: usb endpoint
 304 * @desc: usb descriptor, especially type and address
 305 * @dev: udc managing this endpoint
 306 * @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call)
 307 */
 308struct udc_usb_ep {
 309        struct usb_ep usb_ep;
 310        struct usb_endpoint_descriptor desc;
 311        struct pxa_udc *dev;
 312        struct pxa_ep *pxa_ep;
 313};
 314
 315/**
 316 * struct pxa_ep - pxa endpoint
 317 * @dev: udc device
 318 * @queue: requests queue
 319 * @lock: lock to pxa_ep data (queues and stats)
 320 * @enabled: true when endpoint enabled (not stopped by gadget layer)
 321 * @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX)
 322 * @name: endpoint name (for trace/debug purpose)
 323 * @dir_in: 1 if IN endpoint, 0 if OUT endpoint
 324 * @addr: usb endpoint number
 325 * @config: configuration in which this endpoint is active
 326 * @interface: interface in which this endpoint is active
 327 * @alternate: altsetting in which this endpoitn is active
 328 * @fifo_size: max packet size in the endpoint fifo
 329 * @type: endpoint type (bulk, iso, int, ...)
 330 * @udccsr_value: save register of UDCCSR0 for suspend/resume
 331 * @udccr_value: save register of UDCCR for suspend/resume
 332 * @stats: endpoint statistics
 333 *
 334 * The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned
 335 * (cares about config/interface/altsetting, thus placing needless limits on
 336 * device capability) and full of implementation bugs forcing it to be set up
 337 * for use more or less like a pxa255.
 338 *
 339 * As we define the pxa_ep statically, we must guess all needed pxa_ep for all
 340 * gadget which may work with this udc driver.
 341 */
 342struct pxa_ep {
 343        struct pxa_udc          *dev;
 344
 345        struct list_head        queue;
 346        spinlock_t              lock;           /* Protects this structure */
 347                                                /* (queues, stats) */
 348        unsigned                enabled:1;
 349
 350        unsigned                idx:5;
 351        char                    *name;
 352
 353        /*
 354         * Specific pxa endpoint data, needed for hardware initialization
 355         */
 356        unsigned                dir_in:1;
 357        unsigned                addr:3;
 358        unsigned                config:2;
 359        unsigned                interface:3;
 360        unsigned                alternate:3;
 361        unsigned                fifo_size;
 362        unsigned                type;
 363
 364#ifdef CONFIG_PM
 365        u32                     udccsr_value;
 366        u32                     udccr_value;
 367#endif
 368        struct stats            stats;
 369};
 370
 371/**
 372 * struct pxa27x_request - container of each usb_request structure
 373 * @req: usb request
 374 * @udc_usb_ep: usb endpoint the request was submitted on
 375 * @in_use: sanity check if request already queued on an pxa_ep
 376 * @queue: linked list of requests, linked on pxa_ep->queue
 377 */
 378struct pxa27x_request {
 379        struct usb_request                      req;
 380        struct udc_usb_ep                       *udc_usb_ep;
 381        unsigned                                in_use:1;
 382        struct list_head                        queue;
 383};
 384
 385enum ep0_state {
 386        WAIT_FOR_SETUP,
 387        SETUP_STAGE,
 388        IN_DATA_STAGE,
 389        OUT_DATA_STAGE,
 390        IN_STATUS_STAGE,
 391        OUT_STATUS_STAGE,
 392        STALL,
 393        WAIT_ACK_SET_CONF_INTERF
 394};
 395
 396static char *ep0_state_name[] = {
 397        "WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE",
 398        "IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL",
 399        "WAIT_ACK_SET_CONF_INTERF"
 400};
 401#define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
 402
 403#define EP0_FIFO_SIZE   16U
 404#define BULK_FIFO_SIZE  64U
 405#define ISO_FIFO_SIZE   256U
 406#define INT_FIFO_SIZE   16U
 407
 408struct udc_stats {
 409        unsigned long   irqs_reset;
 410        unsigned long   irqs_suspend;
 411        unsigned long   irqs_resume;
 412        unsigned long   irqs_reconfig;
 413};
 414
 415#define NR_USB_ENDPOINTS (1 + 5)        /* ep0 + ep1in-bulk + .. + ep3in-iso */
 416#define NR_PXA_ENDPOINTS (1 + 14)       /* ep0 + epA + epB + .. + epX */
 417
 418/**
 419 * struct pxa_udc - udc structure
 420 * @regs: mapped IO space
 421 * @irq: udc irq
 422 * @clk: udc clock
 423 * @usb_gadget: udc gadget structure
 424 * @driver: bound gadget (zero, g_ether, g_file_storage, ...)
 425 * @dev: device
 426 * @mach: machine info, used to activate specific GPIO
 427 * @transceiver: external transceiver to handle vbus sense and D+ pullup
 428 * @ep0state: control endpoint state machine state
 429 * @stats: statistics on udc usage
 430 * @udc_usb_ep: array of usb endpoints offered by the gadget
 431 * @pxa_ep: array of pxa available endpoints
 432 * @enabled: UDC was enabled by a previous udc_enable()
 433 * @pullup_on: if pullup resistor connected to D+ pin
 434 * @pullup_resume: if pullup resistor should be connected to D+ pin on resume
 435 * @config: UDC active configuration
 436 * @last_interface: UDC interface of the last SET_INTERFACE host request
 437 * @last_alternate: UDC altsetting of the last SET_INTERFACE host request
 438 * @udccsr0: save of udccsr0 in case of suspend
 439 * @debugfs_root: root entry of debug filesystem
 440 * @debugfs_state: debugfs entry for "udcstate"
 441 * @debugfs_queues: debugfs entry for "queues"
 442 * @debugfs_eps: debugfs entry for "epstate"
 443 */
 444struct pxa_udc {
 445        void __iomem                            *regs;
 446        int                                     irq;
 447        struct clk                              *clk;
 448
 449        struct usb_gadget                       gadget;
 450        struct usb_gadget_driver                *driver;
 451        struct device                           *dev;
 452        struct pxa2xx_udc_mach_info             *mach;
 453        struct otg_transceiver                  *transceiver;
 454
 455        enum ep0_state                          ep0state;
 456        struct udc_stats                        stats;
 457
 458        struct udc_usb_ep                       udc_usb_ep[NR_USB_ENDPOINTS];
 459        struct pxa_ep                           pxa_ep[NR_PXA_ENDPOINTS];
 460
 461        unsigned                                enabled:1;
 462        unsigned                                pullup_on:1;
 463        unsigned                                pullup_resume:1;
 464        unsigned                                vbus_sensed:1;
 465        unsigned                                config:2;
 466        unsigned                                last_interface:3;
 467        unsigned                                last_alternate:3;
 468
 469#ifdef CONFIG_PM
 470        unsigned                                udccsr0;
 471#endif
 472#ifdef CONFIG_USB_GADGET_DEBUG_FS
 473        struct dentry                           *debugfs_root;
 474        struct dentry                           *debugfs_state;
 475        struct dentry                           *debugfs_queues;
 476        struct dentry                           *debugfs_eps;
 477#endif
 478};
 479
 480static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
 481{
 482        return container_of(gadget, struct pxa_udc, gadget);
 483}
 484
 485/*
 486 * Debugging/message support
 487 */
 488#define ep_dbg(ep, fmt, arg...) \
 489        dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 490#define ep_vdbg(ep, fmt, arg...) \
 491        dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 492#define ep_err(ep, fmt, arg...) \
 493        dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 494#define ep_info(ep, fmt, arg...) \
 495        dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
 496#define ep_warn(ep, fmt, arg...) \
 497        dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
 498
 499#endif /* __LINUX_USB_GADGET_PXA27X_H */
 500