LXR linux/drivers/usb/host/ohci-pxa27x.c

   1/*
   2 * OHCI HCD (Host Controller Driver) for USB.
   3 *
   4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
   6 * (C) Copyright 2002 Hewlett-Packard Company
   7 *
   8 * Bus Glue for pxa27x
   9 *
  10 * Written by Christopher Hoover <ch@hpl.hp.com>
  11 * Based on fragments of previous driver by Russell King et al.
  12 *
  13 * Modified for LH7A404 from ohci-sa1111.c
  14 *  by Durgesh Pattamatta <pattamattad@sharpsec.com>
  15 *
  16 * Modified for pxa27x from ohci-lh7a404.c
  17 *  by Nick Bane <nick@cecomputing.co.uk> 26-8-2004
  18 *
  19 * This file is licenced under the GPL.
  20 */
  21
  22#include <linux/device.h>
  23#include <linux/signal.h>
  24#include <linux/platform_device.h>
  25#include <linux/clk.h>
  26#include <mach/ohci.h>
  27
  28/*
  29 * UHC: USB Host Controller (OHCI-like) register definitions
  30 */
  31#define UHCREV          (0x0000) /* UHC HCI Spec Revision */
  32#define UHCHCON         (0x0004) /* UHC Host Control Register */
  33#define UHCCOMS         (0x0008) /* UHC Command Status Register */
  34#define UHCINTS         (0x000C) /* UHC Interrupt Status Register */
  35#define UHCINTE         (0x0010) /* UHC Interrupt Enable */
  36#define UHCINTD         (0x0014) /* UHC Interrupt Disable */
  37#define UHCHCCA         (0x0018) /* UHC Host Controller Comm. Area */
  38#define UHCPCED         (0x001C) /* UHC Period Current Endpt Descr */
  39#define UHCCHED         (0x0020) /* UHC Control Head Endpt Descr */
  40#define UHCCCED         (0x0024) /* UHC Control Current Endpt Descr */
  41#define UHCBHED         (0x0028) /* UHC Bulk Head Endpt Descr */
  42#define UHCBCED         (0x002C) /* UHC Bulk Current Endpt Descr */
  43#define UHCDHEAD        (0x0030) /* UHC Done Head */
  44#define UHCFMI          (0x0034) /* UHC Frame Interval */
  45#define UHCFMR          (0x0038) /* UHC Frame Remaining */
  46#define UHCFMN          (0x003C) /* UHC Frame Number */
  47#define UHCPERS         (0x0040) /* UHC Periodic Start */
  48#define UHCLS           (0x0044) /* UHC Low Speed Threshold */
  49
  50#define UHCRHDA         (0x0048) /* UHC Root Hub Descriptor A */
  51#define UHCRHDA_NOCP    (1 << 12)       /* No over current protection */
  52#define UHCRHDA_OCPM    (1 << 11)       /* Over Current Protection Mode */
  53#define UHCRHDA_POTPGT(x) \
  54                        (((x) & 0xff) << 24) /* Power On To Power Good Time */
  55
  56#define UHCRHDB         (0x004C) /* UHC Root Hub Descriptor B */
  57#define UHCRHS          (0x0050) /* UHC Root Hub Status */
  58#define UHCRHPS1        (0x0054) /* UHC Root Hub Port 1 Status */
  59#define UHCRHPS2        (0x0058) /* UHC Root Hub Port 2 Status */
  60#define UHCRHPS3        (0x005C) /* UHC Root Hub Port 3 Status */
  61
  62#define UHCSTAT         (0x0060) /* UHC Status Register */
  63#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
  64#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
  65#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
  66#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
  67#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
  68#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
  69#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
  70#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
  71#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
  72
  73#define UHCHR           (0x0064) /* UHC Reset Register */
  74#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
  75#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
  76#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
  77#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
  78#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
  79#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
  80#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
  81#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
  82#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
  83#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
  84#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
  85
  86#define UHCHIE          (0x0068) /* UHC Interrupt Enable Register*/
  87#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
  88#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
  89#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
  90#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
  91#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
  92                                           Interrupt Enable*/
  93#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
  94#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
  95
  96#define UHCHIT          (0x006C) /* UHC Interrupt Test register */
  97
  98#define PXA_UHC_MAX_PORTNUM    3
  99
 100struct pxa27x_ohci {
 101        /* must be 1st member here for hcd_to_ohci() to work */
 102        struct ohci_hcd ohci;
 103
 104        struct device   *dev;
 105        struct clk      *clk;
 106        void __iomem    *mmio_base;
 107};
 108
 109#define to_pxa27x_ohci(hcd)     (struct pxa27x_ohci *)hcd_to_ohci(hcd)
 110
 111/*
 112  PMM_NPS_MODE -- PMM Non-power switching mode
 113      Ports are powered continuously.
 114
 115  PMM_GLOBAL_MODE -- PMM global switching mode
 116      All ports are powered at the same time.
 117
 118  PMM_PERPORT_MODE -- PMM per port switching mode
 119      Ports are powered individually.
 120 */
 121static int pxa27x_ohci_select_pmm(struct pxa27x_ohci *ohci, int mode)
 122{
 123        uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
 124        uint32_t uhcrhdb = __raw_readl(ohci->mmio_base + UHCRHDB);
 125
 126        switch (mode) {
 127        case PMM_NPS_MODE:
 128                uhcrhda |= RH_A_NPS;
 129                break;
 130        case PMM_GLOBAL_MODE:
 131                uhcrhda &= ~(RH_A_NPS & RH_A_PSM);
 132                break;
 133        case PMM_PERPORT_MODE:
 134                uhcrhda &= ~(RH_A_NPS);
 135                uhcrhda |= RH_A_PSM;
 136
 137                /* Set port power control mask bits, only 3 ports. */
 138                uhcrhdb |= (0x7<<17);
 139                break;
 140        default:
 141                printk( KERN_ERR
 142                        "Invalid mode %d, set to non-power switch mode.\n",
 143                        mode );
 144
 145                uhcrhda |= RH_A_NPS;
 146        }
 147
 148        __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
 149        __raw_writel(uhcrhdb, ohci->mmio_base + UHCRHDB);
 150        return 0;
 151}
 152
 153extern int usb_disabled(void);
 154
 155/*-------------------------------------------------------------------------*/
 156
 157static inline void pxa27x_setup_hc(struct pxa27x_ohci *ohci,
 158                                   struct pxaohci_platform_data *inf)
 159{
 160        uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
 161        uint32_t uhcrhda = __raw_readl(ohci->mmio_base + UHCRHDA);
 162
 163        if (inf->flags & ENABLE_PORT1)
 164                uhchr &= ~UHCHR_SSEP1;
 165
 166        if (inf->flags & ENABLE_PORT2)
 167                uhchr &= ~UHCHR_SSEP2;
 168
 169        if (inf->flags & ENABLE_PORT3)
 170                uhchr &= ~UHCHR_SSEP3;
 171
 172        if (inf->flags & POWER_CONTROL_LOW)
 173                uhchr |= UHCHR_PCPL;
 174
 175        if (inf->flags & POWER_SENSE_LOW)
 176                uhchr |= UHCHR_PSPL;
 177
 178        if (inf->flags & NO_OC_PROTECTION)
 179                uhcrhda |= UHCRHDA_NOCP;
 180        else
 181                uhcrhda &= ~UHCRHDA_NOCP;
 182
 183        if (inf->flags & OC_MODE_PERPORT)
 184                uhcrhda |= UHCRHDA_OCPM;
 185        else
 186                uhcrhda &= ~UHCRHDA_OCPM;
 187
 188        if (inf->power_on_delay) {
 189                uhcrhda &= ~UHCRHDA_POTPGT(0xff);
 190                uhcrhda |= UHCRHDA_POTPGT(inf->power_on_delay / 2);
 191        }
 192
 193        __raw_writel(uhchr, ohci->mmio_base + UHCHR);
 194        __raw_writel(uhcrhda, ohci->mmio_base + UHCRHDA);
 195}
 196
 197static inline void pxa27x_reset_hc(struct pxa27x_ohci *ohci)
 198{
 199        uint32_t uhchr = __raw_readl(ohci->mmio_base + UHCHR);
 200
 201        __raw_writel(uhchr | UHCHR_FHR, ohci->mmio_base + UHCHR);
 202        udelay(11);
 203        __raw_writel(uhchr & ~UHCHR_FHR, ohci->mmio_base + UHCHR);
 204}
 205
 206#ifdef CONFIG_CPU_PXA27x
 207extern void pxa27x_clear_otgph(void);
 208#else
 209#define pxa27x_clear_otgph()    do {} while (0)
 210#endif
 211
 212static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
 213{
 214        int retval = 0;
 215        struct pxaohci_platform_data *inf;
 216        uint32_t uhchr;
 217
 218        inf = dev->platform_data;
 219
 220        clk_enable(ohci->clk);
 221
 222        pxa27x_reset_hc(ohci);
 223
 224        uhchr = __raw_readl(ohci->mmio_base + UHCHR) | UHCHR_FSBIR;
 225        __raw_writel(uhchr, ohci->mmio_base + UHCHR);
 226
 227        while (__raw_readl(ohci->mmio_base + UHCHR) & UHCHR_FSBIR)
 228                cpu_relax();
 229
 230        pxa27x_setup_hc(ohci, inf);
 231
 232        if (inf->init)
 233                retval = inf->init(dev);
 234
 235        if (retval < 0)
 236                return retval;
 237
 238        uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
 239        __raw_writel(uhchr, ohci->mmio_base + UHCHR);
 240        __raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
 241
 242        /* Clear any OTG Pin Hold */
 243        pxa27x_clear_otgph();
 244        return 0;
 245}
 246
 247static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
 248{
 249        struct pxaohci_platform_data *inf;
 250        uint32_t uhccoms;
 251
 252        inf = dev->platform_data;
 253
 254        if (inf->exit)
 255                inf->exit(dev);
 256
 257        pxa27x_reset_hc(ohci);
 258
 259        /* Host Controller Reset */
 260        uhccoms = __raw_readl(ohci->mmio_base + UHCCOMS) | 0x01;
 261        __raw_writel(uhccoms, ohci->mmio_base + UHCCOMS);
 262        udelay(10);
 263
 264        clk_disable(ohci->clk);
 265}
 266
 267
 268/*-------------------------------------------------------------------------*/
 269
 270/* configure so an HC device and id are always provided */
 271/* always called with process context; sleeping is OK */
 272
 273
 274/**
 275 * usb_hcd_pxa27x_probe - initialize pxa27x-based HCDs
 276 * Context: !in_interrupt()
 277 *
 278 * Allocates basic resources for this USB host controller, and
 279 * then invokes the start() method for the HCD associated with it
 280 * through the hotplug entry's driver_data.
 281 *
 282 */
 283int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device *pdev)
 284{
 285        int retval, irq;
 286        struct usb_hcd *hcd;
 287        struct pxaohci_platform_data *inf;
 288        struct pxa27x_ohci *ohci;
 289        struct resource *r;
 290        struct clk *usb_clk;
 291
 292        inf = pdev->dev.platform_data;
 293
 294        if (!inf)
 295                return -ENODEV;
 296
 297        irq = platform_get_irq(pdev, 0);
 298        if (irq < 0) {
 299                pr_err("no resource of IORESOURCE_IRQ");
 300                return -ENXIO;
 301        }
 302
 303        usb_clk = clk_get(&pdev->dev, NULL);
 304        if (IS_ERR(usb_clk))
 305                return PTR_ERR(usb_clk);
 306
 307        hcd = usb_create_hcd (driver, &pdev->dev, "pxa27x");
 308        if (!hcd)
 309                return -ENOMEM;
 310
 311        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 312        if (!r) {
 313                pr_err("no resource of IORESOURCE_MEM");
 314                retval = -ENXIO;
 315                goto err1;
 316        }
 317
 318        hcd->rsrc_start = r->start;
 319        hcd->rsrc_len = resource_size(r);
 320
 321        if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
 322                pr_debug("request_mem_region failed");
 323                retval = -EBUSY;
 324                goto err1;
 325        }
 326
 327        hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
 328        if (!hcd->regs) {
 329                pr_debug("ioremap failed");
 330                retval = -ENOMEM;
 331                goto err2;
 332        }
 333
 334        /* initialize "struct pxa27x_ohci" */
 335        ohci = (struct pxa27x_ohci *)hcd_to_ohci(hcd);
 336        ohci->dev = &pdev->dev;
 337        ohci->clk = usb_clk;
 338        ohci->mmio_base = (void __iomem *)hcd->regs;
 339
 340        if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
 341                pr_debug("pxa27x_start_hc failed");
 342                goto err3;
 343        }
 344
 345        /* Select Power Management Mode */
 346        pxa27x_ohci_select_pmm(ohci, inf->port_mode);
 347
 348        if (inf->power_budget)
 349                hcd->power_budget = inf->power_budget;
 350
 351        ohci_hcd_init(hcd_to_ohci(hcd));
 352
 353        retval = usb_add_hcd(hcd, irq, IRQF_DISABLED);
 354        if (retval == 0)
 355                return retval;
 356
 357        pxa27x_stop_hc(ohci, &pdev->dev);
 358 err3:
 359        iounmap(hcd->regs);
 360 err2:
 361        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 362 err1:
 363        usb_put_hcd(hcd);
 364        clk_put(usb_clk);
 365        return retval;
 366}
 367
 368
 369/* may be called without controller electrically present */
 370/* may be called with controller, bus, and devices active */
 371
 372/**
 373 * usb_hcd_pxa27x_remove - shutdown processing for pxa27x-based HCDs
 374 * @dev: USB Host Controller being removed
 375 * Context: !in_interrupt()
 376 *
 377 * Reverses the effect of usb_hcd_pxa27x_probe(), first invoking
 378 * the HCD's stop() method.  It is always called from a thread
 379 * context, normally "rmmod", "apmd", or something similar.
 380 *
 381 */
 382void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
 383{
 384        struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
 385
 386        usb_remove_hcd(hcd);
 387        pxa27x_stop_hc(ohci, &pdev->dev);
 388        iounmap(hcd->regs);
 389        release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 390        usb_put_hcd(hcd);
 391        clk_put(ohci->clk);
 392}
 393
 394/*-------------------------------------------------------------------------*/
 395
 396static int __devinit
 397ohci_pxa27x_start (struct usb_hcd *hcd)
 398{
 399        struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 400        int             ret;
 401
 402        ohci_dbg (ohci, "ohci_pxa27x_start, ohci:%p", ohci);
 403
 404        /* The value of NDP in roothub_a is incorrect on this hardware */
 405        ohci->num_ports = 3;
 406
 407        if ((ret = ohci_init(ohci)) < 0)
 408                return ret;
 409
 410        if ((ret = ohci_run (ohci)) < 0) {
 411                err ("can't start %s", hcd->self.bus_name);
 412                ohci_stop (hcd);
 413                return ret;
 414        }
 415
 416        return 0;
 417}
 418
 419/*-------------------------------------------------------------------------*/
 420
 421static const struct hc_driver ohci_pxa27x_hc_driver = {
 422        .description =          hcd_name,
 423        .product_desc =         "PXA27x OHCI",
 424        .hcd_priv_size =        sizeof(struct pxa27x_ohci),
 425
 426        /*
 427         * generic hardware linkage
 428         */
 429        .irq =                  ohci_irq,
 430        .flags =                HCD_USB11 | HCD_MEMORY,
 431
 432        /*
 433         * basic lifecycle operations
 434         */
 435        .start =                ohci_pxa27x_start,
 436        .stop =                 ohci_stop,
 437        .shutdown =             ohci_shutdown,
 438
 439        /*
 440         * managing i/o requests and associated device resources
 441         */
 442        .urb_enqueue =          ohci_urb_enqueue,
 443        .urb_dequeue =          ohci_urb_dequeue,
 444        .endpoint_disable =     ohci_endpoint_disable,
 445
 446        /*
 447         * scheduling support
 448         */
 449        .get_frame_number =     ohci_get_frame,
 450
 451        /*
 452         * root hub support
 453         */
 454        .hub_status_data =      ohci_hub_status_data,
 455        .hub_control =          ohci_hub_control,
 456#ifdef  CONFIG_PM
 457        .bus_suspend =          ohci_bus_suspend,
 458        .bus_resume =           ohci_bus_resume,
 459#endif
 460        .start_port_reset =     ohci_start_port_reset,
 461};
 462
 463/*-------------------------------------------------------------------------*/
 464
 465static int ohci_hcd_pxa27x_drv_probe(struct platform_device *pdev)
 466{
 467        pr_debug ("In ohci_hcd_pxa27x_drv_probe");
 468
 469        if (usb_disabled())
 470                return -ENODEV;
 471
 472        return usb_hcd_pxa27x_probe(&ohci_pxa27x_hc_driver, pdev);
 473}
 474
 475static int ohci_hcd_pxa27x_drv_remove(struct platform_device *pdev)
 476{
 477        struct usb_hcd *hcd = platform_get_drvdata(pdev);
 478
 479        usb_hcd_pxa27x_remove(hcd, pdev);
 480        platform_set_drvdata(pdev, NULL);
 481        return 0;
 482}
 483
 484#ifdef CONFIG_PM
 485static int ohci_hcd_pxa27x_drv_suspend(struct device *dev)
 486{
 487        struct usb_hcd *hcd = dev_get_drvdata(dev);
 488        struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
 489
 490        if (time_before(jiffies, ohci->ohci.next_statechange))
 491                msleep(5);
 492        ohci->ohci.next_statechange = jiffies;
 493
 494        pxa27x_stop_hc(ohci, dev);
 495        hcd->state = HC_STATE_SUSPENDED;
 496
 497        return 0;
 498}
 499
 500static int ohci_hcd_pxa27x_drv_resume(struct device *dev)
 501{
 502        struct usb_hcd *hcd = dev_get_drvdata(dev);
 503        struct pxa27x_ohci *ohci = to_pxa27x_ohci(hcd);
 504        struct pxaohci_platform_data *inf = dev->platform_data;
 505        int status;
 506
 507        if (time_before(jiffies, ohci->ohci.next_statechange))
 508                msleep(5);
 509        ohci->ohci.next_statechange = jiffies;
 510
 511        if ((status = pxa27x_start_hc(ohci, dev)) < 0)
 512                return status;
 513
 514        /* Select Power Management Mode */
 515        pxa27x_ohci_select_pmm(ohci, inf->port_mode);
 516
 517        ohci_finish_controller_resume(hcd);
 518        return 0;
 519}
 520
 521static struct dev_pm_ops ohci_hcd_pxa27x_pm_ops = {
 522        .suspend        = ohci_hcd_pxa27x_drv_suspend,
 523        .resume         = ohci_hcd_pxa27x_drv_resume,
 524};
 525#endif
 526
 527/* work with hotplug and coldplug */
 528MODULE_ALIAS("platform:pxa27x-ohci");
 529
 530static struct platform_driver ohci_hcd_pxa27x_driver = {
 531        .probe          = ohci_hcd_pxa27x_drv_probe,
 532        .remove         = ohci_hcd_pxa27x_drv_remove,
 533        .shutdown       = usb_hcd_platform_shutdown,
 534        .driver         = {
 535                .name   = "pxa27x-ohci",
 536                .owner  = THIS_MODULE,
 537#ifdef CONFIG_PM
 538                .pm     = &ohci_hcd_pxa27x_pm_ops,
 539#endif
 540        },
 541};
 542
 543