1#ifndef __LINUX_UHCI_HCD_H
2#define __LINUX_UHCI_HCD_H
3
4#include <linux/list.h>
5#include <linux/usb.h>
6
7#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
8#define PIPE_DEVEP_MASK 0x0007ff00
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15
16#define USBCMD 0
17#define USBCMD_RS 0x0001
18#define USBCMD_HCRESET 0x0002
19#define USBCMD_GRESET 0x0004
20#define USBCMD_EGSM 0x0008
21#define USBCMD_FGR 0x0010
22#define USBCMD_SWDBG 0x0020
23#define USBCMD_CF 0x0040
24#define USBCMD_MAXP 0x0080
25
26
27#define USBSTS 2
28#define USBSTS_USBINT 0x0001
29#define USBSTS_ERROR 0x0002
30#define USBSTS_RD 0x0004
31#define USBSTS_HSE 0x0008
32#define USBSTS_HCPE 0x0010
33
34#define USBSTS_HCH 0x0020
35
36
37#define USBINTR 4
38#define USBINTR_TIMEOUT 0x0001
39#define USBINTR_RESUME 0x0002
40#define USBINTR_IOC 0x0004
41#define USBINTR_SP 0x0008
42
43#define USBFRNUM 6
44#define USBFLBASEADD 8
45#define USBSOF 12
46#define USBSOF_DEFAULT 64
47
48
49#define USBPORTSC1 16
50#define USBPORTSC2 18
51#define USBPORTSC_CCS 0x0001
52
53#define USBPORTSC_CSC 0x0002
54#define USBPORTSC_PE 0x0004
55#define USBPORTSC_PEC 0x0008
56#define USBPORTSC_DPLUS 0x0010
57#define USBPORTSC_DMINUS 0x0020
58#define USBPORTSC_RD 0x0040
59#define USBPORTSC_RES1 0x0080
60#define USBPORTSC_LSDA 0x0100
61#define USBPORTSC_PR 0x0200
62
63#define USBPORTSC_OC 0x0400
64#define USBPORTSC_OCC 0x0800
65#define USBPORTSC_SUSP 0x1000
66#define USBPORTSC_RES2 0x2000
67#define USBPORTSC_RES3 0x4000
68#define USBPORTSC_RES4 0x8000
69
70
71#define USBLEGSUP 0xc0
72#define USBLEGSUP_DEFAULT 0x2000
73#define USBLEGSUP_RWC 0x8f00
74#define USBLEGSUP_RO 0x5040
75
76#define UHCI_PTR_BITS cpu_to_le32(0x000F)
77#define UHCI_PTR_TERM cpu_to_le32(0x0001)
78#define UHCI_PTR_QH cpu_to_le32(0x0002)
79#define UHCI_PTR_DEPTH cpu_to_le32(0x0004)
80#define UHCI_PTR_BREADTH cpu_to_le32(0x0000)
81
82#define UHCI_NUMFRAMES 1024
83#define UHCI_MAX_SOF_NUMBER 2047
84#define CAN_SCHEDULE_FRAMES 1000
85
86#define MAX_PHASE 32
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89
90#define FSBR_OFF_DELAY msecs_to_jiffies(10)
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93#define QH_WAIT_TIMEOUT msecs_to_jiffies(200)
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120#define QH_STATE_IDLE 1
121#define QH_STATE_UNLINKING 2
122
123
124#define QH_STATE_ACTIVE 3
125
126struct uhci_qh {
127
128 __le32 link;
129 __le32 element;
130
131
132 dma_addr_t dma_handle;
133
134 struct list_head node;
135 struct usb_host_endpoint *hep;
136 struct usb_device *udev;
137 struct list_head queue;
138 struct uhci_td *dummy_td;
139 struct uhci_td *post_td;
140
141 struct usb_iso_packet_descriptor *iso_packet_desc;
142
143 unsigned long advance_jiffies;
144 unsigned int unlink_frame;
145 unsigned int period;
146 short phase;
147 short load;
148 unsigned int iso_frame;
149
150 int state;
151 int type;
152 int skel;
153
154 unsigned int initial_toggle:1;
155 unsigned int needs_fixup:1;
156 unsigned int is_stopped:1;
157 unsigned int wait_expired:1;
158 unsigned int bandwidth_reserved:1;
159
160} __attribute__((aligned(16)));
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165
166static inline __le32 qh_element(struct uhci_qh *qh) {
167 __le32 element = qh->element;
168
169 barrier();
170 return element;
171}
172
173#define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle))
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182
183#define TD_CTRL_SPD (1 << 29)
184#define TD_CTRL_C_ERR_MASK (3 << 27)
185#define TD_CTRL_C_ERR_SHIFT 27
186#define TD_CTRL_LS (1 << 26)
187#define TD_CTRL_IOS (1 << 25)
188#define TD_CTRL_IOC (1 << 24)
189#define TD_CTRL_ACTIVE (1 << 23)
190#define TD_CTRL_STALLED (1 << 22)
191#define TD_CTRL_DBUFERR (1 << 21)
192#define TD_CTRL_BABBLE (1 << 20)
193#define TD_CTRL_NAK (1 << 19)
194#define TD_CTRL_CRCTIMEO (1 << 18)
195#define TD_CTRL_BITSTUFF (1 << 17)
196#define TD_CTRL_ACTLEN_MASK 0x7FF
197
198#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
199 TD_CTRL_BABBLE | TD_CTRL_CRCTIME | \
200 TD_CTRL_BITSTUFF)
201
202#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
203#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
204#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & \
205 TD_CTRL_ACTLEN_MASK)
206
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208
209
210#define td_token(td) le32_to_cpu((td)->token)
211#define TD_TOKEN_DEVADDR_SHIFT 8
212#define TD_TOKEN_TOGGLE_SHIFT 19
213#define TD_TOKEN_TOGGLE (1 << 19)
214#define TD_TOKEN_EXPLEN_SHIFT 21
215#define TD_TOKEN_EXPLEN_MASK 0x7FF
216#define TD_TOKEN_PID_MASK 0xFF
217
218#define uhci_explen(len) ((((len) - 1) & TD_TOKEN_EXPLEN_MASK) << \
219 TD_TOKEN_EXPLEN_SHIFT)
220
221#define uhci_expected_length(token) ((((token) >> TD_TOKEN_EXPLEN_SHIFT) + \
222 1) & TD_TOKEN_EXPLEN_MASK)
223#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
224#define uhci_endpoint(token) (((token) >> 15) & 0xf)
225#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
226#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
227#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
228#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
229#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
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241struct uhci_td {
242
243 __le32 link;
244 __le32 status;
245 __le32 token;
246 __le32 buffer;
247
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249 dma_addr_t dma_handle;
250
251 struct list_head list;
252
253 int frame;
254 struct list_head fl_list;
255} __attribute__((aligned(16)));
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261static inline u32 td_status(struct uhci_td *td) {
262 __le32 status = td->status;
263
264 barrier();
265 return le32_to_cpu(status);
266}
267
268#define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle))
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316#define UHCI_NUM_SKELQH 11
317#define SKEL_UNLINK 0
318#define skel_unlink_qh skelqh[SKEL_UNLINK]
319#define SKEL_ISO 1
320#define skel_iso_qh skelqh[SKEL_ISO]
321
322#define SKEL_INDEX(exponent) (9 - exponent)
323#define SKEL_ASYNC 9
324#define skel_async_qh skelqh[SKEL_ASYNC]
325#define SKEL_TERM 10
326#define skel_term_qh skelqh[SKEL_TERM]
327
328
329#define SKEL_LS_CONTROL 20
330#define SKEL_FS_CONTROL 21
331#define SKEL_FSBR SKEL_FS_CONTROL
332#define SKEL_BULK 22
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347
348enum uhci_rh_state {
349
350
351 UHCI_RH_RESET,
352 UHCI_RH_SUSPENDED,
353
354 UHCI_RH_AUTO_STOPPED,
355 UHCI_RH_RESUMING,
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359 UHCI_RH_SUSPENDING,
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363 UHCI_RH_RUNNING,
364 UHCI_RH_RUNNING_NODEVS,
365};
366
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369
370struct uhci_hcd {
371
372
373 struct dentry *dentry;
374
375
376 unsigned long io_addr;
377
378 struct dma_pool *qh_pool;
379 struct dma_pool *td_pool;
380
381 struct uhci_td *term_td;
382 struct uhci_qh *skelqh[UHCI_NUM_SKELQH];
383 struct uhci_qh *next_qh;
384
385 spinlock_t lock;
386
387 dma_addr_t frame_dma_handle;
388 __le32 *frame;
389 void **frame_cpu;
390
391 enum uhci_rh_state rh_state;
392 unsigned long auto_stop_time;
393
394 unsigned int frame_number;
395 unsigned int is_stopped;
396#define UHCI_IS_STOPPED 9999
397 unsigned int last_iso_frame;
398 unsigned int cur_iso_frame;
399
400 unsigned int scan_in_progress:1;
401 unsigned int need_rescan:1;
402 unsigned int dead:1;
403 unsigned int RD_enable:1;
404
405
406 unsigned int is_initialized:1;
407 unsigned int fsbr_is_on:1;
408 unsigned int fsbr_is_wanted:1;
409 unsigned int fsbr_expiring:1;
410
411 struct timer_list fsbr_timer;
412
413
414 unsigned long port_c_suspend;
415 unsigned long resuming_ports;
416 unsigned long ports_timeout;
417
418 struct list_head idle_qh_list;
419
420 int rh_numports;
421
422 wait_queue_head_t waitqh;
423 int num_waiting;
424
425 int total_load;
426 short load[MAX_PHASE];
427};
428
429
430static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
431{
432 return (struct uhci_hcd *) (hcd->hcd_priv);
433}
434static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
435{
436 return container_of((void *) uhci, struct usb_hcd, hcd_priv);
437}
438
439#define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
440
441
442#define uhci_frame_before_eq(f1, f2) (0 <= (int) ((f2) - (f1)))
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447
448struct urb_priv {
449 struct list_head node;
450
451 struct urb *urb;
452
453 struct uhci_qh *qh;
454 struct list_head td_list;
455
456 unsigned fsbr:1;
457};
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461
462#define PCI_VENDOR_ID_GENESYS 0x17a0
463#define PCI_DEVICE_ID_GL880S_UHCI 0x8083
464
465#endif
466