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11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/sched.h>
14#include <linux/slab.h>
15#include <linux/init.h>
16#include <linux/list.h>
17#include <linux/gpio.h>
18#include <linux/io.h>
19
20#include <asm/cacheflush.h>
21
22#include "musb_core.h"
23#include "blackfin.h"
24
25
26
27
28void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
29{
30 void __iomem *fifo = hw_ep->fifo;
31 void __iomem *epio = hw_ep->regs;
32
33 prefetch((u8 *)src);
34
35 musb_writew(epio, MUSB_TXCOUNT, len);
36
37 DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
38 hw_ep->epnum, fifo, len, src, epio);
39
40 dump_fifo_data(src, len);
41
42 if (unlikely((unsigned long)src & 0x01))
43 outsw_8((unsigned long)fifo, src,
44 len & 0x01 ? (len >> 1) + 1 : len >> 1);
45 else
46 outsw((unsigned long)fifo, src,
47 len & 0x01 ? (len >> 1) + 1 : len >> 1);
48}
49
50
51
52
53void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
54{
55 void __iomem *fifo = hw_ep->fifo;
56 u8 epnum = hw_ep->epnum;
57 u16 dma_reg = 0;
58
59 DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
60 'R', hw_ep->epnum, fifo, len, dst);
61
62#ifdef CONFIG_BF52x
63 invalidate_dcache_range((unsigned int)dst,
64 (unsigned int)(dst + len));
65
66
67 dma_reg = (u16) ((u32) dst & 0xFFFF);
68 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
69 SSYNC();
70
71 dma_reg = (u16) (((u32) dst >> 16) & 0xFFFF);
72 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
73 SSYNC();
74
75
76 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
77 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
78 SSYNC();
79
80
81 dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
82 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
83 SSYNC();
84
85
86 while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
87 cpu_relax();
88
89
90 bfin_write_USB_DMA_INTERRUPT(1 << epnum);
91 SSYNC();
92
93
94 bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
95 SSYNC();
96#else
97 if (unlikely((unsigned long)dst & 0x01))
98 insw_8((unsigned long)fifo, dst,
99 len & 0x01 ? (len >> 1) + 1 : len >> 1);
100 else
101 insw((unsigned long)fifo, dst,
102 len & 0x01 ? (len >> 1) + 1 : len >> 1);
103#endif
104
105 dump_fifo_data(dst, len);
106}
107
108static irqreturn_t blackfin_interrupt(int irq, void *__hci)
109{
110 unsigned long flags;
111 irqreturn_t retval = IRQ_NONE;
112 struct musb *musb = __hci;
113
114 spin_lock_irqsave(&musb->lock, flags);
115
116 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
117 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
118 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
119
120 if (musb->int_usb || musb->int_tx || musb->int_rx) {
121 musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
122 musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
123 musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
124 retval = musb_interrupt(musb);
125 }
126
127 spin_unlock_irqrestore(&musb->lock, flags);
128
129
130
131
132 if (retval != IRQ_HANDLED)
133 DBG(5, "spurious?\n");
134
135 return IRQ_HANDLED;
136}
137
138static void musb_conn_timer_handler(unsigned long _musb)
139{
140 struct musb *musb = (void *)_musb;
141 unsigned long flags;
142 u16 val;
143
144 spin_lock_irqsave(&musb->lock, flags);
145 switch (musb->xceiv->state) {
146 case OTG_STATE_A_IDLE:
147 case OTG_STATE_A_WAIT_BCON:
148
149 val = musb_readw(musb->mregs, MUSB_DEVCTL);
150 val |= MUSB_DEVCTL_SESSION;
151 musb_writew(musb->mregs, MUSB_DEVCTL, val);
152
153 val = musb_readw(musb->mregs, MUSB_DEVCTL);
154 if (!(val & MUSB_DEVCTL_BDEVICE)) {
155 gpio_set_value(musb->config->gpio_vrsel, 1);
156 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
157 } else {
158 gpio_set_value(musb->config->gpio_vrsel, 0);
159
160
161 val = musb_readb(musb->mregs, MUSB_INTRUSBE);
162 val &= ~MUSB_INTR_VBUSERROR;
163 musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
164
165 val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
166 musb_writeb(musb->mregs, MUSB_INTRUSB, val);
167
168 val = MUSB_POWER_HSENAB;
169 musb_writeb(musb->mregs, MUSB_POWER, val);
170 }
171 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
172 break;
173
174 default:
175 DBG(1, "%s state not handled\n", otg_state_string(musb));
176 break;
177 }
178 spin_unlock_irqrestore(&musb->lock, flags);
179
180 DBG(4, "state is %s\n", otg_state_string(musb));
181}
182
183void musb_platform_enable(struct musb *musb)
184{
185 if (is_host_enabled(musb)) {
186 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
187 musb->a_wait_bcon = TIMER_DELAY;
188 }
189}
190
191void musb_platform_disable(struct musb *musb)
192{
193}
194
195static void bfin_vbus_power(struct musb *musb, int is_on, int sleeping)
196{
197}
198
199static void bfin_set_vbus(struct musb *musb, int is_on)
200{
201 if (is_on)
202 gpio_set_value(musb->config->gpio_vrsel, 1);
203 else
204 gpio_set_value(musb->config->gpio_vrsel, 0);
205
206 DBG(1, "VBUS %s, devctl %02x "
207 "\n",
208 otg_state_string(musb),
209 musb_readb(musb->mregs, MUSB_DEVCTL));
210}
211
212static int bfin_set_power(struct otg_transceiver *x, unsigned mA)
213{
214 return 0;
215}
216
217void musb_platform_try_idle(struct musb *musb, unsigned long timeout)
218{
219 if (is_host_enabled(musb))
220 mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
221}
222
223int musb_platform_get_vbus_status(struct musb *musb)
224{
225 return 0;
226}
227
228void musb_platform_set_mode(struct musb *musb, u8 musb_mode)
229{
230}
231
232int __init musb_platform_init(struct musb *musb)
233{
234
235
236
237
238
239
240
241
242 if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
243 printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d \n",
244 musb->config->gpio_vrsel);
245 return -ENODEV;
246 }
247 gpio_direction_output(musb->config->gpio_vrsel, 0);
248
249 usb_nop_xceiv_register();
250 musb->xceiv = otg_get_transceiver();
251 if (!musb->xceiv)
252 return -ENODEV;
253
254 if (ANOMALY_05000346) {
255 bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
256 SSYNC();
257 }
258
259 if (ANOMALY_05000347) {
260 bfin_write_USB_APHY_CNTRL(0x0);
261 SSYNC();
262 }
263
264
265
266
267
268
269 bfin_write_USB_PLLOSC_CTRL(0x30a8);
270 SSYNC();
271
272 bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
273 SSYNC();
274
275 bfin_write_USB_EP_NI0_RXMAXP(64);
276 SSYNC();
277
278 bfin_write_USB_EP_NI0_TXMAXP(64);
279 SSYNC();
280
281
282 bfin_write_USB_GLOBINTR(0x7);
283 SSYNC();
284
285 bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
286 EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
287 EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
288 EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
289 EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
290 SSYNC();
291
292 if (is_host_enabled(musb)) {
293 musb->board_set_vbus = bfin_set_vbus;
294 setup_timer(&musb_conn_timer,
295 musb_conn_timer_handler, (unsigned long) musb);
296 }
297 if (is_peripheral_enabled(musb))
298 musb->xceiv->set_power = bfin_set_power;
299
300 musb->isr = blackfin_interrupt;
301
302 return 0;
303}
304
305int musb_platform_suspend(struct musb *musb)
306{
307 return 0;
308}
309
310int musb_platform_resume(struct musb *musb)
311{
312 return 0;
313}
314
315
316int musb_platform_exit(struct musb *musb)
317{
318
319 bfin_vbus_power(musb, 0 , 1);
320 gpio_free(musb->config->gpio_vrsel);
321 musb_platform_suspend(musb);
322
323 return 0;
324}
325
