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36#include <linux/kernel.h>
37#include <linux/list.h>
38#include <linux/timer.h>
39#include <linux/module.h>
40#include <linux/smp.h>
41#include <linux/spinlock.h>
42#include <linux/delay.h>
43#include <linux/moduleparam.h>
44#include <linux/stat.h>
45#include <linux/dma-mapping.h>
46
47#include "musb_core.h"
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101void musb_g_giveback(
102 struct musb_ep *ep,
103 struct usb_request *request,
104 int status)
105__releases(ep->musb->lock)
106__acquires(ep->musb->lock)
107{
108 struct musb_request *req;
109 struct musb *musb;
110 int busy = ep->busy;
111
112 req = to_musb_request(request);
113
114 list_del(&request->list);
115 if (req->request.status == -EINPROGRESS)
116 req->request.status = status;
117 musb = req->musb;
118
119 ep->busy = 1;
120 spin_unlock(&musb->lock);
121 if (is_dma_capable()) {
122 if (req->mapped) {
123 dma_unmap_single(musb->controller,
124 req->request.dma,
125 req->request.length,
126 req->tx
127 ? DMA_TO_DEVICE
128 : DMA_FROM_DEVICE);
129 req->request.dma = DMA_ADDR_INVALID;
130 req->mapped = 0;
131 } else if (req->request.dma != DMA_ADDR_INVALID)
132 dma_sync_single_for_cpu(musb->controller,
133 req->request.dma,
134 req->request.length,
135 req->tx
136 ? DMA_TO_DEVICE
137 : DMA_FROM_DEVICE);
138 }
139 if (request->status == 0)
140 DBG(5, "%s done request %p, %d/%d\n",
141 ep->end_point.name, request,
142 req->request.actual, req->request.length);
143 else
144 DBG(2, "%s request %p, %d/%d fault %d\n",
145 ep->end_point.name, request,
146 req->request.actual, req->request.length,
147 request->status);
148 req->request.complete(&req->ep->end_point, &req->request);
149 spin_lock(&musb->lock);
150 ep->busy = busy;
151}
152
153
154
155
156
157
158
159static void nuke(struct musb_ep *ep, const int status)
160{
161 struct musb_request *req = NULL;
162 void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
163
164 ep->busy = 1;
165
166 if (is_dma_capable() && ep->dma) {
167 struct dma_controller *c = ep->musb->dma_controller;
168 int value;
169
170 if (ep->is_in) {
171
172
173
174
175
176 musb_writew(epio, MUSB_TXCSR,
177 MUSB_TXCSR_DMAMODE | MUSB_TXCSR_FLUSHFIFO);
178 musb_writew(epio, MUSB_TXCSR,
179 0 | MUSB_TXCSR_FLUSHFIFO);
180 } else {
181 musb_writew(epio, MUSB_RXCSR,
182 0 | MUSB_RXCSR_FLUSHFIFO);
183 musb_writew(epio, MUSB_RXCSR,
184 0 | MUSB_RXCSR_FLUSHFIFO);
185 }
186
187 value = c->channel_abort(ep->dma);
188 DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
189 c->channel_release(ep->dma);
190 ep->dma = NULL;
191 }
192
193 while (!list_empty(&(ep->req_list))) {
194 req = container_of(ep->req_list.next, struct musb_request,
195 request.list);
196 musb_g_giveback(ep, &req->request, status);
197 }
198}
199
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208
209static inline int max_ep_writesize(struct musb *musb, struct musb_ep *ep)
210{
211 if (can_bulk_split(musb, ep->type))
212 return ep->hw_ep->max_packet_sz_tx;
213 else
214 return ep->packet_sz;
215}
216
217
218#ifdef CONFIG_USB_INVENTRA_DMA
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250#endif
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258
259static void txstate(struct musb *musb, struct musb_request *req)
260{
261 u8 epnum = req->epnum;
262 struct musb_ep *musb_ep;
263 void __iomem *epio = musb->endpoints[epnum].regs;
264 struct usb_request *request;
265 u16 fifo_count = 0, csr;
266 int use_dma = 0;
267
268 musb_ep = req->ep;
269
270
271 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
272 DBG(4, "dma pending...\n");
273 return;
274 }
275
276
277 csr = musb_readw(epio, MUSB_TXCSR);
278
279 request = &req->request;
280 fifo_count = min(max_ep_writesize(musb, musb_ep),
281 (int)(request->length - request->actual));
282
283 if (csr & MUSB_TXCSR_TXPKTRDY) {
284 DBG(5, "%s old packet still ready , txcsr %03x\n",
285 musb_ep->end_point.name, csr);
286 return;
287 }
288
289 if (csr & MUSB_TXCSR_P_SENDSTALL) {
290 DBG(5, "%s stalling, txcsr %03x\n",
291 musb_ep->end_point.name, csr);
292 return;
293 }
294
295 DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
296 epnum, musb_ep->packet_sz, fifo_count,
297 csr);
298
299#ifndef CONFIG_MUSB_PIO_ONLY
300 if (is_dma_capable() && musb_ep->dma) {
301 struct dma_controller *c = musb->dma_controller;
302
303 use_dma = (request->dma != DMA_ADDR_INVALID);
304
305
306
307#ifdef CONFIG_USB_INVENTRA_DMA
308 {
309 size_t request_size;
310
311
312 request_size = min(request->length,
313 musb_ep->dma->max_len);
314 if (request_size < musb_ep->packet_sz)
315 musb_ep->dma->desired_mode = 0;
316 else
317 musb_ep->dma->desired_mode = 1;
318
319 use_dma = use_dma && c->channel_program(
320 musb_ep->dma, musb_ep->packet_sz,
321 musb_ep->dma->desired_mode,
322 request->dma, request_size);
323 if (use_dma) {
324 if (musb_ep->dma->desired_mode == 0) {
325
326
327
328
329
330
331 csr &= ~(MUSB_TXCSR_AUTOSET
332 | MUSB_TXCSR_DMAENAB);
333 musb_writew(epio, MUSB_TXCSR, csr
334 | MUSB_TXCSR_P_WZC_BITS);
335 csr &= ~MUSB_TXCSR_DMAMODE;
336 csr |= (MUSB_TXCSR_DMAENAB |
337 MUSB_TXCSR_MODE);
338
339 } else
340 csr |= (MUSB_TXCSR_AUTOSET
341 | MUSB_TXCSR_DMAENAB
342 | MUSB_TXCSR_DMAMODE
343 | MUSB_TXCSR_MODE);
344
345 csr &= ~MUSB_TXCSR_P_UNDERRUN;
346 musb_writew(epio, MUSB_TXCSR, csr);
347 }
348 }
349
350#elif defined(CONFIG_USB_TI_CPPI_DMA)
351
352 csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
353 csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
354 MUSB_TXCSR_MODE;
355 musb_writew(epio, MUSB_TXCSR,
356 (MUSB_TXCSR_P_WZC_BITS & ~MUSB_TXCSR_P_UNDERRUN)
357 | csr);
358
359
360 csr = musb_readw(epio, MUSB_TXCSR);
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372 use_dma = use_dma && c->channel_program(
373 musb_ep->dma, musb_ep->packet_sz,
374 0,
375 request->dma,
376 request->length);
377 if (!use_dma) {
378 c->channel_release(musb_ep->dma);
379 musb_ep->dma = NULL;
380 csr &= ~MUSB_TXCSR_DMAENAB;
381 musb_writew(epio, MUSB_TXCSR, csr);
382
383 }
384#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
385 use_dma = use_dma && c->channel_program(
386 musb_ep->dma, musb_ep->packet_sz,
387 request->zero,
388 request->dma,
389 request->length);
390#endif
391 }
392#endif
393
394 if (!use_dma) {
395 musb_write_fifo(musb_ep->hw_ep, fifo_count,
396 (u8 *) (request->buf + request->actual));
397 request->actual += fifo_count;
398 csr |= MUSB_TXCSR_TXPKTRDY;
399 csr &= ~MUSB_TXCSR_P_UNDERRUN;
400 musb_writew(epio, MUSB_TXCSR, csr);
401 }
402
403
404 DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
405 musb_ep->end_point.name, use_dma ? "dma" : "pio",
406 request->actual, request->length,
407 musb_readw(epio, MUSB_TXCSR),
408 fifo_count,
409 musb_readw(epio, MUSB_TXMAXP));
410}
411
412
413
414
415
416void musb_g_tx(struct musb *musb, u8 epnum)
417{
418 u16 csr;
419 struct usb_request *request;
420 u8 __iomem *mbase = musb->mregs;
421 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_in;
422 void __iomem *epio = musb->endpoints[epnum].regs;
423 struct dma_channel *dma;
424
425 musb_ep_select(mbase, epnum);
426 request = next_request(musb_ep);
427
428 csr = musb_readw(epio, MUSB_TXCSR);
429 DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
430
431 dma = is_dma_capable() ? musb_ep->dma : NULL;
432 do {
433
434
435
436 if (csr & MUSB_TXCSR_P_SENTSTALL) {
437 csr |= MUSB_TXCSR_P_WZC_BITS;
438 csr &= ~MUSB_TXCSR_P_SENTSTALL;
439 musb_writew(epio, MUSB_TXCSR, csr);
440 break;
441 }
442
443 if (csr & MUSB_TXCSR_P_UNDERRUN) {
444
445 csr |= MUSB_TXCSR_P_WZC_BITS;
446 csr &= ~(MUSB_TXCSR_P_UNDERRUN
447 | MUSB_TXCSR_TXPKTRDY);
448 musb_writew(epio, MUSB_TXCSR, csr);
449 DBG(20, "underrun on ep%d, req %p\n", epnum, request);
450 }
451
452 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
453
454
455
456 DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
457 break;
458 }
459
460 if (request) {
461 u8 is_dma = 0;
462
463 if (dma && (csr & MUSB_TXCSR_DMAENAB)) {
464 is_dma = 1;
465 csr |= MUSB_TXCSR_P_WZC_BITS;
466 csr &= ~(MUSB_TXCSR_DMAENAB
467 | MUSB_TXCSR_P_UNDERRUN
468 | MUSB_TXCSR_TXPKTRDY);
469 musb_writew(epio, MUSB_TXCSR, csr);
470
471 csr = musb_readw(epio, MUSB_TXCSR);
472 request->actual += musb_ep->dma->actual_len;
473 DBG(4, "TXCSR%d %04x, dma off, "
474 "len %zu, req %p\n",
475 epnum, csr,
476 musb_ep->dma->actual_len,
477 request);
478 }
479
480 if (is_dma || request->actual == request->length) {
481
482
483
484
485
486 if ((request->zero
487 && request->length
488 && (request->length
489 % musb_ep->packet_sz)
490 == 0)
491#ifdef CONFIG_USB_INVENTRA_DMA
492 || (is_dma &&
493 ((!dma->desired_mode) ||
494 (request->actual &
495 (musb_ep->packet_sz - 1))))
496#endif
497 ) {
498
499
500
501 if (csr & MUSB_TXCSR_TXPKTRDY)
502 break;
503
504 DBG(4, "sending zero pkt\n");
505 musb_writew(epio, MUSB_TXCSR,
506 MUSB_TXCSR_MODE
507 | MUSB_TXCSR_TXPKTRDY);
508 request->zero = 0;
509 }
510
511
512 musb_g_giveback(musb_ep, request, 0);
513
514
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516
517
518
519
520 musb_ep_select(mbase, epnum);
521 csr = musb_readw(epio, MUSB_TXCSR);
522 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
523 break;
524 request = musb_ep->desc
525 ? next_request(musb_ep)
526 : NULL;
527 if (!request) {
528 DBG(4, "%s idle now\n",
529 musb_ep->end_point.name);
530 break;
531 }
532 }
533
534 txstate(musb, to_musb_request(request));
535 }
536
537 } while (0);
538}
539
540
541
542#ifdef CONFIG_USB_INVENTRA_DMA
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571#endif
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575
576static void rxstate(struct musb *musb, struct musb_request *req)
577{
578 const u8 epnum = req->epnum;
579 struct usb_request *request = &req->request;
580 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
581 void __iomem *epio = musb->endpoints[epnum].regs;
582 unsigned fifo_count = 0;
583 u16 len = musb_ep->packet_sz;
584 u16 csr = musb_readw(epio, MUSB_RXCSR);
585
586
587 if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
588 DBG(4, "DMA pending...\n");
589 return;
590 }
591
592 if (csr & MUSB_RXCSR_P_SENDSTALL) {
593 DBG(5, "%s stalling, RXCSR %04x\n",
594 musb_ep->end_point.name, csr);
595 return;
596 }
597
598 if (is_cppi_enabled() && musb_ep->dma) {
599 struct dma_controller *c = musb->dma_controller;
600 struct dma_channel *channel = musb_ep->dma;
601
602
603
604
605
606
607 if (c->channel_program(channel,
608 musb_ep->packet_sz,
609 !request->short_not_ok,
610 request->dma + request->actual,
611 request->length - request->actual)) {
612
613
614
615
616
617 csr &= ~(MUSB_RXCSR_AUTOCLEAR
618 | MUSB_RXCSR_DMAMODE);
619 csr |= MUSB_RXCSR_DMAENAB | MUSB_RXCSR_P_WZC_BITS;
620 musb_writew(epio, MUSB_RXCSR, csr);
621 return;
622 }
623 }
624
625 if (csr & MUSB_RXCSR_RXPKTRDY) {
626 len = musb_readw(epio, MUSB_RXCOUNT);
627 if (request->actual < request->length) {
628#ifdef CONFIG_USB_INVENTRA_DMA
629 if (is_dma_capable() && musb_ep->dma) {
630 struct dma_controller *c;
631 struct dma_channel *channel;
632 int use_dma = 0;
633
634 c = musb->dma_controller;
635 channel = musb_ep->dma;
636
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658 csr |= MUSB_RXCSR_DMAENAB;
659#ifdef USE_MODE1
660 csr |= MUSB_RXCSR_AUTOCLEAR;
661
662
663
664
665
666
667 musb_writew(epio, MUSB_RXCSR,
668 csr | MUSB_RXCSR_DMAMODE);
669#endif
670 musb_writew(epio, MUSB_RXCSR, csr);
671
672 if (request->actual < request->length) {
673 int transfer_size = 0;
674#ifdef USE_MODE1
675 transfer_size = min(request->length,
676 channel->max_len);
677#else
678 transfer_size = len;
679#endif
680 if (transfer_size <= musb_ep->packet_sz)
681 musb_ep->dma->desired_mode = 0;
682 else
683 musb_ep->dma->desired_mode = 1;
684
685 use_dma = c->channel_program(
686 channel,
687 musb_ep->packet_sz,
688 channel->desired_mode,
689 request->dma
690 + request->actual,
691 transfer_size);
692 }
693
694 if (use_dma)
695 return;
696 }
697#endif
698
699 fifo_count = request->length - request->actual;
700 DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
701 musb_ep->end_point.name,
702 len, fifo_count,
703 musb_ep->packet_sz);
704
705 fifo_count = min_t(unsigned, len, fifo_count);
706
707#ifdef CONFIG_USB_TUSB_OMAP_DMA
708 if (tusb_dma_omap() && musb_ep->dma) {
709 struct dma_controller *c = musb->dma_controller;
710 struct dma_channel *channel = musb_ep->dma;
711 u32 dma_addr = request->dma + request->actual;
712 int ret;
713
714 ret = c->channel_program(channel,
715 musb_ep->packet_sz,
716 channel->desired_mode,
717 dma_addr,
718 fifo_count);
719 if (ret)
720 return;
721 }
722#endif
723
724 musb_read_fifo(musb_ep->hw_ep, fifo_count, (u8 *)
725 (request->buf + request->actual));
726 request->actual += fifo_count;
727
728
729
730
731
732
733 csr |= MUSB_RXCSR_P_WZC_BITS;
734 csr &= ~MUSB_RXCSR_RXPKTRDY;
735 musb_writew(epio, MUSB_RXCSR, csr);
736 }
737 }
738
739
740 if (request->actual == request->length || len < musb_ep->packet_sz)
741 musb_g_giveback(musb_ep, request, 0);
742}
743
744
745
746
747void musb_g_rx(struct musb *musb, u8 epnum)
748{
749 u16 csr;
750 struct usb_request *request;
751 void __iomem *mbase = musb->mregs;
752 struct musb_ep *musb_ep = &musb->endpoints[epnum].ep_out;
753 void __iomem *epio = musb->endpoints[epnum].regs;
754 struct dma_channel *dma;
755
756 musb_ep_select(mbase, epnum);
757
758 request = next_request(musb_ep);
759
760 csr = musb_readw(epio, MUSB_RXCSR);
761 dma = is_dma_capable() ? musb_ep->dma : NULL;
762
763 DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
764 csr, dma ? " (dma)" : "", request);
765
766 if (csr & MUSB_RXCSR_P_SENTSTALL) {
767 csr |= MUSB_RXCSR_P_WZC_BITS;
768 csr &= ~MUSB_RXCSR_P_SENTSTALL;
769 musb_writew(epio, MUSB_RXCSR, csr);
770 return;
771 }
772
773 if (csr & MUSB_RXCSR_P_OVERRUN) {
774
775 csr &= ~MUSB_RXCSR_P_OVERRUN;
776 musb_writew(epio, MUSB_RXCSR, csr);
777
778 DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
779 if (request && request->status == -EINPROGRESS)
780 request->status = -EOVERFLOW;
781 }
782 if (csr & MUSB_RXCSR_INCOMPRX) {
783
784 DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
785 }
786
787 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
788
789 DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
790 "%s busy, csr %04x\n",
791 musb_ep->end_point.name, csr);
792 return;
793 }
794
795 if (dma && (csr & MUSB_RXCSR_DMAENAB)) {
796 csr &= ~(MUSB_RXCSR_AUTOCLEAR
797 | MUSB_RXCSR_DMAENAB
798 | MUSB_RXCSR_DMAMODE);
799 musb_writew(epio, MUSB_RXCSR,
800 MUSB_RXCSR_P_WZC_BITS | csr);
801
802 request->actual += musb_ep->dma->actual_len;
803
804 DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
805 epnum, csr,
806 musb_readw(epio, MUSB_RXCSR),
807 musb_ep->dma->actual_len, request);
808
809#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
810
811 if ((dma->desired_mode == 0)
812 || (dma->actual_len
813 & (musb_ep->packet_sz - 1))) {
814
815 csr &= ~MUSB_RXCSR_RXPKTRDY;
816 musb_writew(epio, MUSB_RXCSR, csr);
817 }
818
819
820 if ((request->actual < request->length)
821 && (musb_ep->dma->actual_len
822 == musb_ep->packet_sz))
823 return;
824#endif
825 musb_g_giveback(musb_ep, request, 0);
826
827 request = next_request(musb_ep);
828 if (!request)
829 return;
830 }
831
832
833 if (request)
834 rxstate(musb, to_musb_request(request));
835 else
836 DBG(3, "packet waiting for %s%s request\n",
837 musb_ep->desc ? "" : "inactive ",
838 musb_ep->end_point.name);
839 return;
840}
841
842
843
844static int musb_gadget_enable(struct usb_ep *ep,
845 const struct usb_endpoint_descriptor *desc)
846{
847 unsigned long flags;
848 struct musb_ep *musb_ep;
849 struct musb_hw_ep *hw_ep;
850 void __iomem *regs;
851 struct musb *musb;
852 void __iomem *mbase;
853 u8 epnum;
854 u16 csr;
855 unsigned tmp;
856 int status = -EINVAL;
857
858 if (!ep || !desc)
859 return -EINVAL;
860
861 musb_ep = to_musb_ep(ep);
862 hw_ep = musb_ep->hw_ep;
863 regs = hw_ep->regs;
864 musb = musb_ep->musb;
865 mbase = musb->mregs;
866 epnum = musb_ep->current_epnum;
867
868 spin_lock_irqsave(&musb->lock, flags);
869
870 if (musb_ep->desc) {
871 status = -EBUSY;
872 goto fail;
873 }
874 musb_ep->type = usb_endpoint_type(desc);
875
876
877 if (usb_endpoint_num(desc) != epnum)
878 goto fail;
879
880
881 tmp = le16_to_cpu(desc->wMaxPacketSize);
882 if (tmp & ~0x07ff)
883 goto fail;
884 musb_ep->packet_sz = tmp;
885
886
887
888
889 musb_ep_select(mbase, epnum);
890 if (usb_endpoint_dir_in(desc)) {
891 u16 int_txe = musb_readw(mbase, MUSB_INTRTXE);
892
893 if (hw_ep->is_shared_fifo)
894 musb_ep->is_in = 1;
895 if (!musb_ep->is_in)
896 goto fail;
897 if (tmp > hw_ep->max_packet_sz_tx)
898 goto fail;
899
900 int_txe |= (1 << epnum);
901 musb_writew(mbase, MUSB_INTRTXE, int_txe);
902
903
904
905
906 musb_writew(regs, MUSB_TXMAXP, tmp);
907
908 csr = MUSB_TXCSR_MODE | MUSB_TXCSR_CLRDATATOG;
909 if (musb_readw(regs, MUSB_TXCSR)
910 & MUSB_TXCSR_FIFONOTEMPTY)
911 csr |= MUSB_TXCSR_FLUSHFIFO;
912 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
913 csr |= MUSB_TXCSR_P_ISO;
914
915
916 musb_writew(regs, MUSB_TXCSR, csr);
917
918 musb_writew(regs, MUSB_TXCSR, csr);
919
920 } else {
921 u16 int_rxe = musb_readw(mbase, MUSB_INTRRXE);
922
923 if (hw_ep->is_shared_fifo)
924 musb_ep->is_in = 0;
925 if (musb_ep->is_in)
926 goto fail;
927 if (tmp > hw_ep->max_packet_sz_rx)
928 goto fail;
929
930 int_rxe |= (1 << epnum);
931 musb_writew(mbase, MUSB_INTRRXE, int_rxe);
932
933
934
935
936 musb_writew(regs, MUSB_RXMAXP, tmp);
937
938
939 if (hw_ep->is_shared_fifo) {
940 csr = musb_readw(regs, MUSB_TXCSR);
941 csr &= ~(MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY);
942 musb_writew(regs, MUSB_TXCSR, csr);
943 }
944
945 csr = MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_CLRDATATOG;
946 if (musb_ep->type == USB_ENDPOINT_XFER_ISOC)
947 csr |= MUSB_RXCSR_P_ISO;
948 else if (musb_ep->type == USB_ENDPOINT_XFER_INT)
949 csr |= MUSB_RXCSR_DISNYET;
950
951
952 musb_writew(regs, MUSB_RXCSR, csr);
953 musb_writew(regs, MUSB_RXCSR, csr);
954 }
955
956
957
958
959 if (is_dma_capable() && musb->dma_controller) {
960 struct dma_controller *c = musb->dma_controller;
961
962 musb_ep->dma = c->channel_alloc(c, hw_ep,
963 (desc->bEndpointAddress & USB_DIR_IN));
964 } else
965 musb_ep->dma = NULL;
966
967 musb_ep->desc = desc;
968 musb_ep->busy = 0;
969 status = 0;
970
971 pr_debug("%s periph: enabled %s for %s %s, %smaxpacket %d\n",
972 musb_driver_name, musb_ep->end_point.name,
973 ({ char *s; switch (musb_ep->type) {
974 case USB_ENDPOINT_XFER_BULK: s = "bulk"; break;
975 case USB_ENDPOINT_XFER_INT: s = "int"; break;
976 default: s = "iso"; break;
977 }; s; }),
978 musb_ep->is_in ? "IN" : "OUT",
979 musb_ep->dma ? "dma, " : "",
980 musb_ep->packet_sz);
981
982 schedule_work(&musb->irq_work);
983
984fail:
985 spin_unlock_irqrestore(&musb->lock, flags);
986 return status;
987}
988
989
990
991
992static int musb_gadget_disable(struct usb_ep *ep)
993{
994 unsigned long flags;
995 struct musb *musb;
996 u8 epnum;
997 struct musb_ep *musb_ep;
998 void __iomem *epio;
999 int status = 0;
1000
1001 musb_ep = to_musb_ep(ep);
1002 musb = musb_ep->musb;
1003 epnum = musb_ep->current_epnum;
1004 epio = musb->endpoints[epnum].regs;
1005
1006 spin_lock_irqsave(&musb->lock, flags);
1007 musb_ep_select(musb->mregs, epnum);
1008
1009
1010 if (musb_ep->is_in) {
1011 u16 int_txe = musb_readw(musb->mregs, MUSB_INTRTXE);
1012 int_txe &= ~(1 << epnum);
1013 musb_writew(musb->mregs, MUSB_INTRTXE, int_txe);
1014 musb_writew(epio, MUSB_TXMAXP, 0);
1015 } else {
1016 u16 int_rxe = musb_readw(musb->mregs, MUSB_INTRRXE);
1017 int_rxe &= ~(1 << epnum);
1018 musb_writew(musb->mregs, MUSB_INTRRXE, int_rxe);
1019 musb_writew(epio, MUSB_RXMAXP, 0);
1020 }
1021
1022 musb_ep->desc = NULL;
1023
1024
1025 nuke(musb_ep, -ESHUTDOWN);
1026
1027 schedule_work(&musb->irq_work);
1028
1029 spin_unlock_irqrestore(&(musb->lock), flags);
1030
1031 DBG(2, "%s\n", musb_ep->end_point.name);
1032
1033 return status;
1034}
1035
1036
1037
1038
1039
1040struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1041{
1042 struct musb_ep *musb_ep = to_musb_ep(ep);
1043 struct musb_request *request = NULL;
1044
1045 request = kzalloc(sizeof *request, gfp_flags);
1046 if (request) {
1047 INIT_LIST_HEAD(&request->request.list);
1048 request->request.dma = DMA_ADDR_INVALID;
1049 request->epnum = musb_ep->current_epnum;
1050 request->ep = musb_ep;
1051 }
1052
1053 return &request->request;
1054}
1055
1056
1057
1058
1059
1060void musb_free_request(struct usb_ep *ep, struct usb_request *req)
1061{
1062 kfree(to_musb_request(req));
1063}
1064
1065static LIST_HEAD(buffers);
1066
1067struct free_record {
1068 struct list_head list;
1069 struct device *dev;
1070 unsigned bytes;
1071 dma_addr_t dma;
1072};
1073
1074
1075
1076
1077static void musb_ep_restart(struct musb *musb, struct musb_request *req)
1078{
1079 DBG(3, "<== %s request %p len %u on hw_ep%d\n",
1080 req->tx ? "TX/IN" : "RX/OUT",
1081 &req->request, req->request.length, req->epnum);
1082
1083 musb_ep_select(musb->mregs, req->epnum);
1084 if (req->tx)
1085 txstate(musb, req);
1086 else
1087 rxstate(musb, req);
1088}
1089
1090static int musb_gadget_queue(struct usb_ep *ep, struct usb_request *req,
1091 gfp_t gfp_flags)
1092{
1093 struct musb_ep *musb_ep;
1094 struct musb_request *request;
1095 struct musb *musb;
1096 int status = 0;
1097 unsigned long lockflags;
1098
1099 if (!ep || !req)
1100 return -EINVAL;
1101 if (!req->buf)
1102 return -ENODATA;
1103
1104 musb_ep = to_musb_ep(ep);
1105 musb = musb_ep->musb;
1106
1107 request = to_musb_request(req);
1108 request->musb = musb;
1109
1110 if (request->ep != musb_ep)
1111 return -EINVAL;
1112
1113 DBG(4, "<== to %s request=%p\n", ep->name, req);
1114
1115
1116 request->request.actual = 0;
1117 request->request.status = -EINPROGRESS;
1118 request->epnum = musb_ep->current_epnum;
1119 request->tx = musb_ep->is_in;
1120
1121 if (is_dma_capable() && musb_ep->dma) {
1122 if (request->request.dma == DMA_ADDR_INVALID) {
1123 request->request.dma = dma_map_single(
1124 musb->controller,
1125 request->request.buf,
1126 request->request.length,
1127 request->tx
1128 ? DMA_TO_DEVICE
1129 : DMA_FROM_DEVICE);
1130 request->mapped = 1;
1131 } else {
1132 dma_sync_single_for_device(musb->controller,
1133 request->request.dma,
1134 request->request.length,
1135 request->tx
1136 ? DMA_TO_DEVICE
1137 : DMA_FROM_DEVICE);
1138 request->mapped = 0;
1139 }
1140 } else if (!req->buf) {
1141 return -ENODATA;
1142 } else
1143 request->mapped = 0;
1144
1145 spin_lock_irqsave(&musb->lock, lockflags);
1146
1147
1148 if (!musb_ep->desc) {
1149 DBG(4, "req %p queued to %s while ep %s\n",
1150 req, ep->name, "disabled");
1151 status = -ESHUTDOWN;
1152 goto cleanup;
1153 }
1154
1155
1156 list_add_tail(&(request->request.list), &(musb_ep->req_list));
1157
1158
1159 if (!musb_ep->busy && &request->request.list == musb_ep->req_list.next)
1160 musb_ep_restart(musb, request);
1161
1162cleanup:
1163 spin_unlock_irqrestore(&musb->lock, lockflags);
1164 return status;
1165}
1166
1167static int musb_gadget_dequeue(struct usb_ep *ep, struct usb_request *request)
1168{
1169 struct musb_ep *musb_ep = to_musb_ep(ep);
1170 struct usb_request *r;
1171 unsigned long flags;
1172 int status = 0;
1173 struct musb *musb = musb_ep->musb;
1174
1175 if (!ep || !request || to_musb_request(request)->ep != musb_ep)
1176 return -EINVAL;
1177
1178 spin_lock_irqsave(&musb->lock, flags);
1179
1180 list_for_each_entry(r, &musb_ep->req_list, list) {
1181 if (r == request)
1182 break;
1183 }
1184 if (r != request) {
1185 DBG(3, "request %p not queued to %s\n", request, ep->name);
1186 status = -EINVAL;
1187 goto done;
1188 }
1189
1190
1191 if (musb_ep->req_list.next != &request->list || musb_ep->busy)
1192 musb_g_giveback(musb_ep, request, -ECONNRESET);
1193
1194
1195 else if (is_dma_capable() && musb_ep->dma) {
1196 struct dma_controller *c = musb->dma_controller;
1197
1198 musb_ep_select(musb->mregs, musb_ep->current_epnum);
1199 if (c->channel_abort)
1200 status = c->channel_abort(musb_ep->dma);
1201 else
1202 status = -EBUSY;
1203 if (status == 0)
1204 musb_g_giveback(musb_ep, request, -ECONNRESET);
1205 } else {
1206
1207
1208
1209 musb_g_giveback(musb_ep, request, -ECONNRESET);
1210 }
1211
1212done:
1213 spin_unlock_irqrestore(&musb->lock, flags);
1214 return status;
1215}
1216
1217
1218
1219
1220
1221
1222
1223int musb_gadget_set_halt(struct usb_ep *ep, int value)
1224{
1225 struct musb_ep *musb_ep = to_musb_ep(ep);
1226 u8 epnum = musb_ep->current_epnum;
1227 struct musb *musb = musb_ep->musb;
1228 void __iomem *epio = musb->endpoints[epnum].regs;
1229 void __iomem *mbase;
1230 unsigned long flags;
1231 u16 csr;
1232 struct musb_request *request;
1233 int status = 0;
1234
1235 if (!ep)
1236 return -EINVAL;
1237 mbase = musb->mregs;
1238
1239 spin_lock_irqsave(&musb->lock, flags);
1240
1241 if ((USB_ENDPOINT_XFER_ISOC == musb_ep->type)) {
1242 status = -EINVAL;
1243 goto done;
1244 }
1245
1246 musb_ep_select(mbase, epnum);
1247
1248 request = to_musb_request(next_request(musb_ep));
1249 if (value) {
1250 if (request) {
1251 DBG(3, "request in progress, cannot halt %s\n",
1252 ep->name);
1253 status = -EAGAIN;
1254 goto done;
1255 }
1256
1257 if (musb_ep->is_in) {
1258 csr = musb_readw(epio, MUSB_TXCSR);
1259 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1260 DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
1261 status = -EAGAIN;
1262 goto done;
1263 }
1264 }
1265 }
1266
1267
1268 DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
1269 if (musb_ep->is_in) {
1270 csr = musb_readw(epio, MUSB_TXCSR);
1271 csr |= MUSB_TXCSR_P_WZC_BITS
1272 | MUSB_TXCSR_CLRDATATOG;
1273 if (value)
1274 csr |= MUSB_TXCSR_P_SENDSTALL;
1275 else
1276 csr &= ~(MUSB_TXCSR_P_SENDSTALL
1277 | MUSB_TXCSR_P_SENTSTALL);
1278 csr &= ~MUSB_TXCSR_TXPKTRDY;
1279 musb_writew(epio, MUSB_TXCSR, csr);
1280 } else {
1281 csr = musb_readw(epio, MUSB_RXCSR);
1282 csr |= MUSB_RXCSR_P_WZC_BITS
1283 | MUSB_RXCSR_FLUSHFIFO
1284 | MUSB_RXCSR_CLRDATATOG;
1285 if (value)
1286 csr |= MUSB_RXCSR_P_SENDSTALL;
1287 else
1288 csr &= ~(MUSB_RXCSR_P_SENDSTALL
1289 | MUSB_RXCSR_P_SENTSTALL);
1290 musb_writew(epio, MUSB_RXCSR, csr);
1291 }
1292
1293
1294 if (!musb_ep->busy && !value && request) {
1295 DBG(3, "restarting the request\n");
1296 musb_ep_restart(musb, request);
1297 }
1298
1299done:
1300 spin_unlock_irqrestore(&musb->lock, flags);
1301 return status;
1302}
1303
1304static int musb_gadget_fifo_status(struct usb_ep *ep)
1305{
1306 struct musb_ep *musb_ep = to_musb_ep(ep);
1307 void __iomem *epio = musb_ep->hw_ep->regs;
1308 int retval = -EINVAL;
1309
1310 if (musb_ep->desc && !musb_ep->is_in) {
1311 struct musb *musb = musb_ep->musb;
1312 int epnum = musb_ep->current_epnum;
1313 void __iomem *mbase = musb->mregs;
1314 unsigned long flags;
1315
1316 spin_lock_irqsave(&musb->lock, flags);
1317
1318 musb_ep_select(mbase, epnum);
1319
1320 retval = musb_readw(epio, MUSB_RXCOUNT);
1321
1322 spin_unlock_irqrestore(&musb->lock, flags);
1323 }
1324 return retval;
1325}
1326
1327static void musb_gadget_fifo_flush(struct usb_ep *ep)
1328{
1329 struct musb_ep *musb_ep = to_musb_ep(ep);
1330 struct musb *musb = musb_ep->musb;
1331 u8 epnum = musb_ep->current_epnum;
1332 void __iomem *epio = musb->endpoints[epnum].regs;
1333 void __iomem *mbase;
1334 unsigned long flags;
1335 u16 csr, int_txe;
1336
1337 mbase = musb->mregs;
1338
1339 spin_lock_irqsave(&musb->lock, flags);
1340 musb_ep_select(mbase, (u8) epnum);
1341
1342
1343 int_txe = musb_readw(mbase, MUSB_INTRTXE);
1344 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
1345
1346 if (musb_ep->is_in) {
1347 csr = musb_readw(epio, MUSB_TXCSR);
1348 if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
1349 csr |= MUSB_TXCSR_FLUSHFIFO | MUSB_TXCSR_P_WZC_BITS;
1350 musb_writew(epio, MUSB_TXCSR, csr);
1351
1352 musb_writew(epio, MUSB_TXCSR, csr);
1353 }
1354 } else {
1355 csr = musb_readw(epio, MUSB_RXCSR);
1356 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_P_WZC_BITS;
1357 musb_writew(epio, MUSB_RXCSR, csr);
1358 musb_writew(epio, MUSB_RXCSR, csr);
1359 }
1360
1361
1362 musb_writew(mbase, MUSB_INTRTXE, int_txe);
1363 spin_unlock_irqrestore(&musb->lock, flags);
1364}
1365
1366static const struct usb_ep_ops musb_ep_ops = {
1367 .enable = musb_gadget_enable,
1368 .disable = musb_gadget_disable,
1369 .alloc_request = musb_alloc_request,
1370 .free_request = musb_free_request,
1371 .queue = musb_gadget_queue,
1372 .dequeue = musb_gadget_dequeue,
1373 .set_halt = musb_gadget_set_halt,
1374 .fifo_status = musb_gadget_fifo_status,
1375 .fifo_flush = musb_gadget_fifo_flush
1376};
1377
1378
1379
1380static int musb_gadget_get_frame(struct usb_gadget *gadget)
1381{
1382 struct musb *musb = gadget_to_musb(gadget);
1383
1384 return (int)musb_readw(musb->mregs, MUSB_FRAME);
1385}
1386
1387static int musb_gadget_wakeup(struct usb_gadget *gadget)
1388{
1389 struct musb *musb = gadget_to_musb(gadget);
1390 void __iomem *mregs = musb->mregs;
1391 unsigned long flags;
1392 int status = -EINVAL;
1393 u8 power, devctl;
1394 int retries;
1395
1396 spin_lock_irqsave(&musb->lock, flags);
1397
1398 switch (musb->xceiv->state) {
1399 case OTG_STATE_B_PERIPHERAL:
1400
1401
1402
1403
1404 if (musb->may_wakeup && musb->is_suspended)
1405 break;
1406 goto done;
1407 case OTG_STATE_B_IDLE:
1408
1409 devctl = musb_readb(mregs, MUSB_DEVCTL);
1410 DBG(2, "Sending SRP: devctl: %02x\n", devctl);
1411 devctl |= MUSB_DEVCTL_SESSION;
1412 musb_writeb(mregs, MUSB_DEVCTL, devctl);
1413 devctl = musb_readb(mregs, MUSB_DEVCTL);
1414 retries = 100;
1415 while (!(devctl & MUSB_DEVCTL_SESSION)) {
1416 devctl = musb_readb(mregs, MUSB_DEVCTL);
1417 if (retries-- < 1)
1418 break;
1419 }
1420 retries = 10000;
1421 while (devctl & MUSB_DEVCTL_SESSION) {
1422 devctl = musb_readb(mregs, MUSB_DEVCTL);
1423 if (retries-- < 1)
1424 break;
1425 }
1426
1427
1428 musb_platform_try_idle(musb,
1429 jiffies + msecs_to_jiffies(1 * HZ));
1430
1431 status = 0;
1432 goto done;
1433 default:
1434 DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
1435 goto done;
1436 }
1437
1438 status = 0;
1439
1440 power = musb_readb(mregs, MUSB_POWER);
1441 power |= MUSB_POWER_RESUME;
1442 musb_writeb(mregs, MUSB_POWER, power);
1443 DBG(2, "issue wakeup\n");
1444
1445
1446 mdelay(2);
1447
1448 power = musb_readb(mregs, MUSB_POWER);
1449 power &= ~MUSB_POWER_RESUME;
1450 musb_writeb(mregs, MUSB_POWER, power);
1451done:
1452 spin_unlock_irqrestore(&musb->lock, flags);
1453 return status;
1454}
1455
1456static int
1457musb_gadget_set_self_powered(struct usb_gadget *gadget, int is_selfpowered)
1458{
1459 struct musb *musb = gadget_to_musb(gadget);
1460
1461 musb->is_self_powered = !!is_selfpowered;
1462 return 0;
1463}
1464
1465static void musb_pullup(struct musb *musb, int is_on)
1466{
1467 u8 power;
1468
1469 power = musb_readb(musb->mregs, MUSB_POWER);
1470 if (is_on)
1471 power |= MUSB_POWER_SOFTCONN;
1472 else
1473 power &= ~MUSB_POWER_SOFTCONN;
1474
1475
1476
1477 DBG(3, "gadget %s D+ pullup %s\n",
1478 musb->gadget_driver->function, is_on ? "on" : "off");
1479 musb_writeb(musb->mregs, MUSB_POWER, power);
1480}
1481
1482#if 0
1483static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
1484{
1485 DBG(2, "<= %s =>\n", __func__);
1486
1487
1488
1489
1490
1491
1492 return -EINVAL;
1493}
1494#endif
1495
1496static int musb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1497{
1498 struct musb *musb = gadget_to_musb(gadget);
1499
1500 if (!musb->xceiv->set_power)
1501 return -EOPNOTSUPP;
1502 return otg_set_power(musb->xceiv, mA);
1503}
1504
1505static int musb_gadget_pullup(struct usb_gadget *gadget, int is_on)
1506{
1507 struct musb *musb = gadget_to_musb(gadget);
1508 unsigned long flags;
1509
1510 is_on = !!is_on;
1511
1512
1513
1514
1515 spin_lock_irqsave(&musb->lock, flags);
1516 if (is_on != musb->softconnect) {
1517 musb->softconnect = is_on;
1518 musb_pullup(musb, is_on);
1519 }
1520 spin_unlock_irqrestore(&musb->lock, flags);
1521 return 0;
1522}
1523
1524static const struct usb_gadget_ops musb_gadget_operations = {
1525 .get_frame = musb_gadget_get_frame,
1526 .wakeup = musb_gadget_wakeup,
1527 .set_selfpowered = musb_gadget_set_self_powered,
1528
1529 .vbus_draw = musb_gadget_vbus_draw,
1530 .pullup = musb_gadget_pullup,
1531};
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541static struct musb *the_gadget;
1542
1543static void musb_gadget_release(struct device *dev)
1544{
1545
1546 dev_dbg(dev, "%s\n", __func__);
1547}
1548
1549
1550static void __init
1551init_peripheral_ep(struct musb *musb, struct musb_ep *ep, u8 epnum, int is_in)
1552{
1553 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1554
1555 memset(ep, 0, sizeof *ep);
1556
1557 ep->current_epnum = epnum;
1558 ep->musb = musb;
1559 ep->hw_ep = hw_ep;
1560 ep->is_in = is_in;
1561
1562 INIT_LIST_HEAD(&ep->req_list);
1563
1564 sprintf(ep->name, "ep%d%s", epnum,
1565 (!epnum || hw_ep->is_shared_fifo) ? "" : (
1566 is_in ? "in" : "out"));
1567 ep->end_point.name = ep->name;
1568 INIT_LIST_HEAD(&ep->end_point.ep_list);
1569 if (!epnum) {
1570 ep->end_point.maxpacket = 64;
1571 ep->end_point.ops = &musb_g_ep0_ops;
1572 musb->g.ep0 = &ep->end_point;
1573 } else {
1574 if (is_in)
1575 ep->end_point.maxpacket = hw_ep->max_packet_sz_tx;
1576 else
1577 ep->end_point.maxpacket = hw_ep->max_packet_sz_rx;
1578 ep->end_point.ops = &musb_ep_ops;
1579 list_add_tail(&ep->end_point.ep_list, &musb->g.ep_list);
1580 }
1581}
1582
1583
1584
1585
1586
1587static inline void __init musb_g_init_endpoints(struct musb *musb)
1588{
1589 u8 epnum;
1590 struct musb_hw_ep *hw_ep;
1591 unsigned count = 0;
1592
1593
1594 INIT_LIST_HEAD(&(musb->g.ep_list));
1595
1596 for (epnum = 0, hw_ep = musb->endpoints;
1597 epnum < musb->nr_endpoints;
1598 epnum++, hw_ep++) {
1599 if (hw_ep->is_shared_fifo ) {
1600 init_peripheral_ep(musb, &hw_ep->ep_in, epnum, 0);
1601 count++;
1602 } else {
1603 if (hw_ep->max_packet_sz_tx) {
1604 init_peripheral_ep(musb, &hw_ep->ep_in,
1605 epnum, 1);
1606 count++;
1607 }
1608 if (hw_ep->max_packet_sz_rx) {
1609 init_peripheral_ep(musb, &hw_ep->ep_out,
1610 epnum, 0);
1611 count++;
1612 }
1613 }
1614 }
1615}
1616
1617
1618
1619
1620int __init musb_gadget_setup(struct musb *musb)
1621{
1622 int status;
1623
1624
1625
1626
1627
1628 if (the_gadget)
1629 return -EBUSY;
1630 the_gadget = musb;
1631
1632 musb->g.ops = &musb_gadget_operations;
1633 musb->g.is_dualspeed = 1;
1634 musb->g.speed = USB_SPEED_UNKNOWN;
1635
1636
1637 dev_set_name(&musb->g.dev, "gadget");
1638 musb->g.dev.parent = musb->controller;
1639 musb->g.dev.dma_mask = musb->controller->dma_mask;
1640 musb->g.dev.release = musb_gadget_release;
1641 musb->g.name = musb_driver_name;
1642
1643 if (is_otg_enabled(musb))
1644 musb->g.is_otg = 1;
1645
1646 musb_g_init_endpoints(musb);
1647
1648 musb->is_active = 0;
1649 musb_platform_try_idle(musb, 0);
1650
1651 status = device_register(&musb->g.dev);
1652 if (status != 0)
1653 the_gadget = NULL;
1654 return status;
1655}
1656
1657void musb_gadget_cleanup(struct musb *musb)
1658{
1659 if (musb != the_gadget)
1660 return;
1661
1662 device_unregister(&musb->g.dev);
1663 the_gadget = NULL;
1664}
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677int usb_gadget_register_driver(struct usb_gadget_driver *driver)
1678{
1679 int retval;
1680 unsigned long flags;
1681 struct musb *musb = the_gadget;
1682
1683 if (!driver
1684 || driver->speed != USB_SPEED_HIGH
1685 || !driver->bind
1686 || !driver->setup)
1687 return -EINVAL;
1688
1689
1690 if (!musb || !(musb->board_mode == MUSB_OTG
1691 || musb->board_mode != MUSB_OTG)) {
1692 DBG(1, "%s, no dev??\n", __func__);
1693 return -ENODEV;
1694 }
1695
1696 DBG(3, "registering driver %s\n", driver->function);
1697 spin_lock_irqsave(&musb->lock, flags);
1698
1699 if (musb->gadget_driver) {
1700 DBG(1, "%s is already bound to %s\n",
1701 musb_driver_name,
1702 musb->gadget_driver->driver.name);
1703 retval = -EBUSY;
1704 } else {
1705 musb->gadget_driver = driver;
1706 musb->g.dev.driver = &driver->driver;
1707 driver->driver.bus = NULL;
1708 musb->softconnect = 1;
1709 retval = 0;
1710 }
1711
1712 spin_unlock_irqrestore(&musb->lock, flags);
1713
1714 if (retval == 0) {
1715 retval = driver->bind(&musb->g);
1716 if (retval != 0) {
1717 DBG(3, "bind to driver %s failed --> %d\n",
1718 driver->driver.name, retval);
1719 musb->gadget_driver = NULL;
1720 musb->g.dev.driver = NULL;
1721 }
1722
1723 spin_lock_irqsave(&musb->lock, flags);
1724
1725 otg_set_peripheral(musb->xceiv, &musb->g);
1726 musb->is_active = 1;
1727
1728
1729
1730
1731
1732
1733
1734 if (!is_otg_enabled(musb))
1735 musb_start(musb);
1736
1737 otg_set_peripheral(musb->xceiv, &musb->g);
1738
1739 spin_unlock_irqrestore(&musb->lock, flags);
1740
1741 if (is_otg_enabled(musb)) {
1742 DBG(3, "OTG startup...\n");
1743
1744
1745
1746
1747
1748 retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
1749 if (retval < 0) {
1750 DBG(1, "add_hcd failed, %d\n", retval);
1751 spin_lock_irqsave(&musb->lock, flags);
1752 otg_set_peripheral(musb->xceiv, NULL);
1753 musb->gadget_driver = NULL;
1754 musb->g.dev.driver = NULL;
1755 spin_unlock_irqrestore(&musb->lock, flags);
1756 }
1757 }
1758 }
1759
1760 return retval;
1761}
1762EXPORT_SYMBOL(usb_gadget_register_driver);
1763
1764static void stop_activity(struct musb *musb, struct usb_gadget_driver *driver)
1765{
1766 int i;
1767 struct musb_hw_ep *hw_ep;
1768
1769
1770 if (musb->g.speed == USB_SPEED_UNKNOWN)
1771 driver = NULL;
1772 else
1773 musb->g.speed = USB_SPEED_UNKNOWN;
1774
1775
1776 if (musb->softconnect) {
1777 musb->softconnect = 0;
1778 musb_pullup(musb, 0);
1779 }
1780 musb_stop(musb);
1781
1782
1783
1784
1785 if (driver) {
1786 for (i = 0, hw_ep = musb->endpoints;
1787 i < musb->nr_endpoints;
1788 i++, hw_ep++) {
1789 musb_ep_select(musb->mregs, i);
1790 if (hw_ep->is_shared_fifo ) {
1791 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1792 } else {
1793 if (hw_ep->max_packet_sz_tx)
1794 nuke(&hw_ep->ep_in, -ESHUTDOWN);
1795 if (hw_ep->max_packet_sz_rx)
1796 nuke(&hw_ep->ep_out, -ESHUTDOWN);
1797 }
1798 }
1799
1800 spin_unlock(&musb->lock);
1801 driver->disconnect(&musb->g);
1802 spin_lock(&musb->lock);
1803 }
1804}
1805
1806
1807
1808
1809
1810
1811
1812int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
1813{
1814 unsigned long flags;
1815 int retval = 0;
1816 struct musb *musb = the_gadget;
1817
1818 if (!driver || !driver->unbind || !musb)
1819 return -EINVAL;
1820
1821
1822
1823
1824
1825 spin_lock_irqsave(&musb->lock, flags);
1826
1827#ifdef CONFIG_USB_MUSB_OTG
1828 musb_hnp_stop(musb);
1829#endif
1830
1831 if (musb->gadget_driver == driver) {
1832
1833 (void) musb_gadget_vbus_draw(&musb->g, 0);
1834
1835 musb->xceiv->state = OTG_STATE_UNDEFINED;
1836 stop_activity(musb, driver);
1837 otg_set_peripheral(musb->xceiv, NULL);
1838
1839 DBG(3, "unregistering driver %s\n", driver->function);
1840 spin_unlock_irqrestore(&musb->lock, flags);
1841 driver->unbind(&musb->g);
1842 spin_lock_irqsave(&musb->lock, flags);
1843
1844 musb->gadget_driver = NULL;
1845 musb->g.dev.driver = NULL;
1846
1847 musb->is_active = 0;
1848 musb_platform_try_idle(musb, 0);
1849 } else
1850 retval = -EINVAL;
1851 spin_unlock_irqrestore(&musb->lock, flags);
1852
1853 if (is_otg_enabled(musb) && retval == 0) {
1854 usb_remove_hcd(musb_to_hcd(musb));
1855
1856
1857
1858
1859 }
1860
1861 return retval;
1862}
1863EXPORT_SYMBOL(usb_gadget_unregister_driver);
1864
1865
1866
1867
1868
1869
1870void musb_g_resume(struct musb *musb)
1871{
1872 musb->is_suspended = 0;
1873 switch (musb->xceiv->state) {
1874 case OTG_STATE_B_IDLE:
1875 break;
1876 case OTG_STATE_B_WAIT_ACON:
1877 case OTG_STATE_B_PERIPHERAL:
1878 musb->is_active = 1;
1879 if (musb->gadget_driver && musb->gadget_driver->resume) {
1880 spin_unlock(&musb->lock);
1881 musb->gadget_driver->resume(&musb->g);
1882 spin_lock(&musb->lock);
1883 }
1884 break;
1885 default:
1886 WARNING("unhandled RESUME transition (%s)\n",
1887 otg_state_string(musb));
1888 }
1889}
1890
1891
1892void musb_g_suspend(struct musb *musb)
1893{
1894 u8 devctl;
1895
1896 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1897 DBG(3, "devctl %02x\n", devctl);
1898
1899 switch (musb->xceiv->state) {
1900 case OTG_STATE_B_IDLE:
1901 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1902 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1903 break;
1904 case OTG_STATE_B_PERIPHERAL:
1905 musb->is_suspended = 1;
1906 if (musb->gadget_driver && musb->gadget_driver->suspend) {
1907 spin_unlock(&musb->lock);
1908 musb->gadget_driver->suspend(&musb->g);
1909 spin_lock(&musb->lock);
1910 }
1911 break;
1912 default:
1913
1914
1915
1916 WARNING("unhandled SUSPEND transition (%s)\n",
1917 otg_state_string(musb));
1918 }
1919}
1920
1921
1922void musb_g_wakeup(struct musb *musb)
1923{
1924 musb_gadget_wakeup(&musb->g);
1925}
1926
1927
1928void musb_g_disconnect(struct musb *musb)
1929{
1930 void __iomem *mregs = musb->mregs;
1931 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
1932
1933 DBG(3, "devctl %02x\n", devctl);
1934
1935
1936 musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
1937
1938
1939 (void) musb_gadget_vbus_draw(&musb->g, 0);
1940
1941 musb->g.speed = USB_SPEED_UNKNOWN;
1942 if (musb->gadget_driver && musb->gadget_driver->disconnect) {
1943 spin_unlock(&musb->lock);
1944 musb->gadget_driver->disconnect(&musb->g);
1945 spin_lock(&musb->lock);
1946 }
1947
1948 switch (musb->xceiv->state) {
1949 default:
1950#ifdef CONFIG_USB_MUSB_OTG
1951 DBG(2, "Unhandled disconnect %s, setting a_idle\n",
1952 otg_state_string(musb));
1953 musb->xceiv->state = OTG_STATE_A_IDLE;
1954 MUSB_HST_MODE(musb);
1955 break;
1956 case OTG_STATE_A_PERIPHERAL:
1957 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
1958 MUSB_HST_MODE(musb);
1959 break;
1960 case OTG_STATE_B_WAIT_ACON:
1961 case OTG_STATE_B_HOST:
1962#endif
1963 case OTG_STATE_B_PERIPHERAL:
1964 case OTG_STATE_B_IDLE:
1965 musb->xceiv->state = OTG_STATE_B_IDLE;
1966 break;
1967 case OTG_STATE_B_SRP_INIT:
1968 break;
1969 }
1970
1971 musb->is_active = 0;
1972}
1973
1974void musb_g_reset(struct musb *musb)
1975__releases(musb->lock)
1976__acquires(musb->lock)
1977{
1978 void __iomem *mbase = musb->mregs;
1979 u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
1980 u8 power;
1981
1982 DBG(3, "<== %s addr=%x driver '%s'\n",
1983 (devctl & MUSB_DEVCTL_BDEVICE)
1984 ? "B-Device" : "A-Device",
1985 musb_readb(mbase, MUSB_FADDR),
1986 musb->gadget_driver
1987 ? musb->gadget_driver->driver.name
1988 : NULL
1989 );
1990
1991
1992 if (musb->g.speed != USB_SPEED_UNKNOWN)
1993 musb_g_disconnect(musb);
1994
1995
1996 else if (devctl & MUSB_DEVCTL_HR)
1997 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
1998
1999
2000
2001 power = musb_readb(mbase, MUSB_POWER);
2002 musb->g.speed = (power & MUSB_POWER_HSMODE)
2003 ? USB_SPEED_HIGH : USB_SPEED_FULL;
2004
2005
2006 musb->is_active = 1;
2007 musb->is_suspended = 0;
2008 MUSB_DEV_MODE(musb);
2009 musb->address = 0;
2010 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
2011
2012 musb->may_wakeup = 0;
2013 musb->g.b_hnp_enable = 0;
2014 musb->g.a_alt_hnp_support = 0;
2015 musb->g.a_hnp_support = 0;
2016
2017
2018
2019
2020 if (devctl & MUSB_DEVCTL_BDEVICE) {
2021 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
2022 musb->g.is_a_peripheral = 0;
2023 } else if (is_otg_enabled(musb)) {
2024 musb->xceiv->state = OTG_STATE_A_PERIPHERAL;
2025 musb->g.is_a_peripheral = 1;
2026 } else
2027 WARN_ON(1);
2028
2029
2030 (void) musb_gadget_vbus_draw(&musb->g,
2031 is_otg_enabled(musb) ? 8 : 100);
2032}
2033