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36#include <linux/kernel.h>
37#include <linux/list.h>
38#include <linux/timer.h>
39#include <linux/spinlock.h>
40#include <linux/init.h>
41#include <linux/device.h>
42#include <linux/interrupt.h>
43
44#include "musb_core.h"
45
46
47#define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
48
49
50
51
52
53
54
55
56
57
58
59static char *decode_ep0stage(u8 stage)
60{
61 switch (stage) {
62 case MUSB_EP0_STAGE_IDLE: return "idle";
63 case MUSB_EP0_STAGE_SETUP: return "setup";
64 case MUSB_EP0_STAGE_TX: return "in";
65 case MUSB_EP0_STAGE_RX: return "out";
66 case MUSB_EP0_STAGE_ACKWAIT: return "wait";
67 case MUSB_EP0_STAGE_STATUSIN: return "in/status";
68 case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
69 default: return "?";
70 }
71}
72
73
74
75
76static int service_tx_status_request(
77 struct musb *musb,
78 const struct usb_ctrlrequest *ctrlrequest)
79{
80 void __iomem *mbase = musb->mregs;
81 int handled = 1;
82 u8 result[2], epnum = 0;
83 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
84
85 result[1] = 0;
86
87 switch (recip) {
88 case USB_RECIP_DEVICE:
89 result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
90 result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
91#ifdef CONFIG_USB_MUSB_OTG
92 if (musb->g.is_otg) {
93 result[0] |= musb->g.b_hnp_enable
94 << USB_DEVICE_B_HNP_ENABLE;
95 result[0] |= musb->g.a_alt_hnp_support
96 << USB_DEVICE_A_ALT_HNP_SUPPORT;
97 result[0] |= musb->g.a_hnp_support
98 << USB_DEVICE_A_HNP_SUPPORT;
99 }
100#endif
101 break;
102
103 case USB_RECIP_INTERFACE:
104 result[0] = 0;
105 break;
106
107 case USB_RECIP_ENDPOINT: {
108 int is_in;
109 struct musb_ep *ep;
110 u16 tmp;
111 void __iomem *regs;
112
113 epnum = (u8) ctrlrequest->wIndex;
114 if (!epnum) {
115 result[0] = 0;
116 break;
117 }
118
119 is_in = epnum & USB_DIR_IN;
120 if (is_in) {
121 epnum &= 0x0f;
122 ep = &musb->endpoints[epnum].ep_in;
123 } else {
124 ep = &musb->endpoints[epnum].ep_out;
125 }
126 regs = musb->endpoints[epnum].regs;
127
128 if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
129 handled = -EINVAL;
130 break;
131 }
132
133 musb_ep_select(mbase, epnum);
134 if (is_in)
135 tmp = musb_readw(regs, MUSB_TXCSR)
136 & MUSB_TXCSR_P_SENDSTALL;
137 else
138 tmp = musb_readw(regs, MUSB_RXCSR)
139 & MUSB_RXCSR_P_SENDSTALL;
140 musb_ep_select(mbase, 0);
141
142 result[0] = tmp ? 1 : 0;
143 } break;
144
145 default:
146
147 handled = 0;
148 break;
149 }
150
151
152 if (handled > 0) {
153 u16 len = le16_to_cpu(ctrlrequest->wLength);
154
155 if (len > 2)
156 len = 2;
157 musb_write_fifo(&musb->endpoints[0], len, result);
158 }
159
160 return handled;
161}
162
163
164
165
166
167
168
169
170
171
172
173
174static int
175service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
176{
177 int handled = 0;
178
179 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
180 == USB_TYPE_STANDARD) {
181 switch (ctrlrequest->bRequest) {
182 case USB_REQ_GET_STATUS:
183 handled = service_tx_status_request(musb,
184 ctrlrequest);
185 break;
186
187
188
189 default:
190 break;
191 }
192 }
193 return handled;
194}
195
196
197
198
199static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
200{
201 musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
202 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
203}
204
205
206
207
208static inline void musb_try_b_hnp_enable(struct musb *musb)
209{
210 void __iomem *mbase = musb->mregs;
211 u8 devctl;
212
213 DBG(1, "HNP: Setting HR\n");
214 devctl = musb_readb(mbase, MUSB_DEVCTL);
215 musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
216}
217
218
219
220
221
222
223
224
225
226
227
228static int
229service_zero_data_request(struct musb *musb,
230 struct usb_ctrlrequest *ctrlrequest)
231__releases(musb->lock)
232__acquires(musb->lock)
233{
234 int handled = -EINVAL;
235 void __iomem *mbase = musb->mregs;
236 const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
237
238
239 if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
240 == USB_TYPE_STANDARD) {
241 switch (ctrlrequest->bRequest) {
242 case USB_REQ_SET_ADDRESS:
243
244 musb->set_address = true;
245 musb->address = (u8) (ctrlrequest->wValue & 0x7f);
246 handled = 1;
247 break;
248
249 case USB_REQ_CLEAR_FEATURE:
250 switch (recip) {
251 case USB_RECIP_DEVICE:
252 if (ctrlrequest->wValue
253 != USB_DEVICE_REMOTE_WAKEUP)
254 break;
255 musb->may_wakeup = 0;
256 handled = 1;
257 break;
258 case USB_RECIP_INTERFACE:
259 break;
260 case USB_RECIP_ENDPOINT:{
261 const u8 num = ctrlrequest->wIndex & 0x0f;
262 struct musb_ep *musb_ep;
263
264 if (num == 0
265 || num >= MUSB_C_NUM_EPS
266 || ctrlrequest->wValue
267 != USB_ENDPOINT_HALT)
268 break;
269
270 if (ctrlrequest->wIndex & USB_DIR_IN)
271 musb_ep = &musb->endpoints[num].ep_in;
272 else
273 musb_ep = &musb->endpoints[num].ep_out;
274 if (!musb_ep->desc)
275 break;
276
277
278 spin_unlock(&musb->lock);
279 musb_gadget_set_halt(&musb_ep->end_point, 0);
280 spin_lock(&musb->lock);
281
282
283 musb_ep_select(mbase, 0);
284 handled = 1;
285 } break;
286 default:
287
288 handled = 0;
289 break;
290 }
291 break;
292
293 case USB_REQ_SET_FEATURE:
294 switch (recip) {
295 case USB_RECIP_DEVICE:
296 handled = 1;
297 switch (ctrlrequest->wValue) {
298 case USB_DEVICE_REMOTE_WAKEUP:
299 musb->may_wakeup = 1;
300 break;
301 case USB_DEVICE_TEST_MODE:
302 if (musb->g.speed != USB_SPEED_HIGH)
303 goto stall;
304 if (ctrlrequest->wIndex & 0xff)
305 goto stall;
306
307 switch (ctrlrequest->wIndex >> 8) {
308 case 1:
309 pr_debug("TEST_J\n");
310
311 musb->test_mode_nr =
312 MUSB_TEST_J;
313 break;
314 case 2:
315
316 pr_debug("TEST_K\n");
317 musb->test_mode_nr =
318 MUSB_TEST_K;
319 break;
320 case 3:
321
322 pr_debug("TEST_SE0_NAK\n");
323 musb->test_mode_nr =
324 MUSB_TEST_SE0_NAK;
325 break;
326 case 4:
327
328 pr_debug("TEST_PACKET\n");
329 musb->test_mode_nr =
330 MUSB_TEST_PACKET;
331 break;
332 default:
333 goto stall;
334 }
335
336
337 if (handled > 0)
338 musb->test_mode = true;
339 break;
340#ifdef CONFIG_USB_MUSB_OTG
341 case USB_DEVICE_B_HNP_ENABLE:
342 if (!musb->g.is_otg)
343 goto stall;
344 musb->g.b_hnp_enable = 1;
345 musb_try_b_hnp_enable(musb);
346 break;
347 case USB_DEVICE_A_HNP_SUPPORT:
348 if (!musb->g.is_otg)
349 goto stall;
350 musb->g.a_hnp_support = 1;
351 break;
352 case USB_DEVICE_A_ALT_HNP_SUPPORT:
353 if (!musb->g.is_otg)
354 goto stall;
355 musb->g.a_alt_hnp_support = 1;
356 break;
357#endif
358stall:
359 default:
360 handled = -EINVAL;
361 break;
362 }
363 break;
364
365 case USB_RECIP_INTERFACE:
366 break;
367
368 case USB_RECIP_ENDPOINT:{
369 const u8 epnum =
370 ctrlrequest->wIndex & 0x0f;
371 struct musb_ep *musb_ep;
372 struct musb_hw_ep *ep;
373 void __iomem *regs;
374 int is_in;
375 u16 csr;
376
377 if (epnum == 0
378 || epnum >= MUSB_C_NUM_EPS
379 || ctrlrequest->wValue
380 != USB_ENDPOINT_HALT)
381 break;
382
383 ep = musb->endpoints + epnum;
384 regs = ep->regs;
385 is_in = ctrlrequest->wIndex & USB_DIR_IN;
386 if (is_in)
387 musb_ep = &ep->ep_in;
388 else
389 musb_ep = &ep->ep_out;
390 if (!musb_ep->desc)
391 break;
392
393 musb_ep_select(mbase, epnum);
394 if (is_in) {
395 csr = musb_readw(regs,
396 MUSB_TXCSR);
397 if (csr & MUSB_TXCSR_FIFONOTEMPTY)
398 csr |= MUSB_TXCSR_FLUSHFIFO;
399 csr |= MUSB_TXCSR_P_SENDSTALL
400 | MUSB_TXCSR_CLRDATATOG
401 | MUSB_TXCSR_P_WZC_BITS;
402 musb_writew(regs, MUSB_TXCSR,
403 csr);
404 } else {
405 csr = musb_readw(regs,
406 MUSB_RXCSR);
407 csr |= MUSB_RXCSR_P_SENDSTALL
408 | MUSB_RXCSR_FLUSHFIFO
409 | MUSB_RXCSR_CLRDATATOG
410 | MUSB_RXCSR_P_WZC_BITS;
411 musb_writew(regs, MUSB_RXCSR,
412 csr);
413 }
414
415
416 musb_ep_select(mbase, 0);
417 handled = 1;
418 } break;
419
420 default:
421
422 handled = 0;
423 break;
424 }
425 break;
426 default:
427
428 handled = 0;
429 }
430 } else
431 handled = 0;
432 return handled;
433}
434
435
436
437
438static void ep0_rxstate(struct musb *musb)
439{
440 void __iomem *regs = musb->control_ep->regs;
441 struct usb_request *req;
442 u16 count, csr;
443
444 req = next_ep0_request(musb);
445
446
447
448
449 if (req) {
450 void *buf = req->buf + req->actual;
451 unsigned len = req->length - req->actual;
452
453
454 count = musb_readb(regs, MUSB_COUNT0);
455 if (count > len) {
456 req->status = -EOVERFLOW;
457 count = len;
458 }
459 musb_read_fifo(&musb->endpoints[0], count, buf);
460 req->actual += count;
461 csr = MUSB_CSR0_P_SVDRXPKTRDY;
462 if (count < 64 || req->actual == req->length) {
463 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
464 csr |= MUSB_CSR0_P_DATAEND;
465 } else
466 req = NULL;
467 } else
468 csr = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
469
470
471
472
473
474 if (req) {
475 musb->ackpend = csr;
476 musb_g_ep0_giveback(musb, req);
477 if (!musb->ackpend)
478 return;
479 musb->ackpend = 0;
480 }
481 musb_ep_select(musb->mregs, 0);
482 musb_writew(regs, MUSB_CSR0, csr);
483}
484
485
486
487
488
489
490
491static void ep0_txstate(struct musb *musb)
492{
493 void __iomem *regs = musb->control_ep->regs;
494 struct usb_request *request = next_ep0_request(musb);
495 u16 csr = MUSB_CSR0_TXPKTRDY;
496 u8 *fifo_src;
497 u8 fifo_count;
498
499 if (!request) {
500
501 DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
502 return;
503 }
504
505
506 fifo_src = (u8 *) request->buf + request->actual;
507 fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
508 request->length - request->actual);
509 musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
510 request->actual += fifo_count;
511
512
513 if (fifo_count < MUSB_MAX_END0_PACKET
514 || (request->actual == request->length
515 && !request->zero)) {
516 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
517 csr |= MUSB_CSR0_P_DATAEND;
518 } else
519 request = NULL;
520
521
522
523
524
525
526 if (request) {
527 musb->ackpend = csr;
528 musb_g_ep0_giveback(musb, request);
529 if (!musb->ackpend)
530 return;
531 musb->ackpend = 0;
532 }
533
534
535 musb_ep_select(musb->mregs, 0);
536 musb_writew(regs, MUSB_CSR0, csr);
537}
538
539
540
541
542
543
544
545static void
546musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
547{
548 struct usb_request *r;
549 void __iomem *regs = musb->control_ep->regs;
550
551 musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
552
553
554
555
556 DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
557 req->bRequestType,
558 req->bRequest,
559 le16_to_cpu(req->wValue),
560 le16_to_cpu(req->wIndex),
561 le16_to_cpu(req->wLength));
562
563
564 r = next_ep0_request(musb);
565 if (r)
566 musb_g_ep0_giveback(musb, r);
567
568
569
570
571
572
573
574
575
576 musb->set_address = false;
577 musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
578 if (req->wLength == 0) {
579 if (req->bRequestType & USB_DIR_IN)
580 musb->ackpend |= MUSB_CSR0_TXPKTRDY;
581 musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
582 } else if (req->bRequestType & USB_DIR_IN) {
583 musb->ep0_state = MUSB_EP0_STAGE_TX;
584 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
585 while ((musb_readw(regs, MUSB_CSR0)
586 & MUSB_CSR0_RXPKTRDY) != 0)
587 cpu_relax();
588 musb->ackpend = 0;
589 } else
590 musb->ep0_state = MUSB_EP0_STAGE_RX;
591}
592
593static int
594forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
595__releases(musb->lock)
596__acquires(musb->lock)
597{
598 int retval;
599 if (!musb->gadget_driver)
600 return -EOPNOTSUPP;
601 spin_unlock(&musb->lock);
602 retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
603 spin_lock(&musb->lock);
604 return retval;
605}
606
607
608
609
610
611
612irqreturn_t musb_g_ep0_irq(struct musb *musb)
613{
614 u16 csr;
615 u16 len;
616 void __iomem *mbase = musb->mregs;
617 void __iomem *regs = musb->endpoints[0].regs;
618 irqreturn_t retval = IRQ_NONE;
619
620 musb_ep_select(mbase, 0);
621 csr = musb_readw(regs, MUSB_CSR0);
622 len = musb_readb(regs, MUSB_COUNT0);
623
624 DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
625 csr, len,
626 musb_readb(mbase, MUSB_FADDR),
627 decode_ep0stage(musb->ep0_state));
628
629
630 if (csr & MUSB_CSR0_P_SENTSTALL) {
631 musb_writew(regs, MUSB_CSR0,
632 csr & ~MUSB_CSR0_P_SENTSTALL);
633 retval = IRQ_HANDLED;
634 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
635 csr = musb_readw(regs, MUSB_CSR0);
636 }
637
638
639 if (csr & MUSB_CSR0_P_SETUPEND) {
640 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
641 retval = IRQ_HANDLED;
642
643 switch (musb->ep0_state) {
644 case MUSB_EP0_STAGE_TX:
645 musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
646 break;
647 case MUSB_EP0_STAGE_RX:
648 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
649 break;
650 default:
651 ERR("SetupEnd came in a wrong ep0stage %s",
652 decode_ep0stage(musb->ep0_state));
653 }
654 csr = musb_readw(regs, MUSB_CSR0);
655
656 }
657
658
659
660
661
662 switch (musb->ep0_state) {
663
664 case MUSB_EP0_STAGE_TX:
665
666 if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
667 ep0_txstate(musb);
668 retval = IRQ_HANDLED;
669 }
670 break;
671
672 case MUSB_EP0_STAGE_RX:
673
674 if (csr & MUSB_CSR0_RXPKTRDY) {
675 ep0_rxstate(musb);
676 retval = IRQ_HANDLED;
677 }
678 break;
679
680 case MUSB_EP0_STAGE_STATUSIN:
681
682
683
684
685
686
687
688 if (musb->set_address) {
689 musb->set_address = false;
690 musb_writeb(mbase, MUSB_FADDR, musb->address);
691 }
692
693
694 else if (musb->test_mode) {
695 DBG(1, "entering TESTMODE\n");
696
697 if (MUSB_TEST_PACKET == musb->test_mode_nr)
698 musb_load_testpacket(musb);
699
700 musb_writeb(mbase, MUSB_TESTMODE,
701 musb->test_mode_nr);
702 }
703
704
705 case MUSB_EP0_STAGE_STATUSOUT:
706
707 {
708 struct usb_request *req;
709
710 req = next_ep0_request(musb);
711 if (req)
712 musb_g_ep0_giveback(musb, req);
713 }
714
715
716
717
718
719 if (csr & MUSB_CSR0_RXPKTRDY)
720 goto setup;
721
722 retval = IRQ_HANDLED;
723 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
724 break;
725
726 case MUSB_EP0_STAGE_IDLE:
727
728
729
730
731
732
733 retval = IRQ_HANDLED;
734 musb->ep0_state = MUSB_EP0_STAGE_SETUP;
735
736
737 case MUSB_EP0_STAGE_SETUP:
738setup:
739 if (csr & MUSB_CSR0_RXPKTRDY) {
740 struct usb_ctrlrequest setup;
741 int handled = 0;
742
743 if (len != 8) {
744 ERR("SETUP packet len %d != 8 ?\n", len);
745 break;
746 }
747 musb_read_setup(musb, &setup);
748 retval = IRQ_HANDLED;
749
750
751 if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
752 u8 power;
753
754 printk(KERN_NOTICE "%s: peripheral reset "
755 "irq lost!\n",
756 musb_driver_name);
757 power = musb_readb(mbase, MUSB_POWER);
758 musb->g.speed = (power & MUSB_POWER_HSMODE)
759 ? USB_SPEED_HIGH : USB_SPEED_FULL;
760
761 }
762
763 switch (musb->ep0_state) {
764
765
766
767
768
769
770 case MUSB_EP0_STAGE_ACKWAIT:
771 handled = service_zero_data_request(
772 musb, &setup);
773
774
775 if (handled > 0) {
776 musb->ackpend |= MUSB_CSR0_P_DATAEND;
777 musb->ep0_state =
778 MUSB_EP0_STAGE_STATUSIN;
779 }
780 break;
781
782
783
784
785
786 case MUSB_EP0_STAGE_TX:
787 handled = service_in_request(musb, &setup);
788 if (handled > 0) {
789 musb->ackpend = MUSB_CSR0_TXPKTRDY
790 | MUSB_CSR0_P_DATAEND;
791 musb->ep0_state =
792 MUSB_EP0_STAGE_STATUSOUT;
793 }
794 break;
795
796
797 default:
798 break;
799 }
800
801 DBG(3, "handled %d, csr %04x, ep0stage %s\n",
802 handled, csr,
803 decode_ep0stage(musb->ep0_state));
804
805
806
807
808
809 if (handled < 0)
810 goto stall;
811 else if (handled > 0)
812 goto finish;
813
814 handled = forward_to_driver(musb, &setup);
815 if (handled < 0) {
816 musb_ep_select(mbase, 0);
817stall:
818 DBG(3, "stall (%d)\n", handled);
819 musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
820 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
821finish:
822 musb_writew(regs, MUSB_CSR0,
823 musb->ackpend);
824 musb->ackpend = 0;
825 }
826 }
827 break;
828
829 case MUSB_EP0_STAGE_ACKWAIT:
830
831
832
833 retval = IRQ_HANDLED;
834 break;
835
836 default:
837
838 WARN_ON(1);
839 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
840 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
841 break;
842 }
843
844 return retval;
845}
846
847
848static int
849musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
850{
851
852 return -EINVAL;
853}
854
855static int musb_g_ep0_disable(struct usb_ep *e)
856{
857
858 return -EINVAL;
859}
860
861static int
862musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
863{
864 struct musb_ep *ep;
865 struct musb_request *req;
866 struct musb *musb;
867 int status;
868 unsigned long lockflags;
869 void __iomem *regs;
870
871 if (!e || !r)
872 return -EINVAL;
873
874 ep = to_musb_ep(e);
875 musb = ep->musb;
876 regs = musb->control_ep->regs;
877
878 req = to_musb_request(r);
879 req->musb = musb;
880 req->request.actual = 0;
881 req->request.status = -EINPROGRESS;
882 req->tx = ep->is_in;
883
884 spin_lock_irqsave(&musb->lock, lockflags);
885
886 if (!list_empty(&ep->req_list)) {
887 status = -EBUSY;
888 goto cleanup;
889 }
890
891 switch (musb->ep0_state) {
892 case MUSB_EP0_STAGE_RX:
893 case MUSB_EP0_STAGE_TX:
894 case MUSB_EP0_STAGE_ACKWAIT:
895 status = 0;
896 break;
897 default:
898 DBG(1, "ep0 request queued in state %d\n",
899 musb->ep0_state);
900 status = -EINVAL;
901 goto cleanup;
902 }
903
904
905 list_add_tail(&(req->request.list), &(ep->req_list));
906
907 DBG(3, "queue to %s (%s), length=%d\n",
908 ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
909 req->request.length);
910
911 musb_ep_select(musb->mregs, 0);
912
913
914 if (musb->ep0_state == MUSB_EP0_STAGE_TX)
915 ep0_txstate(musb);
916
917
918 else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
919 if (req->request.length)
920 status = -EINVAL;
921 else {
922 musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
923 musb_writew(regs, MUSB_CSR0,
924 musb->ackpend | MUSB_CSR0_P_DATAEND);
925 musb->ackpend = 0;
926 musb_g_ep0_giveback(ep->musb, r);
927 }
928
929
930
931
932
933 } else if (musb->ackpend) {
934 musb_writew(regs, MUSB_CSR0, musb->ackpend);
935 musb->ackpend = 0;
936 }
937
938cleanup:
939 spin_unlock_irqrestore(&musb->lock, lockflags);
940 return status;
941}
942
943static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
944{
945
946 return -EINVAL;
947}
948
949static int musb_g_ep0_halt(struct usb_ep *e, int value)
950{
951 struct musb_ep *ep;
952 struct musb *musb;
953 void __iomem *base, *regs;
954 unsigned long flags;
955 int status;
956 u16 csr;
957
958 if (!e || !value)
959 return -EINVAL;
960
961 ep = to_musb_ep(e);
962 musb = ep->musb;
963 base = musb->mregs;
964 regs = musb->control_ep->regs;
965 status = 0;
966
967 spin_lock_irqsave(&musb->lock, flags);
968
969 if (!list_empty(&ep->req_list)) {
970 status = -EBUSY;
971 goto cleanup;
972 }
973
974 musb_ep_select(base, 0);
975 csr = musb->ackpend;
976
977 switch (musb->ep0_state) {
978
979
980
981
982 case MUSB_EP0_STAGE_TX:
983 case MUSB_EP0_STAGE_ACKWAIT:
984 case MUSB_EP0_STAGE_RX:
985 csr = musb_readw(regs, MUSB_CSR0);
986
987
988
989
990
991 case MUSB_EP0_STAGE_STATUSIN:
992 case MUSB_EP0_STAGE_STATUSOUT:
993
994 csr |= MUSB_CSR0_P_SENDSTALL;
995 musb_writew(regs, MUSB_CSR0, csr);
996 musb->ep0_state = MUSB_EP0_STAGE_IDLE;
997 musb->ackpend = 0;
998 break;
999 default:
1000 DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
1001 status = -EINVAL;
1002 }
1003
1004cleanup:
1005 spin_unlock_irqrestore(&musb->lock, flags);
1006 return status;
1007}
1008
1009const struct usb_ep_ops musb_g_ep0_ops = {
1010 .enable = musb_g_ep0_enable,
1011 .disable = musb_g_ep0_disable,
1012 .alloc_request = musb_alloc_request,
1013 .free_request = musb_free_request,
1014 .queue = musb_g_ep0_queue,
1015 .dequeue = musb_g_ep0_dequeue,
1016 .set_halt = musb_g_ep0_halt,
1017};
1018