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32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/errno.h>
35#include <linux/string.h>
36#include <linux/mm.h>
37#include <linux/slab.h>
38#include <linux/delay.h>
39#include <linux/fb.h>
40#include <linux/init.h>
41#include <linux/pci.h>
42#include <linux/backlight.h>
43#include <linux/bitrev.h>
44#ifdef CONFIG_MTRR
45#include <asm/mtrr.h>
46#endif
47#ifdef CONFIG_PPC_OF
48#include <asm/prom.h>
49#include <asm/pci-bridge.h>
50#endif
51#ifdef CONFIG_PMAC_BACKLIGHT
52#include <asm/machdep.h>
53#include <asm/backlight.h>
54#endif
55
56#include "rivafb.h"
57#include "nvreg.h"
58
59
60#define RIVAFB_VERSION "0.9.5b"
61
62
63
64
65
66
67#ifdef CONFIG_FB_RIVA_DEBUG
68#define NVTRACE printk
69#else
70#define NVTRACE if(0) printk
71#endif
72
73#define NVTRACE_ENTER(...) NVTRACE("%s START\n", __func__)
74#define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __func__)
75
76#ifdef CONFIG_FB_RIVA_DEBUG
77#define assert(expr) \
78 if(!(expr)) { \
79 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
80 #expr,__FILE__,__func__,__LINE__); \
81 BUG(); \
82 }
83#else
84#define assert(expr)
85#endif
86
87#define PFX "rivafb: "
88
89
90#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
91#define SetBit(n) (1<<(n))
92#define Set8Bits(value) ((value)&0xff)
93
94
95#define MAX_CURS 32
96
97
98
99
100
101
102
103static int rivafb_blank(int blank, struct fb_info *info);
104
105
106
107
108
109
110
111static struct pci_device_id rivafb_pci_tbl[] = {
112 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152
153 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
155 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
157 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { 0, }
198};
199MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
200
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207
208static int flatpanel __devinitdata = -1;
209static int forceCRTC __devinitdata = -1;
210static int noaccel __devinitdata = 0;
211#ifdef CONFIG_MTRR
212static int nomtrr __devinitdata = 0;
213#endif
214#ifdef CONFIG_PMAC_BACKLIGHT
215static int backlight __devinitdata = 1;
216#else
217static int backlight __devinitdata = 0;
218#endif
219
220static char *mode_option __devinitdata = NULL;
221static int strictmode = 0;
222
223static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
224 .type = FB_TYPE_PACKED_PIXELS,
225 .xpanstep = 1,
226 .ypanstep = 1,
227};
228
229static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
230 .xres = 640,
231 .yres = 480,
232 .xres_virtual = 640,
233 .yres_virtual = 480,
234 .bits_per_pixel = 8,
235 .red = {0, 8, 0},
236 .green = {0, 8, 0},
237 .blue = {0, 8, 0},
238 .transp = {0, 0, 0},
239 .activate = FB_ACTIVATE_NOW,
240 .height = -1,
241 .width = -1,
242 .pixclock = 39721,
243 .left_margin = 40,
244 .right_margin = 24,
245 .upper_margin = 32,
246 .lower_margin = 11,
247 .hsync_len = 96,
248 .vsync_len = 2,
249 .vmode = FB_VMODE_NONINTERLACED
250};
251
252
253static const struct riva_regs reg_template = {
254 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
255 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
256 0x41, 0x01, 0x0F, 0x00, 0x00},
257 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
259 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3,
260 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
261 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
264 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
265 0x00,
266 },
267 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F,
268 0xFF},
269 {0x03, 0x01, 0x0F, 0x00, 0x0E},
270 0xEB
271};
272
273
274
275
276#ifdef CONFIG_FB_RIVA_BACKLIGHT
277
278
279
280#define MIN_LEVEL 0x158
281#define MAX_LEVEL 0x534
282#define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
283
284static int riva_bl_get_level_brightness(struct riva_par *par,
285 int level)
286{
287 struct fb_info *info = pci_get_drvdata(par->pdev);
288 int nlevel;
289
290
291
292 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
293
294 if (nlevel < 0)
295 nlevel = 0;
296 else if (nlevel < MIN_LEVEL)
297 nlevel = MIN_LEVEL;
298 else if (nlevel > MAX_LEVEL)
299 nlevel = MAX_LEVEL;
300
301 return nlevel;
302}
303
304static int riva_bl_update_status(struct backlight_device *bd)
305{
306 struct riva_par *par = bl_get_data(bd);
307 U032 tmp_pcrt, tmp_pmc;
308 int level;
309
310 if (bd->props.power != FB_BLANK_UNBLANK ||
311 bd->props.fb_blank != FB_BLANK_UNBLANK)
312 level = 0;
313 else
314 level = bd->props.brightness;
315
316 tmp_pmc = NV_RD32(par->riva.PMC, 0x10F0) & 0x0000FFFF;
317 tmp_pcrt = NV_RD32(par->riva.PCRTC0, 0x081C) & 0xFFFFFFFC;
318 if(level > 0) {
319 tmp_pcrt |= 0x1;
320 tmp_pmc |= (1 << 31);
321 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16;
322 }
323 NV_WR32(par->riva.PCRTC0, 0x081C, tmp_pcrt);
324 NV_WR32(par->riva.PMC, 0x10F0, tmp_pmc);
325
326 return 0;
327}
328
329static int riva_bl_get_brightness(struct backlight_device *bd)
330{
331 return bd->props.brightness;
332}
333
334static struct backlight_ops riva_bl_ops = {
335 .get_brightness = riva_bl_get_brightness,
336 .update_status = riva_bl_update_status,
337};
338
339static void riva_bl_init(struct riva_par *par)
340{
341 struct fb_info *info = pci_get_drvdata(par->pdev);
342 struct backlight_device *bd;
343 char name[12];
344
345 if (!par->FlatPanel)
346 return;
347
348#ifdef CONFIG_PMAC_BACKLIGHT
349 if (!machine_is(powermac) ||
350 !pmac_has_backlight_type("mnca"))
351 return;
352#endif
353
354 snprintf(name, sizeof(name), "rivabl%d", info->node);
355
356 bd = backlight_device_register(name, info->dev, par, &riva_bl_ops);
357 if (IS_ERR(bd)) {
358 info->bl_dev = NULL;
359 printk(KERN_WARNING "riva: Backlight registration failed\n");
360 goto error;
361 }
362
363 info->bl_dev = bd;
364 fb_bl_default_curve(info, 0,
365 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
366 FB_BACKLIGHT_MAX);
367
368 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
369 bd->props.brightness = bd->props.max_brightness;
370 bd->props.power = FB_BLANK_UNBLANK;
371 backlight_update_status(bd);
372
373 printk("riva: Backlight initialized (%s)\n", name);
374
375 return;
376
377error:
378 return;
379}
380
381static void riva_bl_exit(struct fb_info *info)
382{
383 struct backlight_device *bd = info->bl_dev;
384
385 backlight_device_unregister(bd);
386 printk("riva: Backlight unloaded\n");
387}
388#else
389static inline void riva_bl_init(struct riva_par *par) {}
390static inline void riva_bl_exit(struct fb_info *info) {}
391#endif
392
393
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396
397
398
399static inline void CRTCout(struct riva_par *par, unsigned char index,
400 unsigned char val)
401{
402 VGA_WR08(par->riva.PCIO, 0x3d4, index);
403 VGA_WR08(par->riva.PCIO, 0x3d5, val);
404}
405
406static inline unsigned char CRTCin(struct riva_par *par,
407 unsigned char index)
408{
409 VGA_WR08(par->riva.PCIO, 0x3d4, index);
410 return (VGA_RD08(par->riva.PCIO, 0x3d5));
411}
412
413static inline void GRAout(struct riva_par *par, unsigned char index,
414 unsigned char val)
415{
416 VGA_WR08(par->riva.PVIO, 0x3ce, index);
417 VGA_WR08(par->riva.PVIO, 0x3cf, val);
418}
419
420static inline unsigned char GRAin(struct riva_par *par,
421 unsigned char index)
422{
423 VGA_WR08(par->riva.PVIO, 0x3ce, index);
424 return (VGA_RD08(par->riva.PVIO, 0x3cf));
425}
426
427static inline void SEQout(struct riva_par *par, unsigned char index,
428 unsigned char val)
429{
430 VGA_WR08(par->riva.PVIO, 0x3c4, index);
431 VGA_WR08(par->riva.PVIO, 0x3c5, val);
432}
433
434static inline unsigned char SEQin(struct riva_par *par,
435 unsigned char index)
436{
437 VGA_WR08(par->riva.PVIO, 0x3c4, index);
438 return (VGA_RD08(par->riva.PVIO, 0x3c5));
439}
440
441static inline void ATTRout(struct riva_par *par, unsigned char index,
442 unsigned char val)
443{
444 VGA_WR08(par->riva.PCIO, 0x3c0, index);
445 VGA_WR08(par->riva.PCIO, 0x3c0, val);
446}
447
448static inline unsigned char ATTRin(struct riva_par *par,
449 unsigned char index)
450{
451 VGA_WR08(par->riva.PCIO, 0x3c0, index);
452 return (VGA_RD08(par->riva.PCIO, 0x3c1));
453}
454
455static inline void MISCout(struct riva_par *par, unsigned char val)
456{
457 VGA_WR08(par->riva.PVIO, 0x3c2, val);
458}
459
460static inline unsigned char MISCin(struct riva_par *par)
461{
462 return (VGA_RD08(par->riva.PVIO, 0x3cc));
463}
464
465static inline void reverse_order(u32 *l)
466{
467 u8 *a = (u8 *)l;
468 a[0] = bitrev8(a[0]);
469 a[1] = bitrev8(a[1]);
470 a[2] = bitrev8(a[2]);
471 a[3] = bitrev8(a[3]);
472}
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498static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
499 u16 bg, u16 fg, u32 w, u32 h)
500{
501 int i, j, k = 0;
502 u32 b, tmp;
503 u32 *data = (u32 *)data8;
504 bg = le16_to_cpu(bg);
505 fg = le16_to_cpu(fg);
506
507 w = (w + 1) & ~1;
508
509 for (i = 0; i < h; i++) {
510 b = *data++;
511 reverse_order(&b);
512
513 for (j = 0; j < w/2; j++) {
514 tmp = 0;
515#if defined (__BIG_ENDIAN)
516 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
517 b <<= 1;
518 tmp |= (b & (1 << 31)) ? fg : bg;
519 b <<= 1;
520#else
521 tmp = (b & 1) ? fg : bg;
522 b >>= 1;
523 tmp |= (b & 1) ? fg << 16 : bg << 16;
524 b >>= 1;
525#endif
526 writel(tmp, &par->riva.CURSOR[k++]);
527 }
528 k += (MAX_CURS - w)/2;
529 }
530}
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551
552static void riva_wclut(RIVA_HW_INST *chip,
553 unsigned char regnum, unsigned char red,
554 unsigned char green, unsigned char blue)
555{
556 VGA_WR08(chip->PDIO, 0x3c8, regnum);
557 VGA_WR08(chip->PDIO, 0x3c9, red);
558 VGA_WR08(chip->PDIO, 0x3c9, green);
559 VGA_WR08(chip->PDIO, 0x3c9, blue);
560}
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575
576static void riva_rclut(RIVA_HW_INST *chip,
577 unsigned char regnum, unsigned char *red,
578 unsigned char *green, unsigned char *blue)
579{
580
581 VGA_WR08(chip->PDIO, 0x3c7, regnum);
582 *red = VGA_RD08(chip->PDIO, 0x3c9);
583 *green = VGA_RD08(chip->PDIO, 0x3c9);
584 *blue = VGA_RD08(chip->PDIO, 0x3c9);
585}
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597
598
599static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
600{
601 int i;
602
603 NVTRACE_ENTER();
604 par->riva.LockUnlock(&par->riva, 0);
605
606 par->riva.UnloadStateExt(&par->riva, ®s->ext);
607
608 regs->misc_output = MISCin(par);
609
610 for (i = 0; i < NUM_CRT_REGS; i++)
611 regs->crtc[i] = CRTCin(par, i);
612
613 for (i = 0; i < NUM_ATC_REGS; i++)
614 regs->attr[i] = ATTRin(par, i);
615
616 for (i = 0; i < NUM_GRC_REGS; i++)
617 regs->gra[i] = GRAin(par, i);
618
619 for (i = 0; i < NUM_SEQ_REGS; i++)
620 regs->seq[i] = SEQin(par, i);
621 NVTRACE_LEAVE();
622}
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637
638static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
639{
640 RIVA_HW_STATE *state = ®s->ext;
641 int i;
642
643 NVTRACE_ENTER();
644 CRTCout(par, 0x11, 0x00);
645
646 par->riva.LockUnlock(&par->riva, 0);
647
648 par->riva.LoadStateExt(&par->riva, state);
649
650 MISCout(par, regs->misc_output);
651
652 for (i = 0; i < NUM_CRT_REGS; i++) {
653 switch (i) {
654 case 0x19:
655 case 0x20 ... 0x40:
656 break;
657 default:
658 CRTCout(par, i, regs->crtc[i]);
659 }
660 }
661
662 for (i = 0; i < NUM_ATC_REGS; i++)
663 ATTRout(par, i, regs->attr[i]);
664
665 for (i = 0; i < NUM_GRC_REGS; i++)
666 GRAout(par, i, regs->gra[i]);
667
668 for (i = 0; i < NUM_SEQ_REGS; i++)
669 SEQout(par, i, regs->seq[i]);
670 NVTRACE_LEAVE();
671}
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682
683static int riva_load_video_mode(struct fb_info *info)
684{
685 int bpp, width, hDisplaySize, hDisplay, hStart,
686 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
687 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
688 int rc;
689 struct riva_par *par = info->par;
690 struct riva_regs newmode;
691
692 NVTRACE_ENTER();
693
694 rivafb_blank(FB_BLANK_NORMAL, info);
695
696 bpp = info->var.bits_per_pixel;
697 if (bpp == 16 && info->var.green.length == 5)
698 bpp = 15;
699 width = info->var.xres_virtual;
700 hDisplaySize = info->var.xres;
701 hDisplay = (hDisplaySize / 8) - 1;
702 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
703 hEnd = (hDisplaySize + info->var.right_margin +
704 info->var.hsync_len) / 8 - 1;
705 hTotal = (hDisplaySize + info->var.right_margin +
706 info->var.hsync_len + info->var.left_margin) / 8 - 5;
707 hBlankStart = hDisplay;
708 hBlankEnd = hTotal + 4;
709
710 height = info->var.yres_virtual;
711 vDisplay = info->var.yres - 1;
712 vStart = info->var.yres + info->var.lower_margin - 1;
713 vEnd = info->var.yres + info->var.lower_margin +
714 info->var.vsync_len - 1;
715 vTotal = info->var.yres + info->var.lower_margin +
716 info->var.vsync_len + info->var.upper_margin + 2;
717 vBlankStart = vDisplay;
718 vBlankEnd = vTotal + 1;
719 dotClock = 1000000000 / info->var.pixclock;
720
721 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
722
723 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
724 vTotal |= 1;
725
726 if (par->FlatPanel) {
727 vStart = vTotal - 3;
728 vEnd = vTotal - 2;
729 vBlankStart = vStart;
730 hStart = hTotal - 3;
731 hEnd = hTotal - 2;
732 hBlankEnd = hTotal + 4;
733 }
734
735 newmode.crtc[0x0] = Set8Bits (hTotal);
736 newmode.crtc[0x1] = Set8Bits (hDisplay);
737 newmode.crtc[0x2] = Set8Bits (hBlankStart);
738 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
739 newmode.crtc[0x4] = Set8Bits (hStart);
740 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
741 | SetBitField (hEnd, 4: 0, 4:0);
742 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
743 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
744 | SetBitField (vDisplay, 8: 8, 1:1)
745 | SetBitField (vStart, 8: 8, 2:2)
746 | SetBitField (vBlankStart, 8: 8, 3:3)
747 | SetBit (4)
748 | SetBitField (vTotal, 9: 9, 5:5)
749 | SetBitField (vDisplay, 9: 9, 6:6)
750 | SetBitField (vStart, 9: 9, 7:7);
751 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
752 | SetBit (6);
753 newmode.crtc[0x10] = Set8Bits (vStart);
754 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
755 | SetBit (5);
756 newmode.crtc[0x12] = Set8Bits (vDisplay);
757 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
758 newmode.crtc[0x15] = Set8Bits (vBlankStart);
759 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
760
761 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
762 | SetBitField(vBlankStart,10:10,3:3)
763 | SetBitField(vStart,10:10,2:2)
764 | SetBitField(vDisplay,10:10,1:1)
765 | SetBitField(vTotal,10:10,0:0);
766 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
767 | SetBitField(hDisplay,8:8,1:1)
768 | SetBitField(hBlankStart,8:8,2:2)
769 | SetBitField(hStart,8:8,3:3);
770 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
771 | SetBitField(vDisplay,11:11,2:2)
772 | SetBitField(vStart,11:11,4:4)
773 | SetBitField(vBlankStart,11:11,6:6);
774
775 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
776 int tmp = (hTotal >> 1) & ~1;
777 newmode.ext.interlace = Set8Bits(tmp);
778 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
779 } else
780 newmode.ext.interlace = 0xff;
781
782 if (par->riva.Architecture >= NV_ARCH_10)
783 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
784
785 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
786 newmode.misc_output &= ~0x40;
787 else
788 newmode.misc_output |= 0x40;
789 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
790 newmode.misc_output &= ~0x80;
791 else
792 newmode.misc_output |= 0x80;
793
794 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
795 hDisplaySize, height, dotClock);
796 if (rc)
797 goto out;
798
799 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
800 0xfff000ff;
801 if (par->FlatPanel == 1) {
802 newmode.ext.pixel |= (1 << 7);
803 newmode.ext.scale |= (1 << 8);
804 }
805 if (par->SecondCRTC) {
806 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
807 ~0x00001000;
808 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
809 0x00001000;
810 newmode.ext.crtcOwner = 3;
811 newmode.ext.pllsel |= 0x20000800;
812 newmode.ext.vpll2 = newmode.ext.vpll;
813 } else if (par->riva.twoHeads) {
814 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
815 0x00001000;
816 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
817 ~0x00001000;
818 newmode.ext.crtcOwner = 0;
819 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
820 }
821 if (par->FlatPanel == 1) {
822 newmode.ext.pixel |= (1 << 7);
823 newmode.ext.scale |= (1 << 8);
824 }
825 newmode.ext.cursorConfig = 0x02000100;
826 par->current_state = newmode;
827 riva_load_state(par, &par->current_state);
828 par->riva.LockUnlock(&par->riva, 0);
829
830out:
831 rivafb_blank(FB_BLANK_UNBLANK, info);
832 NVTRACE_LEAVE();
833
834 return rc;
835}
836
837static void riva_update_var(struct fb_var_screeninfo *var,
838 const struct fb_videomode *modedb)
839{
840 NVTRACE_ENTER();
841 var->xres = var->xres_virtual = modedb->xres;
842 var->yres = modedb->yres;
843 if (var->yres_virtual < var->yres)
844 var->yres_virtual = var->yres;
845 var->xoffset = var->yoffset = 0;
846 var->pixclock = modedb->pixclock;
847 var->left_margin = modedb->left_margin;
848 var->right_margin = modedb->right_margin;
849 var->upper_margin = modedb->upper_margin;
850 var->lower_margin = modedb->lower_margin;
851 var->hsync_len = modedb->hsync_len;
852 var->vsync_len = modedb->vsync_len;
853 var->sync = modedb->sync;
854 var->vmode = modedb->vmode;
855 NVTRACE_LEAVE();
856}
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875static int rivafb_do_maximize(struct fb_info *info,
876 struct fb_var_screeninfo *var,
877 int nom, int den)
878{
879 static struct {
880 int xres, yres;
881 } modes[] = {
882 {1600, 1280},
883 {1280, 1024},
884 {1024, 768},
885 {800, 600},
886 {640, 480},
887 {-1, -1}
888 };
889 int i;
890
891 NVTRACE_ENTER();
892
893 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
894 printk(KERN_WARNING PFX
895 "using maximum available virtual resolution\n");
896 for (i = 0; modes[i].xres != -1; i++) {
897 if (modes[i].xres * nom / den * modes[i].yres <
898 info->fix.smem_len)
899 break;
900 }
901 if (modes[i].xres == -1) {
902 printk(KERN_ERR PFX
903 "could not find a virtual resolution that fits into video memory!!\n");
904 NVTRACE("EXIT - EINVAL error\n");
905 return -EINVAL;
906 }
907 var->xres_virtual = modes[i].xres;
908 var->yres_virtual = modes[i].yres;
909
910 printk(KERN_INFO PFX
911 "virtual resolution set to maximum of %dx%d\n",
912 var->xres_virtual, var->yres_virtual);
913 } else if (var->xres_virtual == -1) {
914 var->xres_virtual = (info->fix.smem_len * den /
915 (nom * var->yres_virtual)) & ~15;
916 printk(KERN_WARNING PFX
917 "setting virtual X resolution to %d\n", var->xres_virtual);
918 } else if (var->yres_virtual == -1) {
919 var->xres_virtual = (var->xres_virtual + 15) & ~15;
920 var->yres_virtual = info->fix.smem_len * den /
921 (nom * var->xres_virtual);
922 printk(KERN_WARNING PFX
923 "setting virtual Y resolution to %d\n", var->yres_virtual);
924 } else {
925 var->xres_virtual = (var->xres_virtual + 15) & ~15;
926 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
927 printk(KERN_ERR PFX
928 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
929 var->xres, var->yres, var->bits_per_pixel);
930 NVTRACE("EXIT - EINVAL error\n");
931 return -EINVAL;
932 }
933 }
934
935 if (var->xres_virtual * nom / den >= 8192) {
936 printk(KERN_WARNING PFX
937 "virtual X resolution (%d) is too high, lowering to %d\n",
938 var->xres_virtual, 8192 * den / nom - 16);
939 var->xres_virtual = 8192 * den / nom - 16;
940 }
941
942 if (var->xres_virtual < var->xres) {
943 printk(KERN_ERR PFX
944 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
945 return -EINVAL;
946 }
947
948 if (var->yres_virtual < var->yres) {
949 printk(KERN_ERR PFX
950 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
951 return -EINVAL;
952 }
953 if (var->yres_virtual > 0x7fff/nom)
954 var->yres_virtual = 0x7fff/nom;
955 if (var->xres_virtual > 0x7fff/nom)
956 var->xres_virtual = 0x7fff/nom;
957 NVTRACE_LEAVE();
958 return 0;
959}
960
961static void
962riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
963{
964 RIVA_FIFO_FREE(par->riva, Patt, 4);
965 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
966 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
967 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
968 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
969}
970
971
972static inline void wait_for_idle(struct riva_par *par)
973{
974 while (par->riva.Busy(&par->riva));
975}
976
977
978
979
980static void
981riva_set_rop_solid(struct riva_par *par, int rop)
982{
983 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
984 RIVA_FIFO_FREE(par->riva, Rop, 1);
985 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
986
987}
988
989static void riva_setup_accel(struct fb_info *info)
990{
991 struct riva_par *par = info->par;
992
993 RIVA_FIFO_FREE(par->riva, Clip, 2);
994 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
995 NV_WR32(&par->riva.Clip->WidthHeight, 0,
996 (info->var.xres_virtual & 0xffff) |
997 (info->var.yres_virtual << 16));
998 riva_set_rop_solid(par, 0xcc);
999 wait_for_idle(par);
1000}
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1016{
1017 int rc = 256;
1018
1019 switch (var->green.length) {
1020 case 8:
1021 rc = 256;
1022 break;
1023 case 5:
1024 rc = 32;
1025 break;
1026 case 6:
1027 rc = 64;
1028 break;
1029 default:
1030
1031 break;
1032 }
1033 return rc;
1034}
1035
1036
1037
1038
1039
1040
1041
1042static int rivafb_open(struct fb_info *info, int user)
1043{
1044 struct riva_par *par = info->par;
1045
1046 NVTRACE_ENTER();
1047 mutex_lock(&par->open_lock);
1048 if (!par->ref_count) {
1049#ifdef CONFIG_X86
1050 memset(&par->state, 0, sizeof(struct vgastate));
1051 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1052
1053 if (par->riva.Architecture == NV_ARCH_03)
1054 par->state.flags |= VGA_SAVE_CMAP;
1055 save_vga(&par->state);
1056#endif
1057
1058 CRTCout(par, 0x11, 0xFF);
1059 par->riva.LockUnlock(&par->riva, 0);
1060
1061 riva_save_state(par, &par->initial_state);
1062 }
1063 par->ref_count++;
1064 mutex_unlock(&par->open_lock);
1065 NVTRACE_LEAVE();
1066 return 0;
1067}
1068
1069static int rivafb_release(struct fb_info *info, int user)
1070{
1071 struct riva_par *par = info->par;
1072
1073 NVTRACE_ENTER();
1074 mutex_lock(&par->open_lock);
1075 if (!par->ref_count) {
1076 mutex_unlock(&par->open_lock);
1077 return -EINVAL;
1078 }
1079 if (par->ref_count == 1) {
1080 par->riva.LockUnlock(&par->riva, 0);
1081 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1082 riva_load_state(par, &par->initial_state);
1083#ifdef CONFIG_X86
1084 restore_vga(&par->state);
1085#endif
1086 par->riva.LockUnlock(&par->riva, 1);
1087 }
1088 par->ref_count--;
1089 mutex_unlock(&par->open_lock);
1090 NVTRACE_LEAVE();
1091 return 0;
1092}
1093
1094static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1095{
1096 const struct fb_videomode *mode;
1097 struct riva_par *par = info->par;
1098 int nom, den;
1099 int mode_valid = 0;
1100
1101 NVTRACE_ENTER();
1102 switch (var->bits_per_pixel) {
1103 case 1 ... 8:
1104 var->red.offset = var->green.offset = var->blue.offset = 0;
1105 var->red.length = var->green.length = var->blue.length = 8;
1106 var->bits_per_pixel = 8;
1107 nom = den = 1;
1108 break;
1109 case 9 ... 15:
1110 var->green.length = 5;
1111
1112 case 16:
1113 var->bits_per_pixel = 16;
1114
1115 if (par->riva.Architecture == NV_ARCH_03)
1116 var->green.length = 5;
1117 if (var->green.length == 5) {
1118
1119 var->red.offset = 10;
1120 var->green.offset = 5;
1121 var->blue.offset = 0;
1122 var->red.length = 5;
1123 var->green.length = 5;
1124 var->blue.length = 5;
1125 } else {
1126
1127 var->red.offset = 11;
1128 var->green.offset = 5;
1129 var->blue.offset = 0;
1130 var->red.length = 5;
1131 var->green.length = 6;
1132 var->blue.length = 5;
1133 }
1134 nom = 2;
1135 den = 1;
1136 break;
1137 case 17 ... 32:
1138 var->red.length = var->green.length = var->blue.length = 8;
1139 var->bits_per_pixel = 32;
1140 var->red.offset = 16;
1141 var->green.offset = 8;
1142 var->blue.offset = 0;
1143 nom = 4;
1144 den = 1;
1145 break;
1146 default:
1147 printk(KERN_ERR PFX
1148 "mode %dx%dx%d rejected...color depth not supported.\n",
1149 var->xres, var->yres, var->bits_per_pixel);
1150 NVTRACE("EXIT, returning -EINVAL\n");
1151 return -EINVAL;
1152 }
1153
1154 if (!strictmode) {
1155 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1156 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1157 mode_valid = 1;
1158 }
1159
1160
1161 if (!mode_valid && info->monspecs.gtf) {
1162 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1163 mode_valid = 1;
1164 }
1165
1166 if (!mode_valid) {
1167 mode = fb_find_best_mode(var, &info->modelist);
1168 if (mode) {
1169 riva_update_var(var, mode);
1170 mode_valid = 1;
1171 }
1172 }
1173
1174 if (!mode_valid && info->monspecs.modedb_len)
1175 return -EINVAL;
1176
1177 if (var->xres_virtual < var->xres)
1178 var->xres_virtual = var->xres;
1179 if (var->yres_virtual <= var->yres)
1180 var->yres_virtual = -1;
1181 if (rivafb_do_maximize(info, var, nom, den) < 0)
1182 return -EINVAL;
1183
1184 if (var->xoffset < 0)
1185 var->xoffset = 0;
1186 if (var->yoffset < 0)
1187 var->yoffset = 0;
1188
1189
1190 if (var->xoffset > var->xres_virtual - var->xres)
1191 var->xoffset = var->xres_virtual - var->xres - 1;
1192
1193 if (var->yoffset > var->yres_virtual - var->yres)
1194 var->yoffset = var->yres_virtual - var->yres - 1;
1195
1196 var->red.msb_right =
1197 var->green.msb_right =
1198 var->blue.msb_right =
1199 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1200 NVTRACE_LEAVE();
1201 return 0;
1202}
1203
1204static int rivafb_set_par(struct fb_info *info)
1205{
1206 struct riva_par *par = info->par;
1207 int rc = 0;
1208
1209 NVTRACE_ENTER();
1210
1211 CRTCout(par, 0x11, 0xFF);
1212 par->riva.LockUnlock(&par->riva, 0);
1213 rc = riva_load_video_mode(info);
1214 if (rc)
1215 goto out;
1216 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1217 riva_setup_accel(info);
1218
1219 par->cursor_reset = 1;
1220 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1221 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1222 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1223
1224 if (info->flags & FBINFO_HWACCEL_DISABLED)
1225 info->pixmap.scan_align = 1;
1226 else
1227 info->pixmap.scan_align = 4;
1228
1229out:
1230 NVTRACE_LEAVE();
1231 return rc;
1232}
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247static int rivafb_pan_display(struct fb_var_screeninfo *var,
1248 struct fb_info *info)
1249{
1250 struct riva_par *par = info->par;
1251 unsigned int base;
1252
1253 NVTRACE_ENTER();
1254 base = var->yoffset * info->fix.line_length + var->xoffset;
1255 par->riva.SetStartAddress(&par->riva, base);
1256 NVTRACE_LEAVE();
1257 return 0;
1258}
1259
1260static int rivafb_blank(int blank, struct fb_info *info)
1261{
1262 struct riva_par *par= info->par;
1263 unsigned char tmp, vesa;
1264
1265 tmp = SEQin(par, 0x01) & ~0x20;
1266 vesa = CRTCin(par, 0x1a) & ~0xc0;
1267
1268 NVTRACE_ENTER();
1269
1270 if (blank)
1271 tmp |= 0x20;
1272
1273 switch (blank) {
1274 case FB_BLANK_UNBLANK:
1275 case FB_BLANK_NORMAL:
1276 break;
1277 case FB_BLANK_VSYNC_SUSPEND:
1278 vesa |= 0x80;
1279 break;
1280 case FB_BLANK_HSYNC_SUSPEND:
1281 vesa |= 0x40;
1282 break;
1283 case FB_BLANK_POWERDOWN:
1284 vesa |= 0xc0;
1285 break;
1286 }
1287
1288 SEQout(par, 0x01, tmp);
1289 CRTCout(par, 0x1a, vesa);
1290
1291 NVTRACE_LEAVE();
1292
1293 return 0;
1294}
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1316 unsigned blue, unsigned transp,
1317 struct fb_info *info)
1318{
1319 struct riva_par *par = info->par;
1320 RIVA_HW_INST *chip = &par->riva;
1321 int i;
1322
1323 if (regno >= riva_get_cmap_len(&info->var))
1324 return -EINVAL;
1325
1326 if (info->var.grayscale) {
1327
1328 red = green = blue =
1329 (red * 77 + green * 151 + blue * 28) >> 8;
1330 }
1331
1332 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1333 ((u32 *) info->pseudo_palette)[regno] =
1334 (regno << info->var.red.offset) |
1335 (regno << info->var.green.offset) |
1336 (regno << info->var.blue.offset);
1337
1338
1339
1340
1341 if (par->riva.Architecture == NV_ARCH_03) {
1342 switch (info->var.bits_per_pixel) {
1343 case 16:
1344 par->palette[regno] = ((red & 0xf800) >> 1) |
1345 ((green & 0xf800) >> 6) |
1346 ((blue & 0xf800) >> 11);
1347 break;
1348 case 32:
1349 par->palette[regno] = ((red & 0xff00) << 8) |
1350 ((green & 0xff00)) |
1351 ((blue & 0xff00) >> 8);
1352 break;
1353 }
1354 }
1355 }
1356
1357 switch (info->var.bits_per_pixel) {
1358 case 8:
1359
1360 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1361 break;
1362 case 16:
1363 if (info->var.green.length == 5) {
1364 for (i = 0; i < 8; i++) {
1365 riva_wclut(chip, regno*8+i, red >> 8,
1366 green >> 8, blue >> 8);
1367 }
1368 } else {
1369 u8 r, g, b;
1370
1371 if (regno < 32) {
1372 for (i = 0; i < 8; i++) {
1373 riva_wclut(chip, regno*8+i,
1374 red >> 8, green >> 8,
1375 blue >> 8);
1376 }
1377 }
1378 riva_rclut(chip, regno*4, &r, &g, &b);
1379 for (i = 0; i < 4; i++)
1380 riva_wclut(chip, regno*4+i, r,
1381 green >> 8, b);
1382 }
1383 break;
1384 case 32:
1385 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1386 break;
1387 default:
1388
1389 break;
1390 }
1391 return 0;
1392}
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1407{
1408 struct riva_par *par = info->par;
1409 u_int color, rop = 0;
1410
1411 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1412 cfb_fillrect(info, rect);
1413 return;
1414 }
1415
1416 if (info->var.bits_per_pixel == 8)
1417 color = rect->color;
1418 else {
1419 if (par->riva.Architecture != NV_ARCH_03)
1420 color = ((u32 *)info->pseudo_palette)[rect->color];
1421 else
1422 color = par->palette[rect->color];
1423 }
1424
1425 switch (rect->rop) {
1426 case ROP_XOR:
1427 rop = 0x66;
1428 break;
1429 case ROP_COPY:
1430 default:
1431 rop = 0xCC;
1432 break;
1433 }
1434
1435 riva_set_rop_solid(par, rop);
1436
1437 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1438 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1439
1440 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1441 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1442 (rect->dx << 16) | rect->dy);
1443 mb();
1444 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1445 (rect->width << 16) | rect->height);
1446 mb();
1447 riva_set_rop_solid(par, 0xcc);
1448
1449}
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1463{
1464 struct riva_par *par = info->par;
1465
1466 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1467 cfb_copyarea(info, region);
1468 return;
1469 }
1470
1471 RIVA_FIFO_FREE(par->riva, Blt, 3);
1472 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1473 (region->sy << 16) | region->sx);
1474 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1475 (region->dy << 16) | region->dx);
1476 mb();
1477 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1478 (region->height << 16) | region->width);
1479 mb();
1480}
1481
1482static inline void convert_bgcolor_16(u32 *col)
1483{
1484 *col = ((*col & 0x0000F800) << 8)
1485 | ((*col & 0x00007E0) << 5)
1486 | ((*col & 0x0000001F) << 3)
1487 | 0xFF000000;
1488 mb();
1489}
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507static void rivafb_imageblit(struct fb_info *info,
1508 const struct fb_image *image)
1509{
1510 struct riva_par *par = info->par;
1511 u32 fgx = 0, bgx = 0, width, tmp;
1512 u8 *cdat = (u8 *) image->data;
1513 volatile u32 __iomem *d;
1514 int i, size;
1515
1516 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1517 cfb_imageblit(info, image);
1518 return;
1519 }
1520
1521 switch (info->var.bits_per_pixel) {
1522 case 8:
1523 fgx = image->fg_color;
1524 bgx = image->bg_color;
1525 break;
1526 case 16:
1527 case 32:
1528 if (par->riva.Architecture != NV_ARCH_03) {
1529 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1530 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1531 } else {
1532 fgx = par->palette[image->fg_color];
1533 bgx = par->palette[image->bg_color];
1534 }
1535 if (info->var.green.length == 6)
1536 convert_bgcolor_16(&bgx);
1537 break;
1538 }
1539
1540 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1541 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1542 (image->dy << 16) | (image->dx & 0xFFFF));
1543 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1544 (((image->dy + image->height) << 16) |
1545 ((image->dx + image->width) & 0xffff)));
1546 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1547 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1548 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1549 (image->height << 16) | ((image->width + 31) & ~31));
1550 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1551 (image->height << 16) | ((image->width + 31) & ~31));
1552 NV_WR32(&par->riva.Bitmap->PointE, 0,
1553 (image->dy << 16) | (image->dx & 0xFFFF));
1554
1555 d = &par->riva.Bitmap->MonochromeData01E;
1556
1557 width = (image->width + 31)/32;
1558 size = width * image->height;
1559 while (size >= 16) {
1560 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1561 for (i = 0; i < 16; i++) {
1562 tmp = *((u32 *)cdat);
1563 cdat = (u8 *)((u32 *)cdat + 1);
1564 reverse_order(&tmp);
1565 NV_WR32(d, i*4, tmp);
1566 }
1567 size -= 16;
1568 }
1569 if (size) {
1570 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1571 for (i = 0; i < size; i++) {
1572 tmp = *((u32 *) cdat);
1573 cdat = (u8 *)((u32 *)cdat + 1);
1574 reverse_order(&tmp);
1575 NV_WR32(d, i*4, tmp);
1576 }
1577 }
1578}
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1594{
1595 struct riva_par *par = info->par;
1596 u8 data[MAX_CURS * MAX_CURS/8];
1597 int i, set = cursor->set;
1598 u16 fg, bg;
1599
1600 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1601 return -ENXIO;
1602
1603 par->riva.ShowHideCursor(&par->riva, 0);
1604
1605 if (par->cursor_reset) {
1606 set = FB_CUR_SETALL;
1607 par->cursor_reset = 0;
1608 }
1609
1610 if (set & FB_CUR_SETSIZE)
1611 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1612
1613 if (set & FB_CUR_SETPOS) {
1614 u32 xx, yy, temp;
1615
1616 yy = cursor->image.dy - info->var.yoffset;
1617 xx = cursor->image.dx - info->var.xoffset;
1618 temp = xx & 0xFFFF;
1619 temp |= yy << 16;
1620
1621 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1622 }
1623
1624
1625 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1626 u32 bg_idx = cursor->image.bg_color;
1627 u32 fg_idx = cursor->image.fg_color;
1628 u32 s_pitch = (cursor->image.width+7) >> 3;
1629 u32 d_pitch = MAX_CURS/8;
1630 u8 *dat = (u8 *) cursor->image.data;
1631 u8 *msk = (u8 *) cursor->mask;
1632 u8 *src;
1633
1634 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1635
1636 if (src) {
1637 switch (cursor->rop) {
1638 case ROP_XOR:
1639 for (i = 0; i < s_pitch * cursor->image.height; i++)
1640 src[i] = dat[i] ^ msk[i];
1641 break;
1642 case ROP_COPY:
1643 default:
1644 for (i = 0; i < s_pitch * cursor->image.height; i++)
1645 src[i] = dat[i] & msk[i];
1646 break;
1647 }
1648
1649 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1650 cursor->image.height);
1651
1652 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1653 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1654 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1655 1 << 15;
1656
1657 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1658 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1659 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1660 1 << 15;
1661
1662 par->riva.LockUnlock(&par->riva, 0);
1663
1664 rivafb_load_cursor_image(par, data, bg, fg,
1665 cursor->image.width,
1666 cursor->image.height);
1667 kfree(src);
1668 }
1669 }
1670
1671 if (cursor->enable)
1672 par->riva.ShowHideCursor(&par->riva, 1);
1673
1674 return 0;
1675}
1676
1677static int rivafb_sync(struct fb_info *info)
1678{
1679 struct riva_par *par = info->par;
1680
1681 wait_for_idle(par);
1682 return 0;
1683}
1684
1685
1686
1687
1688
1689
1690
1691
1692static struct fb_ops riva_fb_ops = {
1693 .owner = THIS_MODULE,
1694 .fb_open = rivafb_open,
1695 .fb_release = rivafb_release,
1696 .fb_check_var = rivafb_check_var,
1697 .fb_set_par = rivafb_set_par,
1698 .fb_setcolreg = rivafb_setcolreg,
1699 .fb_pan_display = rivafb_pan_display,
1700 .fb_blank = rivafb_blank,
1701 .fb_fillrect = rivafb_fillrect,
1702 .fb_copyarea = rivafb_copyarea,
1703 .fb_imageblit = rivafb_imageblit,
1704 .fb_cursor = rivafb_cursor,
1705 .fb_sync = rivafb_sync,
1706};
1707
1708static int __devinit riva_set_fbinfo(struct fb_info *info)
1709{
1710 unsigned int cmap_len;
1711 struct riva_par *par = info->par;
1712
1713 NVTRACE_ENTER();
1714 info->flags = FBINFO_DEFAULT
1715 | FBINFO_HWACCEL_XPAN
1716 | FBINFO_HWACCEL_YPAN
1717 | FBINFO_HWACCEL_COPYAREA
1718 | FBINFO_HWACCEL_FILLRECT
1719 | FBINFO_HWACCEL_IMAGEBLIT;
1720
1721
1722 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1723 printk(KERN_DEBUG PFX "disabling acceleration\n");
1724 info->flags |= FBINFO_HWACCEL_DISABLED;
1725 }
1726
1727 info->var = rivafb_default_var;
1728 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1729 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1730
1731 info->pseudo_palette = par->pseudo_palette;
1732
1733 cmap_len = riva_get_cmap_len(&info->var);
1734 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1735
1736 info->pixmap.size = 8 * 1024;
1737 info->pixmap.buf_align = 4;
1738 info->pixmap.access_align = 32;
1739 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1740 info->var.yres_virtual = -1;
1741 NVTRACE_LEAVE();
1742 return (rivafb_check_var(&info->var, info));
1743}
1744
1745#ifdef CONFIG_PPC_OF
1746static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1747{
1748 struct riva_par *par = info->par;
1749 struct device_node *dp;
1750 const unsigned char *pedid = NULL;
1751 const unsigned char *disptype = NULL;
1752 static char *propnames[] = {
1753 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1754 int i;
1755
1756 NVTRACE_ENTER();
1757 dp = pci_device_to_OF_node(pd);
1758 for (; dp != NULL; dp = dp->child) {
1759 disptype = of_get_property(dp, "display-type", NULL);
1760 if (disptype == NULL)
1761 continue;
1762 if (strncmp(disptype, "LCD", 3) != 0)
1763 continue;
1764 for (i = 0; propnames[i] != NULL; ++i) {
1765 pedid = of_get_property(dp, propnames[i], NULL);
1766 if (pedid != NULL) {
1767 par->EDID = (unsigned char *)pedid;
1768 NVTRACE("LCD found.\n");
1769 return 1;
1770 }
1771 }
1772 }
1773 NVTRACE_LEAVE();
1774 return 0;
1775}
1776#endif
1777
1778#if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1779static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1780{
1781 struct riva_par *par = info->par;
1782 struct fb_var_screeninfo var;
1783 int i;
1784
1785 NVTRACE_ENTER();
1786 riva_create_i2c_busses(par);
1787 for (i = 0; i < 3; i++) {
1788 if (!par->chan[i].par)
1789 continue;
1790 riva_probe_i2c_connector(par, i, &par->EDID);
1791 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1792 printk(PFX "Found EDID Block from BUS %i\n", i);
1793 break;
1794 }
1795 }
1796
1797 NVTRACE_LEAVE();
1798 return (par->EDID) ? 1 : 0;
1799}
1800#endif
1801
1802static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1803 struct fb_info *info)
1804{
1805 struct fb_monspecs *specs = &info->monspecs;
1806 struct fb_videomode modedb;
1807
1808 NVTRACE_ENTER();
1809
1810 if (mode_option) {
1811 fb_find_mode(var, info, mode_option,
1812 specs->modedb, specs->modedb_len,
1813 NULL, 8);
1814 } else if (specs->modedb != NULL) {
1815
1816 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1817 int i;
1818
1819 for (i = 0; i < specs->modedb_len; i++) {
1820 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1821 modedb = specs->modedb[i];
1822 break;
1823 }
1824 }
1825 } else {
1826
1827 modedb = specs->modedb[0];
1828 }
1829 var->bits_per_pixel = 8;
1830 riva_update_var(var, &modedb);
1831 }
1832 NVTRACE_LEAVE();
1833}
1834
1835
1836static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1837{
1838 NVTRACE_ENTER();
1839#ifdef CONFIG_PPC_OF
1840 if (!riva_get_EDID_OF(info, pdev))
1841 printk(PFX "could not retrieve EDID from OF\n");
1842#elif defined(CONFIG_FB_RIVA_I2C)
1843 if (!riva_get_EDID_i2c(info))
1844 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1845#endif
1846 NVTRACE_LEAVE();
1847}
1848
1849
1850static void __devinit riva_get_edidinfo(struct fb_info *info)
1851{
1852 struct fb_var_screeninfo *var = &rivafb_default_var;
1853 struct riva_par *par = info->par;
1854
1855 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1856 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1857 &info->modelist);
1858 riva_update_default_var(var, info);
1859
1860
1861 if (info->monspecs.input & FB_DISP_DDI)
1862 par->FlatPanel = 1;
1863}
1864
1865
1866
1867
1868
1869
1870
1871static u32 __devinit riva_get_arch(struct pci_dev *pd)
1872{
1873 u32 arch = 0;
1874
1875 switch (pd->device & 0x0ff0) {
1876 case 0x0100:
1877 case 0x0110:
1878 case 0x0150:
1879 case 0x0170:
1880 case 0x0180:
1881 case 0x01A0:
1882 case 0x01F0:
1883 arch = NV_ARCH_10;
1884 break;
1885 case 0x0200:
1886 case 0x0250:
1887 case 0x0280:
1888 arch = NV_ARCH_20;
1889 break;
1890 case 0x0300:
1891 case 0x0310:
1892 case 0x0320:
1893 case 0x0330:
1894 case 0x0340:
1895 arch = NV_ARCH_30;
1896 break;
1897 case 0x0020:
1898 arch = NV_ARCH_04;
1899 break;
1900 case 0x0010:
1901 arch = NV_ARCH_03;
1902 break;
1903 default:
1904 break;
1905 }
1906 return arch;
1907}
1908
1909static int __devinit rivafb_probe(struct pci_dev *pd,
1910 const struct pci_device_id *ent)
1911{
1912 struct riva_par *default_par;
1913 struct fb_info *info;
1914 int ret;
1915
1916 NVTRACE_ENTER();
1917 assert(pd != NULL);
1918
1919 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1920 if (!info) {
1921 printk (KERN_ERR PFX "could not allocate memory\n");
1922 ret = -ENOMEM;
1923 goto err_ret;
1924 }
1925 default_par = info->par;
1926 default_par->pdev = pd;
1927
1928 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1929 if (info->pixmap.addr == NULL) {
1930 ret = -ENOMEM;
1931 goto err_framebuffer_release;
1932 }
1933
1934 ret = pci_enable_device(pd);
1935 if (ret < 0) {
1936 printk(KERN_ERR PFX "cannot enable PCI device\n");
1937 goto err_free_pixmap;
1938 }
1939
1940 ret = pci_request_regions(pd, "rivafb");
1941 if (ret < 0) {
1942 printk(KERN_ERR PFX "cannot request PCI regions\n");
1943 goto err_disable_device;
1944 }
1945
1946 mutex_init(&default_par->open_lock);
1947 default_par->riva.Architecture = riva_get_arch(pd);
1948
1949 default_par->Chipset = (pd->vendor << 16) | pd->device;
1950 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1951
1952 if(default_par->riva.Architecture == 0) {
1953 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1954 ret=-ENODEV;
1955 goto err_release_region;
1956 }
1957 if(default_par->riva.Architecture == NV_ARCH_10 ||
1958 default_par->riva.Architecture == NV_ARCH_20 ||
1959 default_par->riva.Architecture == NV_ARCH_30) {
1960 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1961 } else {
1962 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
1963 }
1964
1965 default_par->FlatPanel = flatpanel;
1966 if (flatpanel == 1)
1967 printk(KERN_INFO PFX "flatpanel support enabled\n");
1968 default_par->forceCRTC = forceCRTC;
1969
1970 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
1971 rivafb_fix.smem_len = pci_resource_len(pd, 1);
1972
1973 {
1974
1975 unsigned short cmd;
1976
1977 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1978 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1979 pci_write_config_word(pd, PCI_COMMAND, cmd);
1980 }
1981
1982 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
1983 rivafb_fix.smem_start = pci_resource_start(pd, 1);
1984
1985 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
1986 rivafb_fix.mmio_len);
1987 if (!default_par->ctrl_base) {
1988 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1989 ret = -EIO;
1990 goto err_release_region;
1991 }
1992
1993 switch (default_par->riva.Architecture) {
1994 case NV_ARCH_03:
1995
1996
1997
1998
1999 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2000 if (!default_par->riva.PRAMIN) {
2001 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2002 ret = -EIO;
2003 goto err_iounmap_ctrl_base;
2004 }
2005 break;
2006 case NV_ARCH_04:
2007 case NV_ARCH_10:
2008 case NV_ARCH_20:
2009 case NV_ARCH_30:
2010 default_par->riva.PCRTC0 =
2011 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2012 default_par->riva.PRAMIN =
2013 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2014 break;
2015 }
2016 riva_common_setup(default_par);
2017
2018 if (default_par->riva.Architecture == NV_ARCH_03) {
2019 default_par->riva.PCRTC = default_par->riva.PCRTC0
2020 = default_par->riva.PGRAPH;
2021 }
2022
2023 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2024 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2025 info->screen_base = ioremap(rivafb_fix.smem_start,
2026 rivafb_fix.smem_len);
2027 if (!info->screen_base) {
2028 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2029 ret = -EIO;
2030 goto err_iounmap_pramin;
2031 }
2032
2033#ifdef CONFIG_MTRR
2034 if (!nomtrr) {
2035 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2036 rivafb_fix.smem_len,
2037 MTRR_TYPE_WRCOMB, 1);
2038 if (default_par->mtrr.vram < 0) {
2039 printk(KERN_ERR PFX "unable to setup MTRR\n");
2040 } else {
2041 default_par->mtrr.vram_valid = 1;
2042
2043 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2044 }
2045 }
2046#endif
2047
2048 info->fbops = &riva_fb_ops;
2049 info->fix = rivafb_fix;
2050 riva_get_EDID(info, pd);
2051 riva_get_edidinfo(info);
2052
2053 ret=riva_set_fbinfo(info);
2054 if (ret < 0) {
2055 printk(KERN_ERR PFX "error setting initial video mode\n");
2056 goto err_iounmap_screen_base;
2057 }
2058
2059 fb_destroy_modedb(info->monspecs.modedb);
2060 info->monspecs.modedb = NULL;
2061
2062 pci_set_drvdata(pd, info);
2063
2064 if (backlight)
2065 riva_bl_init(info->par);
2066
2067 ret = register_framebuffer(info);
2068 if (ret < 0) {
2069 printk(KERN_ERR PFX
2070 "error registering riva framebuffer\n");
2071 goto err_iounmap_screen_base;
2072 }
2073
2074 printk(KERN_INFO PFX
2075 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2076 info->fix.id,
2077 RIVAFB_VERSION,
2078 info->fix.smem_len / (1024 * 1024),
2079 info->fix.smem_start);
2080
2081 NVTRACE_LEAVE();
2082 return 0;
2083
2084err_iounmap_screen_base:
2085#ifdef CONFIG_FB_RIVA_I2C
2086 riva_delete_i2c_busses(info->par);
2087#endif
2088 iounmap(info->screen_base);
2089err_iounmap_pramin:
2090 if (default_par->riva.Architecture == NV_ARCH_03)
2091 iounmap(default_par->riva.PRAMIN);
2092err_iounmap_ctrl_base:
2093 iounmap(default_par->ctrl_base);
2094err_release_region:
2095 pci_release_regions(pd);
2096err_disable_device:
2097err_free_pixmap:
2098 kfree(info->pixmap.addr);
2099err_framebuffer_release:
2100 framebuffer_release(info);
2101err_ret:
2102 return ret;
2103}
2104
2105static void __devexit rivafb_remove(struct pci_dev *pd)
2106{
2107 struct fb_info *info = pci_get_drvdata(pd);
2108 struct riva_par *par = info->par;
2109
2110 NVTRACE_ENTER();
2111
2112#ifdef CONFIG_FB_RIVA_I2C
2113 riva_delete_i2c_busses(par);
2114 kfree(par->EDID);
2115#endif
2116
2117 unregister_framebuffer(info);
2118
2119 riva_bl_exit(info);
2120
2121#ifdef CONFIG_MTRR
2122 if (par->mtrr.vram_valid)
2123 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2124 info->fix.smem_len);
2125#endif
2126
2127 iounmap(par->ctrl_base);
2128 iounmap(info->screen_base);
2129 if (par->riva.Architecture == NV_ARCH_03)
2130 iounmap(par->riva.PRAMIN);
2131 pci_release_regions(pd);
2132 kfree(info->pixmap.addr);
2133 framebuffer_release(info);
2134 pci_set_drvdata(pd, NULL);
2135 NVTRACE_LEAVE();
2136}
2137
2138
2139
2140
2141
2142
2143
2144#ifndef MODULE
2145static int __devinit rivafb_setup(char *options)
2146{
2147 char *this_opt;
2148
2149 NVTRACE_ENTER();
2150 if (!options || !*options)
2151 return 0;
2152
2153 while ((this_opt = strsep(&options, ",")) != NULL) {
2154 if (!strncmp(this_opt, "forceCRTC", 9)) {
2155 char *p;
2156
2157 p = this_opt + 9;
2158 if (!*p || !*(++p)) continue;
2159 forceCRTC = *p - '0';
2160 if (forceCRTC < 0 || forceCRTC > 1)
2161 forceCRTC = -1;
2162 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2163 flatpanel = 1;
2164 } else if (!strncmp(this_opt, "backlight:", 10)) {
2165 backlight = simple_strtoul(this_opt+10, NULL, 0);
2166#ifdef CONFIG_MTRR
2167 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2168 nomtrr = 1;
2169#endif
2170 } else if (!strncmp(this_opt, "strictmode", 10)) {
2171 strictmode = 1;
2172 } else if (!strncmp(this_opt, "noaccel", 7)) {
2173 noaccel = 1;
2174 } else
2175 mode_option = this_opt;
2176 }
2177 NVTRACE_LEAVE();
2178 return 0;
2179}
2180#endif
2181
2182static struct pci_driver rivafb_driver = {
2183 .name = "rivafb",
2184 .id_table = rivafb_pci_tbl,
2185 .probe = rivafb_probe,
2186 .remove = __devexit_p(rivafb_remove),
2187};
2188
2189
2190
2191
2192
2193
2194
2195
2196
2197static int __devinit rivafb_init(void)
2198{
2199#ifndef MODULE
2200 char *option = NULL;
2201
2202 if (fb_get_options("rivafb", &option))
2203 return -ENODEV;
2204 rivafb_setup(option);
2205#endif
2206 return pci_register_driver(&rivafb_driver);
2207}
2208
2209
2210module_init(rivafb_init);
2211
2212static void __exit rivafb_exit(void)
2213{
2214 pci_unregister_driver(&rivafb_driver);
2215}
2216
2217module_exit(rivafb_exit);
2218
2219module_param(noaccel, bool, 0);
2220MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2221module_param(flatpanel, int, 0);
2222MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2223module_param(forceCRTC, int, 0);
2224MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2225#ifdef CONFIG_MTRR
2226module_param(nomtrr, bool, 0);
2227MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2228#endif
2229module_param(strictmode, bool, 0);
2230MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2231
2232MODULE_AUTHOR("Ani Joshi, maintainer");
2233MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2234MODULE_LICENSE("GPL");
2235
