1/* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public 7 * License as published by the Free Software Foundation; 8 * either version 2, or (at your option) any later version. 9 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even 12 * the implied warranty of MERCHANTABILITY or FITNESS FOR 13 * A PARTICULAR PURPOSE.See the GNU General Public License 14 * for more details. 15 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 20 */ 21 22#ifndef __SHARE_H__ 23#define __SHARE_H__ 24 25/* Define Return Value */ 26#define FAIL -1 27#define OK 1 28 29#ifndef NULL 30#define NULL 0 31#endif 32 33/* Define Bit Field */ 34#define BIT0 0x01 35#define BIT1 0x02 36#define BIT2 0x04 37#define BIT3 0x08 38#define BIT4 0x10 39#define BIT5 0x20 40#define BIT6 0x40 41#define BIT7 0x80 42 43/* Video Memory Size */ 44#define VIDEO_MEMORY_SIZE_16M 0x1000000 45 46/* Definition Mode Index 47*/ 48#define VIA_RES_640X480 0 49#define VIA_RES_800X600 1 50#define VIA_RES_1024X768 2 51#define VIA_RES_1152X864 3 52#define VIA_RES_1280X1024 4 53#define VIA_RES_1600X1200 5 54#define VIA_RES_1440X1050 6 55#define VIA_RES_1280X768 7 56#define VIA_RES_1280X960 8 57#define VIA_RES_1920X1440 9 58#define VIA_RES_848X480 10 59#define VIA_RES_1400X1050 11 60#define VIA_RES_720X480 12 61#define VIA_RES_720X576 13 62#define VIA_RES_1024X512 14 63#define VIA_RES_856X480 15 64#define VIA_RES_1024X576 16 65#define VIA_RES_640X400 17 66#define VIA_RES_1280X720 18 67#define VIA_RES_1920X1080 19 68#define VIA_RES_800X480 20 69#define VIA_RES_1368X768 21 70#define VIA_RES_1024X600 22 71#define VIA_RES_1280X800 23 72#define VIA_RES_1680X1050 24 73#define VIA_RES_960X600 25 74#define VIA_RES_1000X600 26 75#define VIA_RES_1088X612 27 76#define VIA_RES_1152X720 28 77#define VIA_RES_1200X720 29 78#define VIA_RES_1280X600 30 79#define VIA_RES_1360X768 31 80#define VIA_RES_1366X768 32 81#define VIA_RES_1440X900 33 82#define VIA_RES_1600X900 34 83#define VIA_RES_1600X1024 35 84#define VIA_RES_1792X1344 36 85#define VIA_RES_1856X1392 37 86#define VIA_RES_1920X1200 38 87#define VIA_RES_2048X1536 39 88#define VIA_RES_480X640 40 89 90/*Reduce Blanking*/ 91#define VIA_RES_1360X768_RB 131 92#define VIA_RES_1440X900_RB 133 93#define VIA_RES_1400X1050_RB 111 94#define VIA_RES_1600X900_RB 134 95#define VIA_RES_1680X1050_RB 124 96#define VIA_RES_1920X1080_RB 119 97#define VIA_RES_1920X1200_RB 138 98 99#define VIA_RES_INVALID 255 100 101/* standard VGA IO port 102*/ 103#define VIARMisc 0x3CC 104#define VIAWMisc 0x3C2 105#define VIAStatus 0x3DA 106#define VIACR 0x3D4 107#define VIASR 0x3C4 108#define VIAGR 0x3CE 109#define VIAAR 0x3C0 110 111#define StdCR 0x19 112#define StdSR 0x04 113#define StdGR 0x09 114#define StdAR 0x14 115 116#define PatchCR 11 117 118/* Display path */ 119#define IGA1 1 120#define IGA2 2 121#define IGA1_IGA2 3 122 123/* Define Color Depth */ 124#define MODE_8BPP 1 125#define MODE_16BPP 2 126#define MODE_32BPP 4 127 128#define GR20 0x20 129#define GR21 0x21 130#define GR22 0x22 131 132/* Sequencer Registers */ 133#define SR01 0x01 134#define SR10 0x10 135#define SR12 0x12 136#define SR15 0x15 137#define SR16 0x16 138#define SR17 0x17 139#define SR18 0x18 140#define SR1B 0x1B 141#define SR1A 0x1A 142#define SR1C 0x1C 143#define SR1D 0x1D 144#define SR1E 0x1E 145#define SR1F 0x1F 146#define SR20 0x20 147#define SR21 0x21 148#define SR22 0x22 149#define SR2A 0x2A 150#define SR2D 0x2D 151#define SR2E 0x2E 152 153#define SR30 0x30 154#define SR39 0x39 155#define SR3D 0x3D 156#define SR3E 0x3E 157#define SR3F 0x3F 158#define SR40 0x40 159#define SR43 0x43 160#define SR44 0x44 161#define SR45 0x45 162#define SR46 0x46 163#define SR47 0x47 164#define SR48 0x48 165#define SR49 0x49 166#define SR4A 0x4A 167#define SR4B 0x4B 168#define SR4C 0x4C 169#define SR52 0x52 170#define SR57 0x57 171#define SR58 0x58 172#define SR59 0x59 173#define SR5D 0x5D 174#define SR5E 0x5E 175#define SR65 0x65 176 177/* CRT Controller Registers */ 178#define CR00 0x00 179#define CR01 0x01 180#define CR02 0x02 181#define CR03 0x03 182#define CR04 0x04 183#define CR05 0x05 184#define CR06 0x06 185#define CR07 0x07 186#define CR08 0x08 187#define CR09 0x09 188#define CR0A 0x0A 189#define CR0B 0x0B 190#define CR0C 0x0C 191#define CR0D 0x0D 192#define CR0E 0x0E 193#define CR0F 0x0F 194#define CR10 0x10 195#define CR11 0x11 196#define CR12 0x12 197#define CR13 0x13 198#define CR14 0x14 199#define CR15 0x15 200#define CR16 0x16 201#define CR17 0x17 202#define CR18 0x18 203 204/* Extend CRT Controller Registers */ 205#define CR30 0x30 206#define CR31 0x31 207#define CR32 0x32 208#define CR33 0x33 209#define CR34 0x34 210#define CR35 0x35 211#define CR36 0x36 212#define CR37 0x37 213#define CR38 0x38 214#define CR39 0x39 215#define CR3A 0x3A 216#define CR3B 0x3B 217#define CR3C 0x3C 218#define CR3D 0x3D 219#define CR3E 0x3E 220#define CR3F 0x3F 221#define CR40 0x40 222#define CR41 0x41 223#define CR42 0x42 224#define CR43 0x43 225#define CR44 0x44 226#define CR45 0x45 227#define CR46 0x46 228#define CR47 0x47 229#define CR48 0x48 230#define CR49 0x49 231#define CR4A 0x4A 232#define CR4B 0x4B 233#define CR4C 0x4C 234#define CR4D 0x4D 235#define CR4E 0x4E 236#define CR4F 0x4F 237#define CR50 0x50 238#define CR51 0x51 239#define CR52 0x52 240#define CR53 0x53 241#define CR54 0x54 242#define CR55 0x55 243#define CR56 0x56 244#define CR57 0x57 245#define CR58 0x58 246#define CR59 0x59 247#define CR5A 0x5A 248#define CR5B 0x5B 249#define CR5C 0x5C 250#define CR5D 0x5D 251#define CR5E 0x5E 252#define CR5F 0x5F 253#define CR60 0x60 254#define CR61 0x61 255#define CR62 0x62 256#define CR63 0x63 257#define CR64 0x64 258#define CR65 0x65 259#define CR66 0x66 260#define CR67 0x67 261#define CR68 0x68 262#define CR69 0x69 263#define CR6A 0x6A 264#define CR6B 0x6B 265#define CR6C 0x6C 266#define CR6D 0x6D 267#define CR6E 0x6E 268#define CR6F 0x6F 269#define CR70 0x70 270#define CR71 0x71 271#define CR72 0x72 272#define CR73 0x73 273#define CR74 0x74 274#define CR75 0x75 275#define CR76 0x76 276#define CR77 0x77 277#define CR78 0x78 278#define CR79 0x79 279#define CR7A 0x7A 280#define CR7B 0x7B 281#define CR7C 0x7C 282#define CR7D 0x7D 283#define CR7E 0x7E 284#define CR7F 0x7F 285#define CR80 0x80 286#define CR81 0x81 287#define CR82 0x82 288#define CR83 0x83 289#define CR84 0x84 290#define CR85 0x85 291#define CR86 0x86 292#define CR87 0x87 293#define CR88 0x88 294#define CR89 0x89 295#define CR8A 0x8A 296#define CR8B 0x8B 297#define CR8C 0x8C 298#define CR8D 0x8D 299#define CR8E 0x8E 300#define CR8F 0x8F 301#define CR90 0x90 302#define CR91 0x91 303#define CR92 0x92 304#define CR93 0x93 305#define CR94 0x94 306#define CR95 0x95 307#define CR96 0x96 308#define CR97 0x97 309#define CR98 0x98 310#define CR99 0x99 311#define CR9A 0x9A 312#define CR9B 0x9B 313#define CR9C 0x9C 314#define CR9D 0x9D 315#define CR9E 0x9E 316#define CR9F 0x9F 317#define CRA0 0xA0 318#define CRA1 0xA1 319#define CRA2 0xA2 320#define CRA3 0xA3 321#define CRD2 0xD2 322#define CRD3 0xD3 323#define CRD4 0xD4 324 325/* LUT Table*/ 326#define LUT_DATA 0x3C9 /* DACDATA */ 327#define LUT_INDEX_READ 0x3C7 /* DACRX */ 328#define LUT_INDEX_WRITE 0x3C8 /* DACWX */ 329#define DACMASK 0x3C6 330 331/* Definition Device */ 332#define DEVICE_CRT 0x01 333#define DEVICE_DVI 0x03 334#define DEVICE_LCD 0x04 335 336/* Device output interface */ 337#define INTERFACE_NONE 0x00 338#define INTERFACE_ANALOG_RGB 0x01 339#define INTERFACE_DVP0 0x02 340#define INTERFACE_DVP1 0x03 341#define INTERFACE_DFP_HIGH 0x04 342#define INTERFACE_DFP_LOW 0x05 343#define INTERFACE_DFP 0x06 344#define INTERFACE_LVDS0 0x07 345#define INTERFACE_LVDS1 0x08 346#define INTERFACE_LVDS0LVDS1 0x09 347#define INTERFACE_TMDS 0x0A 348 349#define HW_LAYOUT_LCD_ONLY 0x01 350#define HW_LAYOUT_DVI_ONLY 0x02 351#define HW_LAYOUT_LCD_DVI 0x03 352#define HW_LAYOUT_LCD1_LCD2 0x04 353#define HW_LAYOUT_LCD_EXTERNAL_LCD2 0x10 354 355/* Definition Refresh Rate */ 356#define REFRESH_50 50 357#define REFRESH_60 60 358#define REFRESH_75 75 359#define REFRESH_85 85 360#define REFRESH_100 100 361#define REFRESH_120 120 362 363/* Definition Sync Polarity*/ 364#define NEGATIVE 1 365#define POSITIVE 0 366 367/*480x640@60 Sync Polarity (GTF) 368*/ 369#define M480X640_R60_HSP NEGATIVE 370#define M480X640_R60_VSP POSITIVE 371 372/*640x480@60 Sync Polarity (VESA Mode) 373*/ 374#define M640X480_R60_HSP NEGATIVE 375#define M640X480_R60_VSP NEGATIVE 376 377/*640x480@75 Sync Polarity (VESA Mode) 378*/ 379#define M640X480_R75_HSP NEGATIVE 380#define M640X480_R75_VSP NEGATIVE 381 382/*640x480@85 Sync Polarity (VESA Mode) 383*/ 384#define M640X480_R85_HSP NEGATIVE 385#define M640X480_R85_VSP NEGATIVE 386 387/*640x480@100 Sync Polarity (GTF Mode) 388*/ 389#define M640X480_R100_HSP NEGATIVE 390#define M640X480_R100_VSP POSITIVE 391 392/*640x480@120 Sync Polarity (GTF Mode) 393*/ 394#define M640X480_R120_HSP NEGATIVE 395#define M640X480_R120_VSP POSITIVE 396 397/*720x480@60 Sync Polarity (GTF Mode) 398*/ 399#define M720X480_R60_HSP NEGATIVE 400#define M720X480_R60_VSP POSITIVE 401 402/*720x576@60 Sync Polarity (GTF Mode) 403*/ 404#define M720X576_R60_HSP NEGATIVE 405#define M720X576_R60_VSP POSITIVE 406 407/*800x600@60 Sync Polarity (VESA Mode) 408*/ 409#define M800X600_R60_HSP POSITIVE 410#define M800X600_R60_VSP POSITIVE 411 412/*800x600@75 Sync Polarity (VESA Mode) 413*/ 414#define M800X600_R75_HSP POSITIVE 415#define M800X600_R75_VSP POSITIVE 416 417/*800x600@85 Sync Polarity (VESA Mode) 418*/ 419#define M800X600_R85_HSP POSITIVE 420#define M800X600_R85_VSP POSITIVE 421 422/*800x600@100 Sync Polarity (GTF Mode) 423*/ 424#define M800X600_R100_HSP NEGATIVE 425#define M800X600_R100_VSP POSITIVE 426 427/*800x600@120 Sync Polarity (GTF Mode) 428*/ 429#define M800X600_R120_HSP NEGATIVE 430#define M800X600_R120_VSP POSITIVE 431 432/*800x480@60 Sync Polarity (CVT Mode) 433*/ 434#define M800X480_R60_HSP NEGATIVE 435#define M800X480_R60_VSP POSITIVE 436 437/*848x480@60 Sync Polarity (CVT Mode) 438*/ 439#define M848X480_R60_HSP NEGATIVE 440#define M848X480_R60_VSP POSITIVE 441 442/*852x480@60 Sync Polarity (GTF Mode) 443*/ 444#define M852X480_R60_HSP NEGATIVE 445#define M852X480_R60_VSP POSITIVE 446 447/*1024x512@60 Sync Polarity (GTF Mode) 448*/ 449#define M1024X512_R60_HSP NEGATIVE 450#define M1024X512_R60_VSP POSITIVE 451 452/*1024x600@60 Sync Polarity (GTF Mode) 453*/ 454#define M1024X600_R60_HSP NEGATIVE 455#define M1024X600_R60_VSP POSITIVE 456 457/*1024x768@60 Sync Polarity (VESA Mode) 458*/ 459#define M1024X768_R60_HSP NEGATIVE 460#define M1024X768_R60_VSP NEGATIVE 461 462/*1024x768@75 Sync Polarity (VESA Mode) 463*/ 464#define M1024X768_R75_HSP POSITIVE 465#define M1024X768_R75_VSP POSITIVE 466 467/*1024x768@85 Sync Polarity (VESA Mode) 468*/ 469#define M1024X768_R85_HSP POSITIVE 470#define M1024X768_R85_VSP POSITIVE 471 472/*1024x768@100 Sync Polarity (GTF Mode) 473*/ 474#define M1024X768_R100_HSP NEGATIVE 475#define M1024X768_R100_VSP POSITIVE 476 477/*1152x864@75 Sync Polarity (VESA Mode) 478*/ 479#define M1152X864_R75_HSP POSITIVE 480#define M1152X864_R75_VSP POSITIVE 481 482/*1280x720@60 Sync Polarity (GTF Mode) 483*/ 484#define M1280X720_R60_HSP NEGATIVE 485#define M1280X720_R60_VSP POSITIVE 486 487/* 1280x768@50 Sync Polarity (GTF Mode) */ 488#define M1280X768_R50_HSP NEGATIVE 489#define M1280X768_R50_VSP POSITIVE 490 491/*1280x768@60 Sync Polarity (GTF Mode) 492*/ 493#define M1280X768_R60_HSP NEGATIVE 494#define M1280X768_R60_VSP POSITIVE 495 496/*1280x800@60 Sync Polarity (CVT Mode) 497*/ 498#define M1280X800_R60_HSP NEGATIVE 499#define M1280X800_R60_VSP POSITIVE 500 501/*1280x960@60 Sync Polarity (VESA Mode) 502*/ 503#define M1280X960_R60_HSP POSITIVE 504#define M1280X960_R60_VSP POSITIVE 505 506/*1280x1024@60 Sync Polarity (VESA Mode) 507*/ 508#define M1280X1024_R60_HSP POSITIVE 509#define M1280X1024_R60_VSP POSITIVE 510 511/* 1360x768@60 Sync Polarity (CVT Mode) */ 512#define M1360X768_R60_HSP POSITIVE 513#define M1360X768_R60_VSP POSITIVE 514 515/* 1360x768@60 Sync Polarity (CVT Reduce Blanking Mode) */ 516#define M1360X768_RB_R60_HSP POSITIVE 517#define M1360X768_RB_R60_VSP NEGATIVE 518 519/* 1368x768@50 Sync Polarity (GTF Mode) */ 520#define M1368X768_R50_HSP NEGATIVE 521#define M1368X768_R50_VSP POSITIVE 522 523/* 1368x768@60 Sync Polarity (VESA Mode) */ 524#define M1368X768_R60_HSP NEGATIVE 525#define M1368X768_R60_VSP POSITIVE 526 527/*1280x1024@75 Sync Polarity (VESA Mode) 528*/ 529#define M1280X1024_R75_HSP POSITIVE 530#define M1280X1024_R75_VSP POSITIVE 531 532/*1280x1024@85 Sync Polarity (VESA Mode) 533*/ 534#define M1280X1024_R85_HSP POSITIVE 535#define M1280X1024_R85_VSP POSITIVE 536 537/*1440x1050@60 Sync Polarity (GTF Mode) 538*/ 539#define M1440X1050_R60_HSP NEGATIVE 540#define M1440X1050_R60_VSP POSITIVE 541 542/*1600x1200@60 Sync Polarity (VESA Mode) 543*/ 544#define M1600X1200_R60_HSP POSITIVE 545#define M1600X1200_R60_VSP POSITIVE 546 547/*1600x1200@75 Sync Polarity (VESA Mode) 548*/ 549#define M1600X1200_R75_HSP POSITIVE 550#define M1600X1200_R75_VSP POSITIVE 551 552/* 1680x1050@60 Sync Polarity (CVT Mode) */ 553#define M1680x1050_R60_HSP NEGATIVE 554#define M1680x1050_R60_VSP NEGATIVE 555 556/* 1680x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */ 557#define M1680x1050_RB_R60_HSP POSITIVE 558#define M1680x1050_RB_R60_VSP NEGATIVE 559 560/* 1680x1050@75 Sync Polarity (CVT Mode) */ 561#define M1680x1050_R75_HSP NEGATIVE 562#define M1680x1050_R75_VSP POSITIVE 563 564/*1920x1080@60 Sync Polarity (CVT Mode) 565*/ 566#define M1920X1080_R60_HSP NEGATIVE 567#define M1920X1080_R60_VSP POSITIVE 568 569/* 1920x1080@60 Sync Polarity (CVT Reduce Blanking Mode) */ 570#define M1920X1080_RB_R60_HSP POSITIVE 571#define M1920X1080_RB_R60_VSP NEGATIVE 572 573/*1920x1440@60 Sync Polarity (VESA Mode) 574*/ 575#define M1920X1440_R60_HSP NEGATIVE 576#define M1920X1440_R60_VSP POSITIVE 577 578/*1920x1440@75 Sync Polarity (VESA Mode) 579*/ 580#define M1920X1440_R75_HSP NEGATIVE 581#define M1920X1440_R75_VSP POSITIVE 582 583#if 0 584/* 1400x1050@60 Sync Polarity (VESA Mode) */ 585#define M1400X1050_R60_HSP NEGATIVE 586#define M1400X1050_R60_VSP NEGATIVE 587#endif 588 589/* 1400x1050@60 Sync Polarity (CVT Mode) */ 590#define M1400X1050_R60_HSP NEGATIVE 591#define M1400X1050_R60_VSP POSITIVE 592 593/* 1400x1050@60 Sync Polarity (CVT Reduce Blanking Mode) */ 594#define M1400X1050_RB_R60_HSP POSITIVE 595#define M1400X1050_RB_R60_VSP NEGATIVE 596 597/* 1400x1050@75 Sync Polarity (CVT Mode) */ 598#define M1400X1050_R75_HSP NEGATIVE 599#define M1400X1050_R75_VSP POSITIVE 600 601/* 960x600@60 Sync Polarity (CVT Mode) */ 602#define M960X600_R60_HSP NEGATIVE 603#define M960X600_R60_VSP POSITIVE 604 605/* 1000x600@60 Sync Polarity (GTF Mode) */ 606#define M1000X600_R60_HSP NEGATIVE 607#define M1000X600_R60_VSP POSITIVE 608 609/* 1024x576@60 Sync Polarity (GTF Mode) */ 610#define M1024X576_R60_HSP NEGATIVE 611#define M1024X576_R60_VSP POSITIVE 612 613/*1024x600@60 Sync Polarity (GTF Mode)*/ 614#define M1024X600_R60_HSP NEGATIVE 615#define M1024X600_R60_VSP POSITIVE 616 617/* 1088x612@60 Sync Polarity (CVT Mode) */ 618#define M1088X612_R60_HSP NEGATIVE 619#define M1088X612_R60_VSP POSITIVE 620 621/* 1152x720@60 Sync Polarity (CVT Mode) */ 622#define M1152X720_R60_HSP NEGATIVE 623#define M1152X720_R60_VSP POSITIVE 624 625/* 1200x720@60 Sync Polarity (GTF Mode) */ 626#define M1200X720_R60_HSP NEGATIVE 627#define M1200X720_R60_VSP POSITIVE 628 629/* 1280x600@60 Sync Polarity (GTF Mode) */ 630#define M1280x600_R60_HSP NEGATIVE 631#define M1280x600_R60_VSP POSITIVE 632 633/* 1280x720@50 Sync Polarity (GTF Mode) */ 634#define M1280X720_R50_HSP NEGATIVE 635#define M1280X720_R50_VSP POSITIVE 636 637/* 1280x720@60 Sync Polarity (CEA Mode) */ 638#define M1280X720_CEA_R60_HSP POSITIVE 639#define M1280X720_CEA_R60_VSP POSITIVE 640 641/* 1440x900@60 Sync Polarity (CVT Mode) */ 642#define M1440X900_R60_HSP NEGATIVE 643#define M1440X900_R60_VSP POSITIVE 644 645/* 1440x900@75 Sync Polarity (CVT Mode) */ 646#define M1440X900_R75_HSP NEGATIVE 647#define M1440X900_R75_VSP POSITIVE 648 649/* 1440x900@60 Sync Polarity (CVT Reduce Blanking Mode) */ 650#define M1440X900_RB_R60_HSP POSITIVE 651#define M1440X900_RB_R60_VSP NEGATIVE 652 653/* 1600x900@60 Sync Polarity (CVT Mode) */ 654#define M1600X900_R60_HSP NEGATIVE 655#define M1600X900_R60_VSP POSITIVE 656 657/* 1600x900@60 Sync Polarity (CVT Reduce Blanking Mode) */ 658#define M1600X900_RB_R60_HSP POSITIVE 659#define M1600X900_RB_R60_VSP NEGATIVE 660 661/* 1600x1024@60 Sync Polarity (GTF Mode) */ 662#define M1600X1024_R60_HSP NEGATIVE 663#define M1600X1024_R60_VSP POSITIVE 664 665/* 1792x1344@60 Sync Polarity (DMT Mode) */ 666#define M1792x1344_R60_HSP NEGATIVE 667#define M1792x1344_R60_VSP POSITIVE 668 669/* 1856x1392@60 Sync Polarity (DMT Mode) */ 670#define M1856x1392_R60_HSP NEGATIVE 671#define M1856x1392_R60_VSP POSITIVE 672 673/* 1920x1200@60 Sync Polarity (CVT Mode) */ 674#define M1920X1200_R60_HSP NEGATIVE 675#define M1920X1200_R60_VSP POSITIVE 676 677/* 1920x1200@60 Sync Polarity (CVT Reduce Blanking Mode) */ 678#define M1920X1200_RB_R60_HSP POSITIVE 679#define M1920X1200_RB_R60_VSP NEGATIVE 680 681/* 1920x1080@60 Sync Polarity (CEA Mode) */ 682#define M1920X1080_CEA_R60_HSP POSITIVE 683#define M1920X1080_CEA_R60_VSP POSITIVE 684 685/* 2048x1536@60 Sync Polarity (CVT Mode) */ 686#define M2048x1536_R60_HSP NEGATIVE 687#define M2048x1536_R60_VSP POSITIVE 688 689/* define PLL index: */ 690#define CLK_25_175M 25175000 691#define CLK_26_880M 26880000 692#define CLK_29_581M 29581000 693#define CLK_31_490M 31490000 694#define CLK_31_500M 31500000 695#define CLK_31_728M 31728000 696#define CLK_32_668M 32688000 697#define CLK_36_000M 36000000 698#define CLK_40_000M 40000000 699#define CLK_41_291M 41291000 700#define CLK_43_163M 43163000 701#define CLK_45_250M 45250000 /* 45.46MHz */ 702#define CLK_46_000M 46000000 703#define CLK_46_996M 46996000 704#define CLK_48_000M 48000000 705#define CLK_48_875M 48875000 706#define CLK_49_500M 49500000 707#define CLK_52_406M 52406000 708#define CLK_52_977M 52977000 709#define CLK_56_250M 56250000 710#define CLK_60_466M 60466000 711#define CLK_61_500M 61500000 712#define CLK_65_000M 65000000 713#define CLK_65_178M 65178000 714#define CLK_66_750M 66750000 /* 67.116MHz */ 715#define CLK_68_179M 68179000 716#define CLK_69_924M 69924000 717#define CLK_70_159M 70159000 718#define CLK_72_000M 72000000 719#define CLK_74_270M 74270000 720#define CLK_78_750M 78750000 721#define CLK_80_136M 80136000 722#define CLK_83_375M 83375000 723#define CLK_83_950M 83950000 724#define CLK_84_750M 84750000 /* 84.537Mhz */ 725#define CLK_85_860M 85860000 726#define CLK_88_750M 88750000 727#define CLK_94_500M 94500000 728#define CLK_97_750M 97750000 729#define CLK_101_000M 101000000 730#define CLK_106_500M 106500000 731#define CLK_108_000M 108000000 732#define CLK_113_309M 113309000 733#define CLK_118_840M 118840000 734#define CLK_119_000M 119000000 735#define CLK_121_750M 121750000 /* 121.704MHz */ 736#define CLK_125_104M 125104000 737#define CLK_133_308M 133308000 738#define CLK_135_000M 135000000 739#define CLK_136_700M 136700000 740#define CLK_138_400M 138400000 741#define CLK_146_760M 146760000 742#define CLK_148_500M 148500000 743 744#define CLK_153_920M 153920000 745#define CLK_156_000M 156000000 746#define CLK_157_500M 157500000 747#define CLK_162_000M 162000000 748#define CLK_187_000M 187000000 749#define CLK_193_295M 193295000 750#define CLK_202_500M 202500000 751#define CLK_204_000M 204000000 752#define CLK_218_500M 218500000 753#define CLK_234_000M 234000000 754#define CLK_267_250M 267250000 755#define CLK_297_500M 297500000 756#define CLK_74_481M 74481000 757#define CLK_172_798M 172798000 758#define CLK_122_614M 122614000 759 760/* CLE266 PLL value 761*/ 762#define CLE266_PLL_25_175M 0x0000C763 763#define CLE266_PLL_26_880M 0x0000440F 764#define CLE266_PLL_29_581M 0x00008421 765#define CLE266_PLL_31_490M 0x00004721 766#define CLE266_PLL_31_500M 0x0000C3B5 767#define CLE266_PLL_31_728M 0x0000471F 768#define CLE266_PLL_32_668M 0x0000C449 769#define CLE266_PLL_36_000M 0x0000C5E5 770#define CLE266_PLL_40_000M 0x0000C459 771#define CLE266_PLL_41_291M 0x00004417 772#define CLE266_PLL_43_163M 0x0000C579 773#define CLE266_PLL_45_250M 0x0000C57F /* 45.46MHz */ 774#define CLE266_PLL_46_000M 0x0000875A 775#define CLE266_PLL_46_996M 0x0000C4E9 776#define CLE266_PLL_48_000M 0x00001443 777#define CLE266_PLL_48_875M 0x00001D63 778#define CLE266_PLL_49_500M 0x00008653 779#define CLE266_PLL_52_406M 0x0000C475 780#define CLE266_PLL_52_977M 0x00004525 781#define CLE266_PLL_56_250M 0x000047B7 782#define CLE266_PLL_60_466M 0x0000494C 783#define CLE266_PLL_61_500M 0x00001456 784#define CLE266_PLL_65_000M 0x000086ED 785#define CLE266_PLL_65_178M 0x0000855B 786#define CLE266_PLL_66_750M 0x0000844B /* 67.116MHz */ 787#define CLE266_PLL_68_179M 0x00000413 788#define CLE266_PLL_69_924M 0x00001153 789#define CLE266_PLL_70_159M 0x00001462 790#define CLE266_PLL_72_000M 0x00001879 791#define CLE266_PLL_74_270M 0x00004853 792#define CLE266_PLL_78_750M 0x00004321 793#define CLE266_PLL_80_136M 0x0000051C 794#define CLE266_PLL_83_375M 0x0000C25D 795#define CLE266_PLL_83_950M 0x00000729 796#define CLE266_PLL_84_750M 0x00008576 /* 84.537MHz */ 797#define CLE266_PLL_85_860M 0x00004754 798#define CLE266_PLL_88_750M 0x0000051F 799#define CLE266_PLL_94_500M 0x00000521 800#define CLE266_PLL_97_750M 0x00004652 801#define CLE266_PLL_101_000M 0x0000497F 802#define CLE266_PLL_106_500M 0x00008477 /* 106.491463 MHz */ 803#define CLE266_PLL_108_000M 0x00008479 804#define CLE266_PLL_113_309M 0x00000C5F 805#define CLE266_PLL_118_840M 0x00004553 806#define CLE266_PLL_119_000M 0x00000D6C 807#define CLE266_PLL_121_750M 0x00004555 /* 121.704MHz */ 808#define CLE266_PLL_125_104M 0x000006B5 809#define CLE266_PLL_133_308M 0x0000465F 810#define CLE266_PLL_135_000M 0x0000455E 811#define CLE266_PLL_136_700M 0x00000C73 812#define CLE266_PLL_138_400M 0x00000957 813#define CLE266_PLL_146_760M 0x00004567 814#define CLE266_PLL_148_500M 0x00000853 815#define CLE266_PLL_153_920M 0x00000856 816#define CLE266_PLL_156_000M 0x0000456D 817#define CLE266_PLL_157_500M 0x000005B7 818#define CLE266_PLL_162_000M 0x00004571 819#define CLE266_PLL_187_000M 0x00000976 820#define CLE266_PLL_193_295M 0x0000086C 821#define CLE266_PLL_202_500M 0x00000763 822#define CLE266_PLL_204_000M 0x00000764 823#define CLE266_PLL_218_500M 0x0000065C 824#define CLE266_PLL_234_000M 0x00000662 825#define CLE266_PLL_267_250M 0x00000670 826#define CLE266_PLL_297_500M 0x000005E6 827#define CLE266_PLL_74_481M 0x0000051A 828#define CLE266_PLL_172_798M 0x00004579 829#define CLE266_PLL_122_614M 0x0000073C 830 831/* K800 PLL value 832*/ 833#define K800_PLL_25_175M 0x00539001 834#define K800_PLL_26_880M 0x001C8C80 835#define K800_PLL_29_581M 0x00409080 836#define K800_PLL_31_490M 0x006F9001 837#define K800_PLL_31_500M 0x008B9002 838#define K800_PLL_31_728M 0x00AF9003 839#define K800_PLL_32_668M 0x00909002 840#define K800_PLL_36_000M 0x009F9002 841#define K800_PLL_40_000M 0x00578C02 842#define K800_PLL_41_291M 0x00438C01 843#define K800_PLL_43_163M 0x00778C03 844#define K800_PLL_45_250M 0x007D8C83 /* 45.46MHz */ 845#define K800_PLL_46_000M 0x00658C02 846#define K800_PLL_46_996M 0x00818C83 847#define K800_PLL_48_000M 0x00848C83 848#define K800_PLL_48_875M 0x00508C81 849#define K800_PLL_49_500M 0x00518C01 850#define K800_PLL_52_406M 0x00738C02 851#define K800_PLL_52_977M 0x00928C83 852#define K800_PLL_56_250M 0x007C8C02 853#define K800_PLL_60_466M 0x00A78C83 854#define K800_PLL_61_500M 0x00AA8C83 855#define K800_PLL_65_000M 0x006B8C01 856#define K800_PLL_65_178M 0x00B48C83 857#define K800_PLL_66_750M 0x00948C82 /* 67.116MHz */ 858#define K800_PLL_68_179M 0x00708C01 859#define K800_PLL_69_924M 0x00C18C83 860#define K800_PLL_70_159M 0x00C28C83 861#define K800_PLL_72_000M 0x009F8C82 862#define K800_PLL_74_270M 0x00ce0c03 863#define K800_PLL_78_750M 0x00408801 864#define K800_PLL_80_136M 0x00428801 865#define K800_PLL_83_375M 0x005B0882 866#define K800_PLL_83_950M 0x00738803 867#define K800_PLL_84_750M 0x00748883 /* 84.477MHz */ 868#define K800_PLL_85_860M 0x00768883 869#define K800_PLL_88_750M 0x007A8883 870#define K800_PLL_94_500M 0x00828803 871#define K800_PLL_97_750M 0x00878883 872#define K800_PLL_101_000M 0x008B8883 873#define K800_PLL_106_500M 0x00758882 /* 106.491463 MHz */ 874#define K800_PLL_108_000M 0x00778882 875#define K800_PLL_113_309M 0x005D8881 876#define K800_PLL_118_840M 0x00A48883 877#define K800_PLL_119_000M 0x00838882 878#define K800_PLL_121_750M 0x00A88883 /* 121.704MHz */ 879#define K800_PLL_125_104M 0x00688801 880#define K800_PLL_133_308M 0x005D8801 881#define K800_PLL_135_000M 0x001A4081 882#define K800_PLL_136_700M 0x00BD8883 883#define K800_PLL_138_400M 0x00728881 884#define K800_PLL_146_760M 0x00CC8883 885#define K800_PLL_148_500M 0x00ce0803 886#define K800_PLL_153_920M 0x00548482 887#define K800_PLL_156_000M 0x006B8483 888#define K800_PLL_157_500M 0x00142080 889#define K800_PLL_162_000M 0x006F8483 890#define K800_PLL_187_000M 0x00818483 891#define K800_PLL_193_295M 0x004F8481 892#define K800_PLL_202_500M 0x00538481 893#define K800_PLL_204_000M 0x008D8483 894#define K800_PLL_218_500M 0x00978483 895#define K800_PLL_234_000M 0x00608401 896#define K800_PLL_267_250M 0x006E8481 897#define K800_PLL_297_500M 0x00A48402 898#define K800_PLL_74_481M 0x007B8C81 899#define K800_PLL_172_798M 0x00778483 900#define K800_PLL_122_614M 0x00878882 901 902/* PLL for VT3324 */ 903#define CX700_25_175M 0x008B1003 904#define CX700_26_719M 0x00931003 905#define CX700_26_880M 0x00941003 906#define CX700_29_581M 0x00A49003 907#define CX700_31_490M 0x00AE1003 908#define CX700_31_500M 0x00AE1003 909#define CX700_31_728M 0x00AF1003 910#define CX700_32_668M 0x00B51003 911#define CX700_36_000M 0x00C81003 912#define CX700_40_000M 0x006E0C03 913#define CX700_41_291M 0x00710C03 914#define CX700_43_163M 0x00770C03 915#define CX700_45_250M 0x007D0C03 /* 45.46MHz */ 916#define CX700_46_000M 0x007F0C03 917#define CX700_46_996M 0x00818C83 918#define CX700_48_000M 0x00840C03 919#define CX700_48_875M 0x00508C81 920#define CX700_49_500M 0x00880C03 921#define CX700_52_406M 0x00730C02 922#define CX700_52_977M 0x00920C03 923#define CX700_56_250M 0x009B0C03 924#define CX700_60_466M 0x00460C00 925#define CX700_61_500M 0x00AA0C03 926#define CX700_65_000M 0x006B0C01 927#define CX700_65_178M 0x006B0C01 928#define CX700_66_750M 0x00940C02 /*67.116MHz */ 929#define CX700_68_179M 0x00BC0C03 930#define CX700_69_924M 0x00C10C03 931#define CX700_70_159M 0x00C20C03 932#define CX700_72_000M 0x009F0C02 933#define CX700_74_270M 0x00CE0C03 934#define CX700_74_481M 0x00CE0C03 935#define CX700_78_750M 0x006C0803 936#define CX700_80_136M 0x006E0803 937#define CX700_83_375M 0x005B0882 938#define CX700_83_950M 0x00730803 939#define CX700_84_750M 0x00740803 /* 84.537Mhz */ 940#define CX700_85_860M 0x00760803 941#define CX700_88_750M 0x00AC8885 942#define CX700_94_500M 0x00820803 943#define CX700_97_750M 0x00870803 944#define CX700_101_000M 0x008B0803 945#define CX700_106_500M 0x00750802 946#define CX700_108_000M 0x00950803 947#define CX700_113_309M 0x005D0801 948#define CX700_118_840M 0x00A40803 949#define CX700_119_000M 0x00830802 950#define CX700_121_750M 0x00420800 /* 121.704MHz */ 951#define CX700_125_104M 0x00AD0803 952#define CX700_133_308M 0x00930802 953#define CX700_135_000M 0x00950802 954#define CX700_136_700M 0x00BD0803 955#define CX700_138_400M 0x00720801 956#define CX700_146_760M 0x00CC0803 957#define CX700_148_500M 0x00a40802 958#define CX700_153_920M 0x00540402 959#define CX700_156_000M 0x006B0403 960#define CX700_157_500M 0x006C0403 961#define CX700_162_000M 0x006F0403 962#define CX700_172_798M 0x00770403 963#define CX700_187_000M 0x00810403 964#define CX700_193_295M 0x00850403 965#define CX700_202_500M 0x008C0403 966#define CX700_204_000M 0x008D0403 967#define CX700_218_500M 0x00970403 968#define CX700_234_000M 0x00600401 969#define CX700_267_250M 0x00B90403 970#define CX700_297_500M 0x00CE0403 971#define CX700_122_614M 0x00870802 972 973/* PLL for VX855 */ 974#define VX855_22_000M 0x007B1005 975#define VX855_25_175M 0x008D1005 976#define VX855_26_719M 0x00961005 977#define VX855_26_880M 0x00961005 978#define VX855_27_000M 0x00971005 979#define VX855_29_581M 0x00A51005 980#define VX855_29_829M 0x00641003 981#define VX855_31_490M 0x00B01005 982#define VX855_31_500M 0x00B01005 983#define VX855_31_728M 0x008E1004 984#define VX855_32_668M 0x00921004 985#define VX855_36_000M 0x00A11004 986#define VX855_40_000M 0x00700C05 987#define VX855_41_291M 0x00730C05 988#define VX855_43_163M 0x00790C05 989#define VX855_45_250M 0x007F0C05 /* 45.46MHz */ 990#define VX855_46_000M 0x00670C04 991#define VX855_46_996M 0x00690C04 992#define VX855_48_000M 0x00860C05 993#define VX855_48_875M 0x00890C05 994#define VX855_49_500M 0x00530C03 995#define VX855_52_406M 0x00580C03 996#define VX855_52_977M 0x00940C05 997#define VX855_56_250M 0x009D0C05 998#define VX855_60_466M 0x00A90C05 999#define VX855_61_500M 0x00AC0C05 1000#define VX855_65_000M 0x006D0C03
1001#define VX855_65_178M 0x00B60C05 1002#define VX855_66_750M 0x00700C03 /*67.116MHz */ 1003#define VX855_67_295M 0x00BC0C05 1004#define VX855_68_179M 0x00BF0C05 1005#define VX855_68_369M 0x00BF0C05 1006#define VX855_69_924M 0x00C30C05 1007#define VX855_70_159M 0x00C30C05 1008#define VX855_72_000M 0x00A10C04 1009#define VX855_73_023M 0x00CC0C05 1010#define VX855_74_481M 0x00D10C05 1011#define VX855_78_750M 0x006E0805 1012#define VX855_79_466M 0x006F0805 1013#define VX855_80_136M 0x00700805 1014#define VX855_81_627M 0x00720805 1015#define VX855_83_375M 0x00750805 1016#define VX855_83_527M 0x00750805 1017#define VX855_83_950M 0x00750805 1018#define VX855_84_537M 0x00760805 1019#define VX855_84_750M 0x00760805 /* 84.537Mhz */ 1020#define VX855_85_500M 0x00760805 /* 85.909080 MHz*/ 1021#define VX855_85_860M 0x00760805 1022#define VX855_85_909M 0x00760805 1023#define VX855_88_750M 0x007C0805 1024#define VX855_89_489M 0x007D0805 1025#define VX855_94_500M 0x00840805 1026#define VX855_96_648M 0x00870805 1027#define VX855_97_750M 0x00890805 1028#define VX855_101_000M 0x008D0805 1029#define VX855_106_500M 0x00950805 1030#define VX855_108_000M 0x00970805 1031#define VX855_110_125M 0x00990805 1032#define VX855_112_000M 0x009D0805 1033#define VX855_113_309M 0x009F0805 1034#define VX855_115_000M 0x00A10805 1035#define VX855_118_840M 0x00A60805 1036#define VX855_119_000M 0x00A70805 1037#define VX855_121_750M 0x00AA0805 /* 121.704MHz */ 1038#define VX855_122_614M 0x00AC0805 1039#define VX855_126_266M 0x00B10805 1040#define VX855_130_250M 0x00B60805 /* 130.250 */ 1041#define VX855_135_000M 0x00BD0805 1042#define VX855_136_700M 0x00BF0805 1043#define VX855_137_750M 0x00C10805 1044#define VX855_138_400M 0x00C20805 1045#define VX855_144_300M 0x00CA0805 1046#define VX855_146_760M 0x00CE0805 1047#define VX855_148_500M 0x00D00805 1048#define VX855_153_920M 0x00540402 1049#define VX855_156_000M 0x006C0405 1050#define VX855_156_867M 0x006E0405 1051#define VX855_157_500M 0x006E0405 1052#define VX855_162_000M 0x00710405 1053#define VX855_172_798M 0x00790405 1054#define VX855_187_000M 0x00830405 1055#define VX855_193_295M 0x00870405 1056#define VX855_202_500M 0x008E0405 1057#define VX855_204_000M 0x008F0405 1058#define VX855_218_500M 0x00990405 1059#define VX855_229_500M 0x00A10405 1060#define VX855_234_000M 0x00A40405 1061#define VX855_267_250M 0x00BB0405 1062#define VX855_297_500M 0x00D00405 1063#define VX855_339_500M 0x00770005 1064#define VX855_340_772M 0x00770005 1065 1066 1067/* Definition CRTC Timing Index */ 1068#define H_TOTAL_INDEX 0 1069#define H_ADDR_INDEX 1 1070#define H_BLANK_START_INDEX 2 1071#define H_BLANK_END_INDEX 3 1072#define H_SYNC_START_INDEX 4 1073#define H_SYNC_END_INDEX 5 1074#define V_TOTAL_INDEX 6 1075#define V_ADDR_INDEX 7 1076#define V_BLANK_START_INDEX 8 1077#define V_BLANK_END_INDEX 9 1078#define V_SYNC_START_INDEX 10 1079#define V_SYNC_END_INDEX 11 1080#define H_TOTAL_SHADOW_INDEX 12 1081#define H_BLANK_END_SHADOW_INDEX 13 1082#define V_TOTAL_SHADOW_INDEX 14 1083#define V_ADDR_SHADOW_INDEX 15 1084#define V_BLANK_SATRT_SHADOW_INDEX 16 1085#define V_BLANK_END_SHADOW_INDEX 17 1086#define V_SYNC_SATRT_SHADOW_INDEX 18 1087#define V_SYNC_END_SHADOW_INDEX 19 1088 1089/* Definition Video Mode Pixel Clock (picoseconds) 1090*/ 1091#define RES_480X640_60HZ_PIXCLOCK 39722 1092#define RES_640X480_60HZ_PIXCLOCK 39722 1093#define RES_640X480_75HZ_PIXCLOCK 31747 1094#define RES_640X480_85HZ_PIXCLOCK 27777 1095#define RES_640X480_100HZ_PIXCLOCK 23168 1096#define RES_640X480_120HZ_PIXCLOCK 19081 1097#define RES_720X480_60HZ_PIXCLOCK 37020 1098#define RES_720X576_60HZ_PIXCLOCK 30611 1099#define RES_800X600_60HZ_PIXCLOCK 25000 1100#define RES_800X600_75HZ_PIXCLOCK 20203 1101#define RES_800X600_85HZ_PIXCLOCK 17777 1102#define RES_800X600_100HZ_PIXCLOCK 14667 1103#define RES_800X600_120HZ_PIXCLOCK 11912 1104#define RES_800X480_60HZ_PIXCLOCK 33805 1105#define RES_848X480_60HZ_PIXCLOCK 31756 1106#define RES_856X480_60HZ_PIXCLOCK 31518 1107#define RES_1024X512_60HZ_PIXCLOCK 24218 1108#define RES_1024X600_60HZ_PIXCLOCK 20460 1109#define RES_1024X768_60HZ_PIXCLOCK 15385 1110#define RES_1024X768_75HZ_PIXCLOCK 12699 1111#define RES_1024X768_85HZ_PIXCLOCK 10582 1112#define RES_1024X768_100HZ_PIXCLOCK 8825 1113#define RES_1152X864_75HZ_PIXCLOCK 9259 1114#define RES_1280X768_60HZ_PIXCLOCK 12480 1115#define RES_1280X800_60HZ_PIXCLOCK 11994 1116#define RES_1280X960_60HZ_PIXCLOCK 9259 1117#define RES_1280X1024_60HZ_PIXCLOCK 9260 1118#define RES_1280X1024_75HZ_PIXCLOCK 7408 1119#define RES_1280X768_85HZ_PIXCLOCK 6349 1120#define RES_1440X1050_60HZ_PIXCLOCK 7993 1121#define RES_1600X1200_60HZ_PIXCLOCK 6172 1122#define RES_1600X1200_75HZ_PIXCLOCK 4938 1123#define RES_1280X720_60HZ_PIXCLOCK 13426 1124#define RES_1920X1080_60HZ_PIXCLOCK 5787 1125#define RES_1400X1050_60HZ_PIXCLOCK 8214 1126#define RES_1400X1050_75HZ_PIXCLOCK 6410 1127#define RES_1368X768_60HZ_PIXCLOCK 11647 1128#define RES_960X600_60HZ_PIXCLOCK 22099 1129#define RES_1000X600_60HZ_PIXCLOCK 20834 1130#define RES_1024X576_60HZ_PIXCLOCK 21278 1131#define RES_1088X612_60HZ_PIXCLOCK 18877 1132#define RES_1152X720_60HZ_PIXCLOCK 14981 1133#define RES_1200X720_60HZ_PIXCLOCK 14253 1134#define RES_1280X600_60HZ_PIXCLOCK 16260 1135#define RES_1280X720_50HZ_PIXCLOCK 16538 1136#define RES_1280X768_50HZ_PIXCLOCK 15342 1137#define RES_1366X768_50HZ_PIXCLOCK 14301 1138#define RES_1366X768_60HZ_PIXCLOCK 11646 1139#define RES_1360X768_60HZ_PIXCLOCK 11799 1140#define RES_1440X900_60HZ_PIXCLOCK 9390 1141#define RES_1440X900_75HZ_PIXCLOCK 7315 1142#define RES_1600X900_60HZ_PIXCLOCK 8415 1143#define RES_1600X1024_60HZ_PIXCLOCK 7315 1144#define RES_1680X1050_60HZ_PIXCLOCK 6814 1145#define RES_1680X1050_75HZ_PIXCLOCK 5348 1146#define RES_1792X1344_60HZ_PIXCLOCK 4902 1147#define RES_1856X1392_60HZ_PIXCLOCK 4577 1148#define RES_1920X1200_60HZ_PIXCLOCK 5173 1149#define RES_1920X1440_60HZ_PIXCLOCK 4274 1150#define RES_1920X1440_75HZ_PIXCLOCK 3367 1151#define RES_2048X1536_60HZ_PIXCLOCK 3742 1152 1153#define RES_1360X768_RB_60HZ_PIXCLOCK 13889 1154#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901 1155#define RES_1440X900_RB_60HZ_PIXCLOCK 11268 1156#define RES_1600X900_RB_60HZ_PIXCLOCK 10230 1157#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403 1158#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225 1159#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497 1160 1161/* LCD display method 1162*/ 1163#define LCD_EXPANDSION 0x00 1164#define LCD_CENTERING 0x01 1165 1166/* LCD mode 1167*/ 1168#define LCD_OPENLDI 0x00 1169#define LCD_SPWG 0x01 1170 1171/* Define display timing 1172*/ 1173struct display_timing { 1174 u16 hor_total; 1175 u16 hor_addr; 1176 u16 hor_blank_start; 1177 u16 hor_blank_end; 1178 u16 hor_sync_start; 1179 u16 hor_sync_end; 1180 u16 ver_total; 1181 u16 ver_addr; 1182 u16 ver_blank_start; 1183 u16 ver_blank_end; 1184 u16 ver_sync_start; 1185 u16 ver_sync_end; 1186}; 1187 1188struct crt_mode_table { 1189 int refresh_rate; 1190 unsigned long clk; 1191 int h_sync_polarity; 1192 int v_sync_polarity; 1193 struct display_timing crtc; 1194}; 1195 1196struct io_reg { 1197 int port; 1198 u8 index; 1199 u8 mask; 1200 u8 value; 1201}; 1202 1203#endif /* __SHARE_H__ */ 1204