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27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30
31
32
33#include <linux/types.h>
34#include "drm.h"
35
36
37
38#define I915_NR_TEX_REGIONS 255
39
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload;
69 int last_enqueue;
70 int last_dispatch;
71 int ctxOwner;
72 int texAge;
73 int pf_enabled;
74 int pf_active;
75 int pf_current_page;
76 int perf_boxes;
77 int width, height;
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation;
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
107
108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
116
117
118 drm_handle_t unused_handle;
119 __u32 unused1, unused2, unused3;
120
121
122
123
124 __u32 front_bo_handle;
125 __u32 back_bo_handle;
126 __u32 unused_bo_handle;
127 __u32 depth_bo_handle;
128
129} drm_i915_sarea_t;
130
131
132#define planeA_x pipeA_x
133#define planeA_y pipeA_y
134#define planeA_w pipeA_w
135#define planeA_h pipeA_h
136#define planeB_x pipeB_x
137#define planeB_y pipeB_y
138#define planeB_w pipeB_w
139#define planeB_h pipeB_h
140
141
142
143#define I915_BOX_RING_EMPTY 0x1
144#define I915_BOX_FLIP 0x2
145#define I915_BOX_WAIT 0x4
146#define I915_BOX_TEXTURE_LOAD 0x8
147#define I915_BOX_LOST_CONTEXT 0x10
148
149
150
151
152#define DRM_I915_INIT 0x00
153#define DRM_I915_FLUSH 0x01
154#define DRM_I915_FLIP 0x02
155#define DRM_I915_BATCHBUFFER 0x03
156#define DRM_I915_IRQ_EMIT 0x04
157#define DRM_I915_IRQ_WAIT 0x05
158#define DRM_I915_GETPARAM 0x06
159#define DRM_I915_SETPARAM 0x07
160#define DRM_I915_ALLOC 0x08
161#define DRM_I915_FREE 0x09
162#define DRM_I915_INIT_HEAP 0x0a
163#define DRM_I915_CMDBUFFER 0x0b
164#define DRM_I915_DESTROY_HEAP 0x0c
165#define DRM_I915_SET_VBLANK_PIPE 0x0d
166#define DRM_I915_GET_VBLANK_PIPE 0x0e
167#define DRM_I915_VBLANK_SWAP 0x0f
168#define DRM_I915_HWS_ADDR 0x11
169#define DRM_I915_GEM_INIT 0x13
170#define DRM_I915_GEM_EXECBUFFER 0x14
171#define DRM_I915_GEM_PIN 0x15
172#define DRM_I915_GEM_UNPIN 0x16
173#define DRM_I915_GEM_BUSY 0x17
174#define DRM_I915_GEM_THROTTLE 0x18
175#define DRM_I915_GEM_ENTERVT 0x19
176#define DRM_I915_GEM_LEAVEVT 0x1a
177#define DRM_I915_GEM_CREATE 0x1b
178#define DRM_I915_GEM_PREAD 0x1c
179#define DRM_I915_GEM_PWRITE 0x1d
180#define DRM_I915_GEM_MMAP 0x1e
181#define DRM_I915_GEM_SET_DOMAIN 0x1f
182#define DRM_I915_GEM_SW_FINISH 0x20
183#define DRM_I915_GEM_SET_TILING 0x21
184#define DRM_I915_GEM_GET_TILING 0x22
185#define DRM_I915_GEM_GET_APERTURE 0x23
186#define DRM_I915_GEM_MMAP_GTT 0x24
187#define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
188#define DRM_I915_GEM_MADVISE 0x26
189
190#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
191#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
192#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
193#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
194#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
195#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
196#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
197#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
198#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
199#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
200#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
201#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
202#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
203#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
204#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
205#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
206#define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
207#define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
208#define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
209#define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
210#define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
211#define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
212#define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
213#define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
214#define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
215#define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
216#define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
217#define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
218#define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
219#define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
220#define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
221#define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
222#define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
223#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
224#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
225#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
226
227
228
229
230typedef struct drm_i915_batchbuffer {
231 int start;
232 int used;
233 int DR1;
234 int DR4;
235 int num_cliprects;
236 struct drm_clip_rect __user *cliprects;
237} drm_i915_batchbuffer_t;
238
239
240
241
242typedef struct _drm_i915_cmdbuffer {
243 char __user *buf;
244 int sz;
245 int DR1;
246 int DR4;
247 int num_cliprects;
248 struct drm_clip_rect __user *cliprects;
249} drm_i915_cmdbuffer_t;
250
251
252
253typedef struct drm_i915_irq_emit {
254 int __user *irq_seq;
255} drm_i915_irq_emit_t;
256
257typedef struct drm_i915_irq_wait {
258 int irq_seq;
259} drm_i915_irq_wait_t;
260
261
262
263#define I915_PARAM_IRQ_ACTIVE 1
264#define I915_PARAM_ALLOW_BATCHBUFFER 2
265#define I915_PARAM_LAST_DISPATCH 3
266#define I915_PARAM_CHIPSET_ID 4
267#define I915_PARAM_HAS_GEM 5
268#define I915_PARAM_NUM_FENCES_AVAIL 6
269
270typedef struct drm_i915_getparam {
271 int param;
272 int __user *value;
273} drm_i915_getparam_t;
274
275
276
277#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
278#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
279#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
280#define I915_SETPARAM_NUM_USED_FENCES 4
281
282typedef struct drm_i915_setparam {
283 int param;
284 int value;
285} drm_i915_setparam_t;
286
287
288
289#define I915_MEM_REGION_AGP 1
290
291typedef struct drm_i915_mem_alloc {
292 int region;
293 int alignment;
294 int size;
295 int __user *region_offset;
296} drm_i915_mem_alloc_t;
297
298typedef struct drm_i915_mem_free {
299 int region;
300 int region_offset;
301} drm_i915_mem_free_t;
302
303typedef struct drm_i915_mem_init_heap {
304 int region;
305 int size;
306 int start;
307} drm_i915_mem_init_heap_t;
308
309
310
311
312typedef struct drm_i915_mem_destroy_heap {
313 int region;
314} drm_i915_mem_destroy_heap_t;
315
316
317
318#define DRM_I915_VBLANK_PIPE_A 1
319#define DRM_I915_VBLANK_PIPE_B 2
320
321typedef struct drm_i915_vblank_pipe {
322 int pipe;
323} drm_i915_vblank_pipe_t;
324
325
326
327typedef struct drm_i915_vblank_swap {
328 drm_drawable_t drawable;
329 enum drm_vblank_seq_type seqtype;
330 unsigned int sequence;
331} drm_i915_vblank_swap_t;
332
333typedef struct drm_i915_hws_addr {
334 __u64 addr;
335} drm_i915_hws_addr_t;
336
337struct drm_i915_gem_init {
338
339
340
341
342 __u64 gtt_start;
343
344
345
346
347 __u64 gtt_end;
348};
349
350struct drm_i915_gem_create {
351
352
353
354
355
356 __u64 size;
357
358
359
360
361
362 __u32 handle;
363 __u32 pad;
364};
365
366struct drm_i915_gem_pread {
367
368 __u32 handle;
369 __u32 pad;
370
371 __u64 offset;
372
373 __u64 size;
374
375
376
377
378
379 __u64 data_ptr;
380};
381
382struct drm_i915_gem_pwrite {
383
384 __u32 handle;
385 __u32 pad;
386
387 __u64 offset;
388
389 __u64 size;
390
391
392
393
394
395 __u64 data_ptr;
396};
397
398struct drm_i915_gem_mmap {
399
400 __u32 handle;
401 __u32 pad;
402
403 __u64 offset;
404
405
406
407
408
409 __u64 size;
410
411
412
413
414
415 __u64 addr_ptr;
416};
417
418struct drm_i915_gem_mmap_gtt {
419
420 __u32 handle;
421 __u32 pad;
422
423
424
425
426
427 __u64 offset;
428};
429
430struct drm_i915_gem_set_domain {
431
432 __u32 handle;
433
434
435 __u32 read_domains;
436
437
438 __u32 write_domain;
439};
440
441struct drm_i915_gem_sw_finish {
442
443 __u32 handle;
444};
445
446struct drm_i915_gem_relocation_entry {
447
448
449
450
451
452
453
454
455 __u32 target_handle;
456
457
458
459
460
461 __u32 delta;
462
463
464 __u64 offset;
465
466
467
468
469
470
471
472
473
474 __u64 presumed_offset;
475
476
477
478
479 __u32 read_domains;
480
481
482
483
484
485
486
487
488 __u32 write_domain;
489};
490
491
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495
496
497
498
499#define I915_GEM_DOMAIN_CPU 0x00000001
500
501#define I915_GEM_DOMAIN_RENDER 0x00000002
502
503#define I915_GEM_DOMAIN_SAMPLER 0x00000004
504
505#define I915_GEM_DOMAIN_COMMAND 0x00000008
506
507#define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
508
509#define I915_GEM_DOMAIN_VERTEX 0x00000020
510
511#define I915_GEM_DOMAIN_GTT 0x00000040
512
513
514struct drm_i915_gem_exec_object {
515
516
517
518
519 __u32 handle;
520
521
522 __u32 relocation_count;
523
524
525
526
527 __u64 relocs_ptr;
528
529
530 __u64 alignment;
531
532
533
534
535
536 __u64 offset;
537};
538
539struct drm_i915_gem_execbuffer {
540
541
542
543
544
545
546
547
548
549
550 __u64 buffers_ptr;
551 __u32 buffer_count;
552
553
554 __u32 batch_start_offset;
555
556 __u32 batch_len;
557 __u32 DR1;
558 __u32 DR4;
559 __u32 num_cliprects;
560
561 __u64 cliprects_ptr;
562};
563
564struct drm_i915_gem_pin {
565
566 __u32 handle;
567 __u32 pad;
568
569
570 __u64 alignment;
571
572
573 __u64 offset;
574};
575
576struct drm_i915_gem_unpin {
577
578 __u32 handle;
579 __u32 pad;
580};
581
582struct drm_i915_gem_busy {
583
584 __u32 handle;
585
586
587 __u32 busy;
588};
589
590#define I915_TILING_NONE 0
591#define I915_TILING_X 1
592#define I915_TILING_Y 2
593
594#define I915_BIT_6_SWIZZLE_NONE 0
595#define I915_BIT_6_SWIZZLE_9 1
596#define I915_BIT_6_SWIZZLE_9_10 2
597#define I915_BIT_6_SWIZZLE_9_11 3
598#define I915_BIT_6_SWIZZLE_9_10_11 4
599
600#define I915_BIT_6_SWIZZLE_UNKNOWN 5
601
602#define I915_BIT_6_SWIZZLE_9_17 6
603#define I915_BIT_6_SWIZZLE_9_10_17 7
604
605struct drm_i915_gem_set_tiling {
606
607 __u32 handle;
608
609
610
611
612
613
614
615
616
617
618
619
620
621 __u32 tiling_mode;
622
623
624
625
626
627 __u32 stride;
628
629
630
631
632
633 __u32 swizzle_mode;
634};
635
636struct drm_i915_gem_get_tiling {
637
638 __u32 handle;
639
640
641
642
643
644 __u32 tiling_mode;
645
646
647
648
649
650 __u32 swizzle_mode;
651};
652
653struct drm_i915_gem_get_aperture {
654
655 __u64 aper_size;
656
657
658
659
660
661 __u64 aper_available_size;
662};
663
664struct drm_i915_get_pipe_from_crtc_id {
665
666 __u32 crtc_id;
667
668
669 __u32 pipe;
670};
671
672#define I915_MADV_WILLNEED 0
673#define I915_MADV_DONTNEED 1
674#define __I915_MADV_PURGED 2
675
676struct drm_i915_gem_madvise {
677
678 __u32 handle;
679
680
681
682
683 __u32 madv;
684
685
686 __u32 retained;
687};
688
689#endif
690