LXR linux/include/drm/via

   1/*
   2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
   3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the
  13 * next paragraph) shall be included in all copies or substantial portions
  14 * of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22 * DEALINGS IN THE SOFTWARE.
  23 */
  24#ifndef _VIA_DRM_H_
  25#define _VIA_DRM_H_
  26
  27#include <linux/types.h>
  28
  29/* WARNING: These defines must be the same as what the Xserver uses.
  30 * if you change them, you must change the defines in the Xserver.
  31 */
  32
  33#ifndef _VIA_DEFINES_
  34#define _VIA_DEFINES_
  35
  36#ifndef __KERNEL__
  37#include "via_drmclient.h"
  38#endif
  39
  40#define VIA_NR_SAREA_CLIPRECTS          8
  41#define VIA_NR_XVMC_PORTS               10
  42#define VIA_NR_XVMC_LOCKS               5
  43#define VIA_MAX_CACHELINE_SIZE          64
  44#define XVMCLOCKPTR(saPriv,lockNo)                                      \
  45        ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
  46                                      (VIA_MAX_CACHELINE_SIZE - 1)) &   \
  47                                     ~(VIA_MAX_CACHELINE_SIZE - 1)) +   \
  48                                    VIA_MAX_CACHELINE_SIZE*(lockNo)))
  49
  50/* Each region is a minimum of 64k, and there are at most 64 of them.
  51 */
  52#define VIA_NR_TEX_REGIONS 64
  53#define VIA_LOG_MIN_TEX_REGION_SIZE 16
  54#endif
  55
  56#define VIA_UPLOAD_TEX0IMAGE  0x1       /* handled clientside */
  57#define VIA_UPLOAD_TEX1IMAGE  0x2       /* handled clientside */
  58#define VIA_UPLOAD_CTX        0x4
  59#define VIA_UPLOAD_BUFFERS    0x8
  60#define VIA_UPLOAD_TEX0       0x10
  61#define VIA_UPLOAD_TEX1       0x20
  62#define VIA_UPLOAD_CLIPRECTS  0x40
  63#define VIA_UPLOAD_ALL        0xff
  64
  65/* VIA specific ioctls */
  66#define DRM_VIA_ALLOCMEM        0x00
  67#define DRM_VIA_FREEMEM         0x01
  68#define DRM_VIA_AGP_INIT        0x02
  69#define DRM_VIA_FB_INIT         0x03
  70#define DRM_VIA_MAP_INIT        0x04
  71#define DRM_VIA_DEC_FUTEX       0x05
  72#define NOT_USED
  73#define DRM_VIA_DMA_INIT        0x07
  74#define DRM_VIA_CMDBUFFER       0x08
  75#define DRM_VIA_FLUSH           0x09
  76#define DRM_VIA_PCICMD          0x0a
  77#define DRM_VIA_CMDBUF_SIZE     0x0b
  78#define NOT_USED
  79#define DRM_VIA_WAIT_IRQ        0x0d
  80#define DRM_VIA_DMA_BLIT        0x0e
  81#define DRM_VIA_BLIT_SYNC       0x0f
  82
  83#define DRM_IOCTL_VIA_ALLOCMEM    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
  84#define DRM_IOCTL_VIA_FREEMEM     DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
  85#define DRM_IOCTL_VIA_AGP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
  86#define DRM_IOCTL_VIA_FB_INIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
  87#define DRM_IOCTL_VIA_MAP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
  88#define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
  89#define DRM_IOCTL_VIA_DMA_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
  90#define DRM_IOCTL_VIA_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
  91#define DRM_IOCTL_VIA_FLUSH       DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
  92#define DRM_IOCTL_VIA_PCICMD      DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
  93#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
  94                                            drm_via_cmdbuf_size_t)
  95#define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
  96#define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
  97#define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
  98
  99/* Indices into buf.Setup where various bits of state are mirrored per
 100 * context and per buffer.  These can be fired at the card as a unit,
 101 * or in a piecewise fashion as required.
 102 */
 103
 104#define VIA_TEX_SETUP_SIZE 8
 105
 106/* Flags for clear ioctl
 107 */
 108#define VIA_FRONT   0x1
 109#define VIA_BACK    0x2
 110#define VIA_DEPTH   0x4
 111#define VIA_STENCIL 0x8
 112#define VIA_MEM_VIDEO   0       /* matches drm constant */
 113#define VIA_MEM_AGP     1       /* matches drm constant */
 114#define VIA_MEM_SYSTEM  2
 115#define VIA_MEM_MIXED   3
 116#define VIA_MEM_UNKNOWN 4
 117
 118typedef struct {
 119        __u32 offset;
 120        __u32 size;
 121} drm_via_agp_t;
 122
 123typedef struct {
 124        __u32 offset;
 125        __u32 size;
 126} drm_via_fb_t;
 127
 128typedef struct {
 129        __u32 context;
 130        __u32 type;
 131        __u32 size;
 132        unsigned long index;
 133        unsigned long offset;
 134} drm_via_mem_t;
 135
 136typedef struct _drm_via_init {
 137        enum {
 138                VIA_INIT_MAP = 0x01,
 139                VIA_CLEANUP_MAP = 0x02
 140        } func;
 141
 142        unsigned long sarea_priv_offset;
 143        unsigned long fb_offset;
 144        unsigned long mmio_offset;
 145        unsigned long agpAddr;
 146} drm_via_init_t;
 147
 148typedef struct _drm_via_futex {
 149        enum {
 150                VIA_FUTEX_WAIT = 0x00,
 151                VIA_FUTEX_WAKE = 0X01
 152        } func;
 153        __u32 ms;
 154        __u32 lock;
 155        __u32 val;
 156} drm_via_futex_t;
 157
 158typedef struct _drm_via_dma_init {
 159        enum {
 160                VIA_INIT_DMA = 0x01,
 161                VIA_CLEANUP_DMA = 0x02,
 162                VIA_DMA_INITIALIZED = 0x03
 163        } func;
 164
 165        unsigned long offset;
 166        unsigned long size;
 167        unsigned long reg_pause_addr;
 168} drm_via_dma_init_t;
 169
 170typedef struct _drm_via_cmdbuffer {
 171        char __user *buf;
 172        unsigned long size;
 173} drm_via_cmdbuffer_t;
 174
 175/* Warning: If you change the SAREA structure you must change the Xserver
 176 * structure as well */
 177
 178typedef struct _drm_via_tex_region {
 179        unsigned char next, prev;       /* indices to form a circular LRU  */
 180        unsigned char inUse;    /* owned by a client, or free? */
 181        int age;                /* tracked by clients to update local LRU's */
 182} drm_via_tex_region_t;
 183
 184typedef struct _drm_via_sarea {
 185        unsigned int dirty;
 186        unsigned int nbox;
 187        struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
 188        drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
 189        int texAge;             /* last time texture was uploaded */
 190        int ctxOwner;           /* last context to upload state */
 191        int vertexPrim;
 192
 193        /*
 194         * Below is for XvMC.
 195         * We want the lock integers alone on, and aligned to, a cache line.
 196         * Therefore this somewhat strange construct.
 197         */
 198
 199        char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
 200
 201        unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
 202        unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
 203        unsigned int XvMCCtxNoGrabbed;  /* Last context to hold decoder */
 204
 205        /* Used by the 3d driver only at this point, for pageflipping:
 206         */
 207        unsigned int pfCurrentOffset;
 208} drm_via_sarea_t;
 209
 210typedef struct _drm_via_cmdbuf_size {
 211        enum {
 212                VIA_CMDBUF_SPACE = 0x01,
 213                VIA_CMDBUF_LAG = 0x02
 214        } func;
 215        int wait;
 216        __u32 size;
 217} drm_via_cmdbuf_size_t;
 218
 219typedef enum {
 220        VIA_IRQ_ABSOLUTE = 0x0,
 221        VIA_IRQ_RELATIVE = 0x1,
 222        VIA_IRQ_SIGNAL = 0x10000000,
 223        VIA_IRQ_FORCE_SEQUENCE = 0x20000000
 224} via_irq_seq_type_t;
 225
 226#define VIA_IRQ_FLAGS_MASK 0xF0000000
 227
 228enum drm_via_irqs {
 229        drm_via_irq_hqv0 = 0,
 230        drm_via_irq_hqv1,
 231        drm_via_irq_dma0_dd,
 232        drm_via_irq_dma0_td,
 233        drm_via_irq_dma1_dd,
 234        drm_via_irq_dma1_td,
 235        drm_via_irq_num
 236};
 237
 238struct drm_via_wait_irq_request {
 239        unsigned irq;
 240        via_irq_seq_type_t type;
 241        __u32 sequence;
 242        __u32 signal;
 243};
 244
 245typedef union drm_via_irqwait {
 246        struct drm_via_wait_irq_request request;
 247        struct drm_wait_vblank_reply reply;
 248} drm_via_irqwait_t;
 249
 250typedef struct drm_via_blitsync {
 251        __u32 sync_handle;
 252        unsigned engine;
 253} drm_via_blitsync_t;
 254
 255/* - * Below,"flags" is currently unused but will be used for possible future
 256 * extensions like kernel space bounce buffers for bad alignments and
 257 * blit engine busy-wait polling for better latency in the absence of
 258 * interrupts.
 259 */
 260
 261typedef struct drm_via_dmablit {
 262        __u32 num_lines;
 263        __u32 line_length;
 264
 265        __u32 fb_addr;
 266        __u32 fb_stride;
 267
 268        unsigned char *mem_addr;
 269        __u32 mem_stride;
 270
 271        __u32 flags;
 272        int to_fb;
 273
 274        drm_via_blitsync_t sync;
 275} drm_via_dmablit_t;
 276
 277#endif                          /* _VIA_DRM_H_ */
 278