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10#ifndef __LINUX_MDIO_H__
11#define __LINUX_MDIO_H__
12
13#include <linux/mii.h>
14
15
16#define MDIO_MMD_PMAPMD 1
17
18#define MDIO_MMD_WIS 2
19#define MDIO_MMD_PCS 3
20#define MDIO_MMD_PHYXS 4
21#define MDIO_MMD_DTEXS 5
22#define MDIO_MMD_TC 6
23#define MDIO_MMD_AN 7
24#define MDIO_MMD_C22EXT 29
25#define MDIO_MMD_VEND1 30
26#define MDIO_MMD_VEND2 31
27
28
29#define MDIO_CTRL1 MII_BMCR
30#define MDIO_STAT1 MII_BMSR
31#define MDIO_DEVID1 MII_PHYSID1
32#define MDIO_DEVID2 MII_PHYSID2
33#define MDIO_SPEED 4
34#define MDIO_DEVS1 5
35#define MDIO_DEVS2 6
36#define MDIO_CTRL2 7
37#define MDIO_STAT2 8
38#define MDIO_PMA_TXDIS 9
39#define MDIO_PMA_RXDET 10
40#define MDIO_PMA_EXTABLE 11
41#define MDIO_PKGID1 14
42#define MDIO_PKGID2 15
43#define MDIO_AN_ADVERTISE 16
44#define MDIO_AN_LPA 19
45#define MDIO_PHYXS_LNSTAT 24
46
47
48#define MDIO_PMA_10GBT_SWAPPOL 130
49#define MDIO_PMA_10GBT_TXPWR 131
50#define MDIO_PMA_10GBT_SNR 133
51
52#define MDIO_PMA_10GBR_FECABLE 170
53#define MDIO_PCS_10GBX_STAT1 24
54#define MDIO_PCS_10GBRT_STAT1 32
55#define MDIO_PCS_10GBRT_STAT2 33
56#define MDIO_AN_10GBT_CTRL 32
57#define MDIO_AN_10GBT_STAT 33
58
59
60#define MDIO_PMA_LASI_RXCTRL 0x9000
61#define MDIO_PMA_LASI_TXCTRL 0x9001
62#define MDIO_PMA_LASI_CTRL 0x9002
63#define MDIO_PMA_LASI_RXSTAT 0x9003
64#define MDIO_PMA_LASI_TXSTAT 0x9004
65#define MDIO_PMA_LASI_STAT 0x9005
66
67
68
69#define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100)
70
71#define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c)
72#define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX
73#define MDIO_CTRL1_LPOWER BMCR_PDOWN
74#define MDIO_CTRL1_RESET BMCR_RESET
75#define MDIO_PMA_CTRL1_LOOPBACK 0x0001
76#define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000
77#define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100
78#define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK
79#define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK
80#define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART
81#define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE
82#define MDIO_AN_CTRL1_XNP 0x2000
83
84
85#define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00)
86
87#define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04)
88
89
90#define MDIO_STAT1_LPOWERABLE 0x0002
91#define MDIO_STAT1_LSTATUS BMSR_LSTATUS
92#define MDIO_STAT1_FAULT 0x0080
93#define MDIO_AN_STAT1_LPABLE 0x0001
94#define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE
95#define MDIO_AN_STAT1_RFAULT BMSR_RFAULT
96#define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE
97#define MDIO_AN_STAT1_PAGE 0x0040
98#define MDIO_AN_STAT1_XNP 0x0080
99
100
101#define MDIO_SPEED_10G 0x0001
102#define MDIO_PMA_SPEED_2B 0x0002
103#define MDIO_PMA_SPEED_10P 0x0004
104#define MDIO_PMA_SPEED_1000 0x0010
105#define MDIO_PMA_SPEED_100 0x0020
106#define MDIO_PMA_SPEED_10 0x0040
107#define MDIO_PCS_SPEED_10P2B 0x0002
108
109
110#define MDIO_DEVS_PRESENT(devad) (1 << (devad))
111#define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD)
112#define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS)
113#define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS)
114#define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS)
115#define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS)
116#define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC)
117#define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN)
118#define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT)
119
120
121#define MDIO_PMA_CTRL2_TYPE 0x000f
122#define MDIO_PMA_CTRL2_10GBCX4 0x0000
123#define MDIO_PMA_CTRL2_10GBEW 0x0001
124#define MDIO_PMA_CTRL2_10GBLW 0x0002
125#define MDIO_PMA_CTRL2_10GBSW 0x0003
126#define MDIO_PMA_CTRL2_10GBLX4 0x0004
127#define MDIO_PMA_CTRL2_10GBER 0x0005
128#define MDIO_PMA_CTRL2_10GBLR 0x0006
129#define MDIO_PMA_CTRL2_10GBSR 0x0007
130#define MDIO_PMA_CTRL2_10GBLRM 0x0008
131#define MDIO_PMA_CTRL2_10GBT 0x0009
132#define MDIO_PMA_CTRL2_10GBKX4 0x000a
133#define MDIO_PMA_CTRL2_10GBKR 0x000b
134#define MDIO_PMA_CTRL2_1000BT 0x000c
135#define MDIO_PMA_CTRL2_1000BKX 0x000d
136#define MDIO_PMA_CTRL2_100BTX 0x000e
137#define MDIO_PMA_CTRL2_10BT 0x000f
138#define MDIO_PCS_CTRL2_TYPE 0x0003
139#define MDIO_PCS_CTRL2_10GBR 0x0000
140#define MDIO_PCS_CTRL2_10GBX 0x0001
141#define MDIO_PCS_CTRL2_10GBW 0x0002
142#define MDIO_PCS_CTRL2_10GBT 0x0003
143
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145#define MDIO_STAT2_RXFAULT 0x0400
146#define MDIO_STAT2_TXFAULT 0x0800
147#define MDIO_STAT2_DEVPRST 0xc000
148#define MDIO_STAT2_DEVPRST_VAL 0x8000
149#define MDIO_PMA_STAT2_LBABLE 0x0001
150#define MDIO_PMA_STAT2_10GBEW 0x0002
151#define MDIO_PMA_STAT2_10GBLW 0x0004
152#define MDIO_PMA_STAT2_10GBSW 0x0008
153#define MDIO_PMA_STAT2_10GBLX4 0x0010
154#define MDIO_PMA_STAT2_10GBER 0x0020
155#define MDIO_PMA_STAT2_10GBLR 0x0040
156#define MDIO_PMA_STAT2_10GBSR 0x0080
157#define MDIO_PMD_STAT2_TXDISAB 0x0100
158#define MDIO_PMA_STAT2_EXTABLE 0x0200
159#define MDIO_PMA_STAT2_RXFLTABLE 0x1000
160#define MDIO_PMA_STAT2_TXFLTABLE 0x2000
161#define MDIO_PCS_STAT2_10GBR 0x0001
162#define MDIO_PCS_STAT2_10GBX 0x0002
163#define MDIO_PCS_STAT2_10GBW 0x0004
164#define MDIO_PCS_STAT2_RXFLTABLE 0x1000
165#define MDIO_PCS_STAT2_TXFLTABLE 0x2000
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167
168#define MDIO_PMD_TXDIS_GLOBAL 0x0001
169#define MDIO_PMD_TXDIS_0 0x0002
170#define MDIO_PMD_TXDIS_1 0x0004
171#define MDIO_PMD_TXDIS_2 0x0008
172#define MDIO_PMD_TXDIS_3 0x0010
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175#define MDIO_PMD_RXDET_GLOBAL 0x0001
176#define MDIO_PMD_RXDET_0 0x0002
177#define MDIO_PMD_RXDET_1 0x0004
178#define MDIO_PMD_RXDET_2 0x0008
179#define MDIO_PMD_RXDET_3 0x0010
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181
182#define MDIO_PMA_EXTABLE_10GCX4 0x0001
183#define MDIO_PMA_EXTABLE_10GBLRM 0x0002
184#define MDIO_PMA_EXTABLE_10GBT 0x0004
185#define MDIO_PMA_EXTABLE_10GBKX4 0x0008
186#define MDIO_PMA_EXTABLE_10GBKR 0x0010
187#define MDIO_PMA_EXTABLE_1000BT 0x0020
188#define MDIO_PMA_EXTABLE_1000BKX 0x0040
189#define MDIO_PMA_EXTABLE_100BTX 0x0080
190#define MDIO_PMA_EXTABLE_10BT 0x0100
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192
193#define MDIO_PHYXS_LNSTAT_SYNC0 0x0001
194#define MDIO_PHYXS_LNSTAT_SYNC1 0x0002
195#define MDIO_PHYXS_LNSTAT_SYNC2 0x0004
196#define MDIO_PHYXS_LNSTAT_SYNC3 0x0008
197#define MDIO_PHYXS_LNSTAT_ALIGN 0x1000
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199
200#define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001
201#define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002
202#define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100
203#define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200
204#define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400
205#define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800
206
207
208#define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001
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211
212#define MDIO_PMA_10GBT_SNR_BIAS 0x8000
213#define MDIO_PMA_10GBT_SNR_MAX 127
214
215
216#define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001
217#define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002
218
219
220#define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001
221
222
223#define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff
224#define MDIO_PCS_10GBRT_STAT2_BER 0x3f00
225
226
227#define MDIO_AN_10GBT_CTRL_ADV10G 0x1000
228
229
230#define MDIO_AN_10GBT_STAT_LPTRR 0x0200
231#define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400
232#define MDIO_AN_10GBT_STAT_LP10G 0x0800
233#define MDIO_AN_10GBT_STAT_REMOK 0x1000
234#define MDIO_AN_10GBT_STAT_LOCOK 0x2000
235#define MDIO_AN_10GBT_STAT_MS 0x4000
236#define MDIO_AN_10GBT_STAT_MSFLT 0x8000
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239#define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001
240#define MDIO_PMA_LASI_RX_PCSLFLT 0x0008
241#define MDIO_PMA_LASI_RX_PMALFLT 0x0010
242#define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020
243#define MDIO_PMA_LASI_RX_WISLFLT 0x0200
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246#define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001
247#define MDIO_PMA_LASI_TX_PCSLFLT 0x0008
248#define MDIO_PMA_LASI_TX_PMALFLT 0x0010
249#define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080
250#define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100
251#define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200
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254#define MDIO_PMA_LASI_LSALARM 0x0001
255#define MDIO_PMA_LASI_TXALARM 0x0002
256#define MDIO_PMA_LASI_RXALARM 0x0004
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260#define MDIO_PHY_ID_C45 0x8000
261#define MDIO_PHY_ID_PRTAD 0x03e0
262#define MDIO_PHY_ID_DEVAD 0x001f
263#define MDIO_PHY_ID_C45_MASK \
264 (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD)
265
266static inline __u16 mdio_phy_id_c45(int prtad, int devad)
267{
268 return MDIO_PHY_ID_C45 | (prtad << 5) | devad;
269}
270
271static inline bool mdio_phy_id_is_c45(int phy_id)
272{
273 return (phy_id & MDIO_PHY_ID_C45) && !(phy_id & ~MDIO_PHY_ID_C45_MASK);
274}
275
276static inline __u16 mdio_phy_id_prtad(int phy_id)
277{
278 return (phy_id & MDIO_PHY_ID_PRTAD) >> 5;
279}
280
281static inline __u16 mdio_phy_id_devad(int phy_id)
282{
283 return phy_id & MDIO_PHY_ID_DEVAD;
284}
285
286#define MDIO_SUPPORTS_C22 1
287#define MDIO_SUPPORTS_C45 2
288
289#ifdef __KERNEL__
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305struct mdio_if_info {
306 int prtad;
307 u32 mmds;
308 unsigned mode_support;
309
310 struct net_device *dev;
311 int (*mdio_read)(struct net_device *dev, int prtad, int devad,
312 u16 addr);
313 int (*mdio_write)(struct net_device *dev, int prtad, int devad,
314 u16 addr, u16 val);
315};
316
317#define MDIO_PRTAD_NONE (-1)
318#define MDIO_DEVAD_NONE (-1)
319#define MDIO_EMULATE_C22 4
320
321struct ethtool_cmd;
322struct ethtool_pauseparam;
323extern int mdio45_probe(struct mdio_if_info *mdio, int prtad);
324extern int mdio_set_flag(const struct mdio_if_info *mdio,
325 int prtad, int devad, u16 addr, int mask,
326 bool sense);
327extern int mdio45_links_ok(const struct mdio_if_info *mdio, u32 mmds);
328extern int mdio45_nway_restart(const struct mdio_if_info *mdio);
329extern void mdio45_ethtool_gset_npage(const struct mdio_if_info *mdio,
330 struct ethtool_cmd *ecmd,
331 u32 npage_adv, u32 npage_lpa);
332extern void
333mdio45_ethtool_spauseparam_an(const struct mdio_if_info *mdio,
334 const struct ethtool_pauseparam *ecmd);
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346static inline void mdio45_ethtool_gset(const struct mdio_if_info *mdio,
347 struct ethtool_cmd *ecmd)
348{
349 mdio45_ethtool_gset_npage(mdio, ecmd, 0, 0);
350}
351
352extern int mdio_mii_ioctl(const struct mdio_if_info *mdio,
353 struct mii_ioctl_data *mii_data, int cmd);
354
355#endif
356#endif
357