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33#ifndef MLX4_QP_H
34#define MLX4_QP_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39
40#define MLX4_INVALID_LKEY 0x100
41
42enum mlx4_qp_optpar {
43 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
44 MLX4_QP_OPTPAR_RRE = 1 << 1,
45 MLX4_QP_OPTPAR_RAE = 1 << 2,
46 MLX4_QP_OPTPAR_RWE = 1 << 3,
47 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
48 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
49 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
50 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
51 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
52 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
53 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
54 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
55 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
56 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
57 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16
58};
59
60enum mlx4_qp_state {
61 MLX4_QP_STATE_RST = 0,
62 MLX4_QP_STATE_INIT = 1,
63 MLX4_QP_STATE_RTR = 2,
64 MLX4_QP_STATE_RTS = 3,
65 MLX4_QP_STATE_SQER = 4,
66 MLX4_QP_STATE_SQD = 5,
67 MLX4_QP_STATE_ERR = 6,
68 MLX4_QP_STATE_SQ_DRAINING = 7,
69 MLX4_QP_NUM_STATE
70};
71
72enum {
73 MLX4_QP_ST_RC = 0x0,
74 MLX4_QP_ST_UC = 0x1,
75 MLX4_QP_ST_RD = 0x2,
76 MLX4_QP_ST_UD = 0x3,
77 MLX4_QP_ST_MLX = 0x7
78};
79
80enum {
81 MLX4_QP_PM_MIGRATED = 0x3,
82 MLX4_QP_PM_ARMED = 0x0,
83 MLX4_QP_PM_REARM = 0x1
84};
85
86enum {
87
88 MLX4_QP_BIT_SRE = 1 << 15,
89 MLX4_QP_BIT_SWE = 1 << 14,
90 MLX4_QP_BIT_SAE = 1 << 13,
91
92 MLX4_QP_BIT_RRE = 1 << 15,
93 MLX4_QP_BIT_RWE = 1 << 14,
94 MLX4_QP_BIT_RAE = 1 << 13,
95 MLX4_QP_BIT_RIC = 1 << 4,
96};
97
98struct mlx4_qp_path {
99 u8 fl;
100 u8 reserved1[2];
101 u8 pkey_index;
102 u8 reserved2;
103 u8 grh_mylmc;
104 __be16 rlid;
105 u8 ackto;
106 u8 mgid_index;
107 u8 static_rate;
108 u8 hop_limit;
109 __be32 tclass_flowlabel;
110 u8 rgid[16];
111 u8 sched_queue;
112 u8 snooper_flags;
113 u8 reserved3[2];
114 u8 counter_index;
115 u8 reserved4[7];
116};
117
118struct mlx4_qp_context {
119 __be32 flags;
120 __be32 pd;
121 u8 mtu_msgmax;
122 u8 rq_size_stride;
123 u8 sq_size_stride;
124 u8 rlkey;
125 __be32 usr_page;
126 __be32 local_qpn;
127 __be32 remote_qpn;
128 struct mlx4_qp_path pri_path;
129 struct mlx4_qp_path alt_path;
130 __be32 params1;
131 u32 reserved1;
132 __be32 next_send_psn;
133 __be32 cqn_send;
134 u32 reserved2[2];
135 __be32 last_acked_psn;
136 __be32 ssn;
137 __be32 params2;
138 __be32 rnr_nextrecvpsn;
139 __be32 srcd;
140 __be32 cqn_recv;
141 __be64 db_rec_addr;
142 __be32 qkey;
143 __be32 srqn;
144 __be32 msn;
145 __be16 rq_wqe_counter;
146 __be16 sq_wqe_counter;
147 u32 reserved3[2];
148 __be32 param3;
149 __be32 nummmcpeers_basemkey;
150 u8 log_page_size;
151 u8 reserved4[2];
152 u8 mtt_base_addr_h;
153 __be32 mtt_base_addr_l;
154 u32 reserved5[10];
155};
156
157
158#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
159
160enum {
161 MLX4_WQE_CTRL_NEC = 1 << 29,
162 MLX4_WQE_CTRL_FENCE = 1 << 6,
163 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
164 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
165 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
166 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
167 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
168 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
169};
170
171struct mlx4_wqe_ctrl_seg {
172 __be32 owner_opcode;
173 __be16 vlan_tag;
174 u8 ins_vlan;
175 u8 fence_size;
176
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182
183
184 __be32 srcrb_flags;
185
186
187
188
189
190 __be32 imm;
191};
192
193enum {
194 MLX4_WQE_MLX_VL15 = 1 << 17,
195 MLX4_WQE_MLX_SLR = 1 << 16
196};
197
198struct mlx4_wqe_mlx_seg {
199 u8 owner;
200 u8 reserved1[2];
201 u8 opcode;
202 u8 reserved2[3];
203 u8 size;
204
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211
212
213 __be32 flags;
214 __be16 rlid;
215 u16 reserved3;
216};
217
218struct mlx4_wqe_datagram_seg {
219 __be32 av[8];
220 __be32 dqpn;
221 __be32 qkey;
222 __be32 reservd[2];
223};
224
225struct mlx4_wqe_lso_seg {
226 __be32 mss_hdr_size;
227 __be32 header[0];
228};
229
230struct mlx4_wqe_bind_seg {
231 __be32 flags1;
232 __be32 flags2;
233 __be32 new_rkey;
234 __be32 lkey;
235 __be64 addr;
236 __be64 length;
237};
238
239enum {
240 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
241 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
242 MLX4_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
243 MLX4_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
244 MLX4_WQE_FMR_PERM_ATOMIC = 1 << 31
245};
246
247struct mlx4_wqe_fmr_seg {
248 __be32 flags;
249 __be32 mem_key;
250 __be64 buf_list;
251 __be64 start_addr;
252 __be64 reg_len;
253 __be32 offset;
254 __be32 page_size;
255 u32 reserved[2];
256};
257
258struct mlx4_wqe_fmr_ext_seg {
259 u8 flags;
260 u8 reserved;
261 __be16 app_mask;
262 __be16 wire_app_tag;
263 __be16 mem_app_tag;
264 __be32 wire_ref_tag_base;
265 __be32 mem_ref_tag_base;
266};
267
268struct mlx4_wqe_local_inval_seg {
269 __be32 flags;
270 u32 reserved1;
271 __be32 mem_key;
272 u32 reserved2[2];
273 __be32 guest_id;
274 __be64 pa;
275};
276
277struct mlx4_wqe_raddr_seg {
278 __be64 raddr;
279 __be32 rkey;
280 u32 reserved;
281};
282
283struct mlx4_wqe_atomic_seg {
284 __be64 swap_add;
285 __be64 compare;
286};
287
288struct mlx4_wqe_data_seg {
289 __be32 byte_count;
290 __be32 lkey;
291 __be64 addr;
292};
293
294enum {
295 MLX4_INLINE_ALIGN = 64,
296};
297
298struct mlx4_wqe_inline_seg {
299 __be32 byte_count;
300};
301
302int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
303 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
304 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
305 int sqd_event, struct mlx4_qp *qp);
306
307int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
308 struct mlx4_qp_context *context);
309
310int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
311 struct mlx4_qp_context *context,
312 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
313
314static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
315{
316 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
317}
318
319void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
320
321#endif
322
