1/* 2 * linux/include/linux/mtd/nand.h 3 * 4 * Copyright (c) 2000 David Woodhouse <dwmw2@infradead.org> 5 * Steven J. Hill <sjhill@realitydiluted.com> 6 * Thomas Gleixner <tglx@linutronix.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * Info: 13 * Contains standard defines and IDs for NAND flash devices 14 * 15 * Changelog: 16 * See git changelog. 17 */ 18#ifndef __LINUX_MTD_NAND_H 19#define __LINUX_MTD_NAND_H 20 21#include <linux/wait.h> 22#include <linux/spinlock.h> 23#include <linux/mtd/mtd.h> 24 25struct mtd_info; 26/* Scan and identify a NAND device */ 27extern int nand_scan (struct mtd_info *mtd, int max_chips); 28/* Separate phases of nand_scan(), allowing board driver to intervene 29 * and override command or ECC setup according to flash type */ 30extern int nand_scan_ident(struct mtd_info *mtd, int max_chips); 31extern int nand_scan_tail(struct mtd_info *mtd); 32 33/* Free resources held by the NAND device */ 34extern void nand_release (struct mtd_info *mtd); 35 36/* Internal helper for board drivers which need to override command function */ 37extern void nand_wait_ready(struct mtd_info *mtd); 38 39/* The maximum number of NAND chips in an array */ 40#define NAND_MAX_CHIPS 8 41 42/* This constant declares the max. oobsize / page, which 43 * is supported now. If you add a chip with bigger oobsize/page 44 * adjust this accordingly. 45 */ 46#define NAND_MAX_OOBSIZE 128 47#define NAND_MAX_PAGESIZE 4096 48 49/* 50 * Constants for hardware specific CLE/ALE/NCE function 51 * 52 * These are bits which can be or'ed to set/clear multiple 53 * bits in one go. 54 */ 55/* Select the chip by setting nCE to low */ 56#define NAND_NCE 0x01 57/* Select the command latch by setting CLE to high */ 58#define NAND_CLE 0x02 59/* Select the address latch by setting ALE to high */ 60#define NAND_ALE 0x04 61 62#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 63#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 64#define NAND_CTRL_CHANGE 0x80 65 66/* 67 * Standard NAND flash commands 68 */ 69#define NAND_CMD_READ0 0 70#define NAND_CMD_READ1 1 71#define NAND_CMD_RNDOUT 5 72#define NAND_CMD_PAGEPROG 0x10 73#define NAND_CMD_READOOB 0x50 74#define NAND_CMD_ERASE1 0x60 75#define NAND_CMD_STATUS 0x70 76#define NAND_CMD_STATUS_MULTI 0x71 77#define NAND_CMD_SEQIN 0x80 78#define NAND_CMD_RNDIN 0x85 79#define NAND_CMD_READID 0x90 80#define NAND_CMD_ERASE2 0xd0 81#define NAND_CMD_RESET 0xff 82 83/* Extended commands for large page devices */ 84#define NAND_CMD_READSTART 0x30 85#define NAND_CMD_RNDOUTSTART 0xE0 86#define NAND_CMD_CACHEDPROG 0x15 87 88/* Extended commands for AG-AND device */ 89/* 90 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but 91 * there is no way to distinguish that from NAND_CMD_READ0 92 * until the remaining sequence of commands has been completed 93 * so add a high order bit and mask it off in the command. 94 */ 95#define NAND_CMD_DEPLETE1 0x100 96#define NAND_CMD_DEPLETE2 0x38 97#define NAND_CMD_STATUS_MULTI 0x71 98#define NAND_CMD_STATUS_ERROR 0x72 99/* multi-bank error status (banks 0-3) */ 100#define NAND_CMD_STATUS_ERROR0 0x73 101#define NAND_CMD_STATUS_ERROR1 0x74 102#define NAND_CMD_STATUS_ERROR2 0x75 103#define NAND_CMD_STATUS_ERROR3 0x76 104#define NAND_CMD_STATUS_RESET 0x7f 105#define NAND_CMD_STATUS_CLEAR 0xff 106 107#define NAND_CMD_NONE -1 108 109/* Status bits */ 110#define NAND_STATUS_FAIL 0x01 111#define NAND_STATUS_FAIL_N1 0x02 112#define NAND_STATUS_TRUE_READY 0x20 113#define NAND_STATUS_READY 0x40 114#define NAND_STATUS_WP 0x80 115 116/* 117 * Constants for ECC_MODES 118 */ 119typedef enum { 120 NAND_ECC_NONE, 121 NAND_ECC_SOFT, 122 NAND_ECC_HW, 123 NAND_ECC_HW_SYNDROME, 124 NAND_ECC_HW_OOB_FIRST, 125} nand_ecc_modes_t; 126 127/* 128 * Constants for Hardware ECC 129 */ 130/* Reset Hardware ECC for read */ 131#define NAND_ECC_READ 0 132/* Reset Hardware ECC for write */ 133#define NAND_ECC_WRITE 1 134/* Enable Hardware ECC before syndrom is read back from flash */ 135#define NAND_ECC_READSYN 2 136 137/* Bit mask for flags passed to do_nand_read_ecc */ 138#define NAND_GET_DEVICE 0x80 139 140 141/* Option constants for bizarre disfunctionality and real 142* features 143*/ 144/* Chip can not auto increment pages */ 145#define NAND_NO_AUTOINCR 0x00000001 146/* Buswitdh is 16 bit */ 147#define NAND_BUSWIDTH_16 0x00000002 148/* Device supports partial programming without padding */ 149#define NAND_NO_PADDING 0x00000004 150/* Chip has cache program function */ 151#define NAND_CACHEPRG 0x00000008 152/* Chip has copy back function */ 153#define NAND_COPYBACK 0x00000010 154/* AND Chip which has 4 banks and a confusing page / block 155 * assignment. See Renesas datasheet for further information */ 156#define NAND_IS_AND 0x00000020 157/* Chip has a array of 4 pages which can be read without 158 * additional ready /busy waits */ 159#define NAND_4PAGE_ARRAY 0x00000040 160/* Chip requires that BBT is periodically rewritten to prevent 161 * bits from adjacent blocks from 'leaking' in altering data. 162 * This happens with the Renesas AG-AND chips, possibly others. */ 163#define BBT_AUTO_REFRESH 0x00000080 164/* Chip does not require ready check on read. True 165 * for all large page devices, as they do not support 166 * autoincrement.*/ 167#define NAND_NO_READRDY 0x00000100 168/* Chip does not allow subpage writes */ 169#define NAND_NO_SUBPAGE_WRITE 0x00000200 170 171 172/* Options valid for Samsung large page devices */ 173#define NAND_SAMSUNG_LP_OPTIONS \ 174 (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK) 175 176/* Macros to identify the above */ 177#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR)) 178#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING)) 179#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG)) 180#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK)) 181/* Large page NAND with SOFT_ECC should support subpage reads */ 182#define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \ 183 && (chip->page_shift > 9)) 184 185/* Mask to zero out the chip options, which come from the id table */ 186#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR) 187 188/* Non chip related options */ 189/* Use a flash based bad block table. This option is passed to the 190 * default bad block table function. */ 191#define NAND_USE_FLASH_BBT 0x00010000 192/* This option skips the bbt scan during initialization. */ 193#define NAND_SKIP_BBTSCAN 0x00020000 194/* This option is defined if the board driver allocates its own buffers 195 (e.g. because it needs them DMA-coherent */ 196#define NAND_OWN_BUFFERS 0x00040000 197/* Options set by nand scan */ 198/* Nand scan has allocated controller struct */ 199#define NAND_CONTROLLER_ALLOC 0x80000000 200 201/* Cell info constants */ 202#define NAND_CI_CHIPNR_MSK 0x03 203#define NAND_CI_CELLTYPE_MSK 0x0C 204 205/* 206 * nand_state_t - chip states 207 * Enumeration for NAND flash chip state 208 */ 209typedef enum { 210 FL_READY, 211 FL_READING, 212 FL_WRITING, 213 FL_ERASING, 214 FL_SYNCING, 215 FL_CACHEDPRG, 216 FL_PM_SUSPENDED, 217} nand_state_t; 218 219/* Keep gcc happy */ 220struct nand_chip; 221 222/** 223 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices 224 * @lock: protection lock 225 * @active: the mtd device which holds the controller currently 226 * @wq: wait queue to sleep on if a NAND operation is in progress 227 * used instead of the per chip wait queue when a hw controller is available 228 */ 229struct nand_hw_control { 230 spinlock_t lock; 231 struct nand_chip *active; 232 wait_queue_head_t wq; 233}; 234 235/** 236 * struct nand_ecc_ctrl - Control structure for ecc 237 * @mode: ecc mode 238 * @steps: number of ecc steps per page 239 * @size: data bytes per ecc step 240 * @bytes: ecc bytes per step 241 * @total: total number of ecc bytes per page 242 * @prepad: padding information for syndrome based ecc generators 243 * @postpad: padding information for syndrome based ecc generators 244 * @layout: ECC layout control struct pointer 245 * @hwctl: function to control hardware ecc generator. Must only 246 * be provided if an hardware ECC is available 247 * @calculate: function for ecc calculation or readback from ecc hardware 248 * @correct: function for ecc correction, matching to ecc generator (sw/hw) 249 * @read_page_raw: function to read a raw page without ECC 250 * @write_page_raw: function to write a raw page without ECC 251 * @read_page: function to read a page according to the ecc generator requirements 252 * @read_subpage: function to read parts of the page covered by ECC. 253 * @write_page: function to write a page according to the ecc generator requirements 254 * @read_oob: function to read chip OOB data 255 * @write_oob: function to write chip OOB data 256 */ 257struct nand_ecc_ctrl { 258 nand_ecc_modes_t mode; 259 int steps; 260 int size; 261 int bytes; 262 int total; 263 int prepad; 264 int postpad; 265 struct nand_ecclayout *layout; 266 void (*hwctl)(struct mtd_info *mtd, int mode); 267 int (*calculate)(struct mtd_info *mtd, 268 const uint8_t *dat, 269 uint8_t *ecc_code); 270 int (*correct)(struct mtd_info *mtd, uint8_t *dat, 271 uint8_t *read_ecc, 272 uint8_t *calc_ecc); 273 int (*read_page_raw)(struct mtd_info *mtd, 274 struct nand_chip *chip, 275 uint8_t *buf, int page); 276 void (*write_page_raw)(struct mtd_info *mtd, 277 struct nand_chip *chip, 278 const uint8_t *buf); 279 int (*read_page)(struct mtd_info *mtd, 280 struct nand_chip *chip, 281 uint8_t *buf, int page); 282 int (*read_subpage)(struct mtd_info *mtd, 283 struct nand_chip *chip, 284 uint32_t offs, uint32_t len, 285 uint8_t *buf); 286 void (*write_page)(struct mtd_info *mtd, 287 struct nand_chip *chip, 288 const uint8_t *buf); 289 int (*read_oob)(struct mtd_info *mtd, 290 struct nand_chip *chip, 291 int page, 292 int sndcmd); 293 int (*write_oob)(struct mtd_info *mtd, 294 struct nand_chip *chip, 295 int page); 296}; 297 298/** 299 * struct nand_buffers - buffer structure for read/write 300 * @ecccalc: buffer for calculated ecc 301 * @ecccode: buffer for ecc read from flash 302 * @databuf: buffer for data - dynamically sized 303 * 304 * Do not change the order of buffers. databuf and oobrbuf must be in 305 * consecutive order. 306 */ 307struct nand_buffers { 308 uint8_t ecccalc[NAND_MAX_OOBSIZE]; 309 uint8_t ecccode[NAND_MAX_OOBSIZE]; 310 uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; 311}; 312 313/** 314 * struct nand_chip - NAND Private Flash Chip Data 315 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device 316 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device 317 * @read_byte: [REPLACEABLE] read one byte from the chip 318 * @read_word: [REPLACEABLE] read one word from the chip 319 * @write_buf: [REPLACEABLE] write data from the buffer to the chip 320 * @read_buf: [REPLACEABLE] read data from the chip into the buffer 321 * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data 322 * @select_chip: [REPLACEABLE] select chip nr 323 * @block_bad: [REPLACEABLE] check, if the block is bad 324 * @block_markbad: [REPLACEABLE] mark the block bad 325 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling 326 * ALE/CLE/nCE. Also used to write command and address 327 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line 328 * If set to NULL no access to ready/busy is available and the ready/busy information 329 * is read from the chip status register 330 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip 331 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready 332 * @ecc: [BOARDSPECIFIC] ecc control ctructure 333 * @buffers: buffer structure for read/write 334 * @hwcontrol: platform-specific hardware control structure 335 * @ops: oob operation operands 336 * @erase_cmd: [INTERN] erase command write function, selectable due to AND support 337 * @scan_bbt: [REPLACEABLE] function to scan bad block table 338 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 339 * @state: [INTERN] the current state of the NAND device 340 * @oob_poi: poison value buffer 341 * @page_shift: [INTERN] number of address bits in a page (column address bits) 342 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 343 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 344 * @chip_shift: [INTERN] number of address bits in one chip 345 * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about 346 * special functionality. See the defines for further explanation 347 * @badblockpos: [INTERN] position of the bad block marker in the oob area 348 * @cellinfo: [INTERN] MLC/multichip data from chip ident 349 * @numchips: [INTERN] number of physical chips 350 * @chipsize: [INTERN] the size of one chip for multichip arrays 351 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 352 * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf 353 * @subpagesize: [INTERN] holds the subpagesize 354 * @ecclayout: [REPLACEABLE] the default ecc placement scheme 355 * @bbt: [INTERN] bad block table pointer 356 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 357 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 358 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 359 * @controller: [REPLACEABLE] a pointer to a hardware controller structure 360 * which is shared among multiple independend devices 361 * @priv: [OPTIONAL] pointer to private chip date 362 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 363 * (determine if errors are correctable) 364 * @write_page: [REPLACEABLE] High-level page write function 365 */ 366 367struct nand_chip { 368 void __iomem *IO_ADDR_R; 369 void __iomem *IO_ADDR_W; 370 371 uint8_t (*read_byte)(struct mtd_info *mtd); 372 u16 (*read_word)(struct mtd_info *mtd); 373 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 374 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); 375 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); 376 void (*select_chip)(struct mtd_info *mtd, int chip); 377 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip); 378 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs); 379 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 380 unsigned int ctrl); 381 int (*dev_ready)(struct mtd_info *mtd); 382 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr); 383 int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this); 384 void (*erase_cmd)(struct mtd_info *mtd, int page); 385 int (*scan_bbt)(struct mtd_info *mtd); 386 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page); 387 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip, 388 const uint8_t *buf, int page, int cached, int raw); 389 390 int chip_delay; 391 unsigned int options; 392 393 int page_shift; 394 int phys_erase_shift; 395 int bbt_erase_shift; 396 int chip_shift; 397 int numchips; 398 uint64_t chipsize; 399 int pagemask; 400 int pagebuf; 401 int subpagesize; 402 uint8_t cellinfo; 403 int badblockpos; 404 405 nand_state_t state; 406 407 uint8_t *oob_poi; 408 struct nand_hw_control *controller; 409 struct nand_ecclayout *ecclayout; 410 411 struct nand_ecc_ctrl ecc; 412 struct nand_buffers *buffers; 413 struct nand_hw_control hwcontrol; 414 415 struct mtd_oob_ops ops; 416 417 uint8_t *bbt; 418 struct nand_bbt_descr *bbt_td; 419 struct nand_bbt_descr *bbt_md; 420 421 struct nand_bbt_descr *badblock_pattern; 422 423 void *priv; 424}; 425 426/* 427 * NAND Flash Manufacturer ID Codes 428 */ 429#define NAND_MFR_TOSHIBA 0x98 430#define NAND_MFR_SAMSUNG 0xec 431#define NAND_MFR_FUJITSU 0x04 432#define NAND_MFR_NATIONAL 0x8f 433#define NAND_MFR_RENESAS 0x07 434#define NAND_MFR_STMICRO 0x20 435#define NAND_MFR_HYNIX 0xad 436#define NAND_MFR_MICRON 0x2c 437#define NAND_MFR_AMD 0x01 438 439/** 440 * struct nand_flash_dev - NAND Flash Device ID Structure 441 * @name: Identify the device type 442 * @id: device ID code 443 * @pagesize: Pagesize in bytes. Either 256 or 512 or 0 444 * If the pagesize is 0, then the real pagesize 445 * and the eraseize are determined from the 446 * extended id bytes in the chip 447 * @erasesize: Size of an erase block in the flash device. 448 * @chipsize: Total chipsize in Mega Bytes 449 * @options: Bitfield to store chip relevant options 450 */ 451struct nand_flash_dev { 452 char *name; 453 int id; 454 unsigned long pagesize; 455 unsigned long chipsize; 456 unsigned long erasesize; 457 unsigned long options; 458}; 459 460/** 461 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure 462 * @name: Manufacturer name 463 * @id: manufacturer ID code of device. 464*/ 465struct nand_manufacturers { 466 int id; 467 char * name; 468}; 469 470extern struct nand_flash_dev nand_flash_ids[]; 471extern struct nand_manufacturers nand_manuf_ids[]; 472 473/** 474 * struct nand_bbt_descr - bad block table descriptor 475 * @options: options for this descriptor 476 * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE 477 * when bbt is searched, then we store the found bbts pages here. 478 * Its an array and supports up to 8 chips now 479 * @offs: offset of the pattern in the oob area of the page 480 * @veroffs: offset of the bbt version counter in the oob are of the page 481 * @version: version read from the bbt page during scan 482 * @len: length of the pattern, if 0 no pattern check is performed 483 * @maxblocks: maximum number of blocks to search for a bbt. This number of 484 * blocks is reserved at the end of the device where the tables are 485 * written. 486 * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than 487 * bad) block in the stored bbt 488 * @pattern: pattern to identify bad block table or factory marked good / 489 * bad blocks, can be NULL, if len = 0 490 * 491 * Descriptor for the bad block table marker and the descriptor for the 492 * pattern which identifies good and bad blocks. The assumption is made 493 * that the pattern and the version count are always located in the oob area 494 * of the first block. 495 */ 496struct nand_bbt_descr { 497 int options; 498 int pages[NAND_MAX_CHIPS]; 499 int offs; 500 int veroffs; 501 uint8_t version[NAND_MAX_CHIPS]; 502 int len; 503 int maxblocks; 504 int reserved_block_code; 505 uint8_t *pattern; 506}; 507 508/* Options for the bad block table descriptors */ 509 510/* The number of bits used per block in the bbt on the device */ 511#define NAND_BBT_NRBITS_MSK 0x0000000F 512#define NAND_BBT_1BIT 0x00000001 513#define NAND_BBT_2BIT 0x00000002 514#define NAND_BBT_4BIT 0x00000004 515#define NAND_BBT_8BIT 0x00000008 516/* The bad block table is in the last good block of the device */ 517#define NAND_BBT_LASTBLOCK 0x00000010 518/* The bbt is at the given page, else we must scan for the bbt */ 519#define NAND_BBT_ABSPAGE 0x00000020 520/* The bbt is at the given page, else we must scan for the bbt */ 521#define NAND_BBT_SEARCH 0x00000040 522/* bbt is stored per chip on multichip devices */ 523#define NAND_BBT_PERCHIP 0x00000080 524/* bbt has a version counter at offset veroffs */ 525#define NAND_BBT_VERSION 0x00000100 526/* Create a bbt if none axists */ 527#define NAND_BBT_CREATE 0x00000200 528/* Search good / bad pattern through all pages of a block */ 529#define NAND_BBT_SCANALLPAGES 0x00000400 530/* Scan block empty during good / bad block scan */ 531#define NAND_BBT_SCANEMPTY 0x00000800 532/* Write bbt if neccecary */ 533#define NAND_BBT_WRITE 0x00001000 534/* Read and write back block contents when writing bbt */ 535#define NAND_BBT_SAVECONTENT 0x00002000 536/* Search good / bad pattern on the first and the second page */ 537#define NAND_BBT_SCAN2NDPAGE 0x00004000 538 539/* The maximum number of blocks to scan for a bbt */ 540#define NAND_BBT_SCAN_MAXBLOCKS 4 541 542extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd); 543extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs); 544extern int nand_default_bbt(struct mtd_info *mtd); 545extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt); 546extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr, 547 int allowbbt); 548extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len, 549 size_t * retlen, uint8_t * buf); 550 551/* 552* Constants for oob configuration 553*/ 554#define NAND_SMALL_BADBLOCK_POS 5 555#define NAND_LARGE_BADBLOCK_POS 0 556 557/** 558 * struct platform_nand_chip - chip level device structure 559 * @nr_chips: max. number of chips to scan for 560 * @chip_offset: chip number offset 561 * @nr_partitions: number of partitions pointed to by partitions (or zero) 562 * @partitions: mtd partition list 563 * @chip_delay: R/B delay value in us 564 * @options: Option flags, e.g. 16bit buswidth 565 * @ecclayout: ecc layout info structure 566 * @part_probe_types: NULL-terminated array of probe types 567 * @set_parts: platform specific function to set partitions 568 * @priv: hardware controller specific settings 569 */ 570struct platform_nand_chip { 571 int nr_chips; 572 int chip_offset; 573 int nr_partitions; 574 struct mtd_partition *partitions; 575 struct nand_ecclayout *ecclayout; 576 int chip_delay; 577 unsigned int options; 578 const char **part_probe_types; 579 void (*set_parts)(uint64_t size, 580 struct platform_nand_chip *chip); 581 void *priv; 582}; 583 584/* Keep gcc happy */ 585struct platform_device; 586 587/** 588 * struct platform_nand_ctrl - controller level device structure 589 * @probe: platform specific function to probe/setup hardware 590 * @remove: platform specific function to remove/teardown hardware 591 * @hwcontrol: platform specific hardware control structure 592 * @dev_ready: platform specific function to read ready/busy pin 593 * @select_chip: platform specific chip select function 594 * @cmd_ctrl: platform specific function for controlling 595 * ALE/CLE/nCE. Also used to write command and address 596 * @write_buf: platform specific function for write buffer 597 * @read_buf: platform specific function for read buffer 598 * @priv: private data to transport driver specific settings 599 * 600 * All fields are optional and depend on the hardware driver requirements 601 */ 602struct platform_nand_ctrl { 603 int (*probe)(struct platform_device *pdev); 604 void (*remove)(struct platform_device *pdev); 605 void (*hwcontrol)(struct mtd_info *mtd, int cmd); 606 int (*dev_ready)(struct mtd_info *mtd); 607 void (*select_chip)(struct mtd_info *mtd, int chip); 608 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, 609 unsigned int ctrl); 610 void (*write_buf)(struct mtd_info *mtd, 611 const uint8_t *buf, int len); 612 void (*read_buf)(struct mtd_info *mtd, 613 uint8_t *buf, int len); 614 void *priv; 615}; 616 617/** 618 * struct platform_nand_data - container structure for platform-specific data 619 * @chip: chip level chip structure 620 * @ctrl: controller level device structure 621 */ 622struct platform_nand_data { 623 struct platform_nand_chip chip; 624 struct platform_nand_ctrl ctrl; 625}; 626 627/* Some helpers to access the data structures */ 628static inline 629struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd) 630{ 631 struct nand_chip *chip = mtd->priv; 632 633 return chip->priv; 634} 635 636#endif /* __LINUX_MTD_NAND_H */ 637