1#ifndef LINUX_SSB_REGS_H_
2#define LINUX_SSB_REGS_H_
3
4
5
6
7
8#define SSB_SDRAM_BASE 0x00000000U
9#define SSB_PCI_MEM 0x08000000U
10#define SSB_PCI_CFG 0x0c000000U
11#define SSB_SDRAM_SWAPPED 0x10000000U
12#define SSB_ENUM_BASE 0x18000000U
13#define SSB_ENUM_LIMIT 0x18010000U
14
15#define SSB_FLASH2 0x1c000000U
16#define SSB_FLASH2_SZ 0x02000000U
17
18#define SSB_EXTIF_BASE 0x1f000000U
19#define SSB_FLASH1 0x1fc00000U
20#define SSB_FLASH1_SZ 0x00400000U
21
22#define SSB_PCI_DMA 0x40000000U
23#define SSB_PCI_DMA_SZ 0x40000000U
24#define SSB_PCIE_DMA_L32 0x00000000U
25#define SSB_PCIE_DMA_H32 0x80000000U
26#define SSB_EUART (SSB_EXTIF_BASE + 0x00800000)
27#define SSB_LED (SSB_EXTIF_BASE + 0x00900000)
28
29
30
31#define SSB_CORE_SIZE 0x1000
32#define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
33
34
35
36#define SSB_EJTAG 0xff200000
37
38
39
40#define SSB_PMCSR 0x44
41#define SSB_PE 0x100
42#define SSB_BAR0_WIN 0x80
43#define SSB_BAR1_WIN 0x84
44#define SSB_SPROMCTL 0x88
45#define SSB_SPROMCTL_WE 0x10
46#define SSB_BAR1_CONTROL 0x8c
47#define SSB_PCI_IRQS 0x90
48#define SSB_PCI_IRQMASK 0x94
49#define SSB_BACKPLANE_IRQS 0x98
50#define SSB_GPIO_IN 0xB0
51#define SSB_GPIO_OUT 0xB4
52#define SSB_GPIO_OUT_ENABLE 0xB8
53#define SSB_GPIO_SCS 0x10
54#define SSB_GPIO_HWRAD 0x20
55#define SSB_GPIO_XTAL 0x40
56#define SSB_GPIO_PLL 0x80
57
58
59#define SSB_BAR0_MAX_RETRIES 50
60
61
62#define SSB_IPSFLAG 0x0F08
63#define SSB_IPSFLAG_IRQ1 0x0000003F
64#define SSB_IPSFLAG_IRQ1_SHIFT 0
65#define SSB_IPSFLAG_IRQ2 0x00003F00
66#define SSB_IPSFLAG_IRQ2_SHIFT 8
67#define SSB_IPSFLAG_IRQ3 0x003F0000
68#define SSB_IPSFLAG_IRQ3_SHIFT 16
69#define SSB_IPSFLAG_IRQ4 0x3F000000
70#define SSB_IPSFLAG_IRQ4_SHIFT 24
71#define SSB_TPSFLAG 0x0F18
72#define SSB_TPSFLAG_BPFLAG 0x0000003F
73#define SSB_TPSFLAG_ALWAYSIRQ 0x00000040
74#define SSB_TMERRLOGA 0x0F48
75#define SSB_TMERRLOG 0x0F50
76#define SSB_ADMATCH3 0x0F60
77#define SSB_ADMATCH2 0x0F68
78#define SSB_ADMATCH1 0x0F70
79#define SSB_IMSTATE 0x0F90
80#define SSB_IMSTATE_PC 0x0000000f
81#define SSB_IMSTATE_AP_MASK 0x00000030
82#define SSB_IMSTATE_AP_BOTH 0x00000000
83#define SSB_IMSTATE_AP_TS 0x00000010
84#define SSB_IMSTATE_AP_TK 0x00000020
85#define SSB_IMSTATE_AP_RSV 0x00000030
86#define SSB_IMSTATE_IBE 0x00020000
87#define SSB_IMSTATE_TO 0x00040000
88#define SSB_INTVEC 0x0F94
89#define SSB_INTVEC_PCI 0x00000001
90#define SSB_INTVEC_ENET0 0x00000002
91#define SSB_INTVEC_ILINE20 0x00000004
92#define SSB_INTVEC_CODEC 0x00000008
93#define SSB_INTVEC_USB 0x00000010
94#define SSB_INTVEC_EXTIF 0x00000020
95#define SSB_INTVEC_ENET1 0x00000040
96#define SSB_TMSLOW 0x0F98
97#define SSB_TMSLOW_RESET 0x00000001
98#define SSB_TMSLOW_REJECT_22 0x00000002
99#define SSB_TMSLOW_REJECT_23 0x00000004
100#define SSB_TMSLOW_CLOCK 0x00010000
101#define SSB_TMSLOW_FGC 0x00020000
102#define SSB_TMSLOW_PE 0x40000000
103#define SSB_TMSLOW_BE 0x80000000
104#define SSB_TMSHIGH 0x0F9C
105#define SSB_TMSHIGH_SERR 0x00000001
106#define SSB_TMSHIGH_INT 0x00000002
107#define SSB_TMSHIGH_BUSY 0x00000004
108#define SSB_TMSHIGH_TO 0x00000020
109#define SSB_TMSHIGH_COREFL 0x1FFF0000
110#define SSB_TMSHIGH_COREFL_SHIFT 16
111#define SSB_TMSHIGH_DMA64 0x10000000
112#define SSB_TMSHIGH_GCR 0x20000000
113#define SSB_TMSHIGH_BISTF 0x40000000
114#define SSB_TMSHIGH_BISTD 0x80000000
115#define SSB_BWA0 0x0FA0
116#define SSB_IMCFGLO 0x0FA8
117#define SSB_IMCFGLO_SERTO 0x00000007
118#define SSB_IMCFGLO_REQTO 0x00000070
119#define SSB_IMCFGLO_REQTO_SHIFT 4
120#define SSB_IMCFGLO_CONNID 0x00FF0000
121#define SSB_IMCFGLO_CONNID_SHIFT 16
122#define SSB_IMCFGHI 0x0FAC
123#define SSB_ADMATCH0 0x0FB0
124#define SSB_TMCFGLO 0x0FB8
125#define SSB_TMCFGHI 0x0FBC
126#define SSB_BCONFIG 0x0FC0
127#define SSB_BSTATE 0x0FC8
128#define SSB_ACTCFG 0x0FD8
129#define SSB_FLAGST 0x0FE8
130#define SSB_IDLOW 0x0FF8
131#define SSB_IDLOW_CFGSP 0x00000003
132#define SSB_IDLOW_ADDRNGE 0x00000038
133#define SSB_IDLOW_ADDRNGE_SHIFT 3
134#define SSB_IDLOW_SYNC 0x00000040
135#define SSB_IDLOW_INITIATOR 0x00000080
136#define SSB_IDLOW_MIBL 0x00000F00
137#define SSB_IDLOW_MIBL_SHIFT 8
138#define SSB_IDLOW_MABL 0x0000F000
139#define SSB_IDLOW_MABL_SHIFT 12
140#define SSB_IDLOW_TIF 0x00010000
141#define SSB_IDLOW_CCW 0x000C0000
142#define SSB_IDLOW_CCW_SHIFT 18
143#define SSB_IDLOW_TPT 0x00F00000
144#define SSB_IDLOW_TPT_SHIFT 20
145#define SSB_IDLOW_INITP 0x0F000000
146#define SSB_IDLOW_INITP_SHIFT 24
147#define SSB_IDLOW_SSBREV 0xF0000000
148#define SSB_IDLOW_SSBREV_22 0x00000000
149#define SSB_IDLOW_SSBREV_23 0x10000000
150#define SSB_IDLOW_SSBREV_24 0x40000000
151#define SSB_IDLOW_SSBREV_25 0x50000000
152#define SSB_IDLOW_SSBREV_26 0x60000000
153#define SSB_IDLOW_SSBREV_27 0x70000000
154#define SSB_IDHIGH 0x0FFC
155#define SSB_IDHIGH_RCLO 0x0000000F
156#define SSB_IDHIGH_CC 0x00008FF0
157#define SSB_IDHIGH_CC_SHIFT 4
158#define SSB_IDHIGH_RCHI 0x00007000
159#define SSB_IDHIGH_RCHI_SHIFT 8
160#define SSB_IDHIGH_VC 0xFFFF0000
161#define SSB_IDHIGH_VC_SHIFT 16
162
163
164
165
166
167#define SSB_SPROMSIZE_WORDS 64
168#define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
169#define SSB_SPROMSIZE_WORDS_R123 64
170#define SSB_SPROMSIZE_WORDS_R4 220
171#define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
172#define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
173#define SSB_SPROM_BASE 0x1000
174#define SSB_SPROM_REVISION 0x107E
175#define SSB_SPROM_REVISION_REV 0x00FF
176#define SSB_SPROM_REVISION_CRC 0xFF00
177#define SSB_SPROM_REVISION_CRC_SHIFT 8
178
179
180#define SSB_SPROM1_SPID 0x1004
181#define SSB_SPROM1_SVID 0x1006
182#define SSB_SPROM1_PID 0x1008
183#define SSB_SPROM1_IL0MAC 0x1048
184#define SSB_SPROM1_ET0MAC 0x104E
185#define SSB_SPROM1_ET1MAC 0x1054
186#define SSB_SPROM1_ETHPHY 0x105A
187#define SSB_SPROM1_ETHPHY_ET0A 0x001F
188#define SSB_SPROM1_ETHPHY_ET1A 0x03E0
189#define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
190#define SSB_SPROM1_ETHPHY_ET0M (1<<14)
191#define SSB_SPROM1_ETHPHY_ET1M (1<<15)
192#define SSB_SPROM1_BINF 0x105C
193#define SSB_SPROM1_BINF_BREV 0x00FF
194#define SSB_SPROM1_BINF_CCODE 0x0F00
195#define SSB_SPROM1_BINF_CCODE_SHIFT 8
196#define SSB_SPROM1_BINF_ANTBG 0x3000
197#define SSB_SPROM1_BINF_ANTBG_SHIFT 12
198#define SSB_SPROM1_BINF_ANTA 0xC000
199#define SSB_SPROM1_BINF_ANTA_SHIFT 14
200#define SSB_SPROM1_PA0B0 0x105E
201#define SSB_SPROM1_PA0B1 0x1060
202#define SSB_SPROM1_PA0B2 0x1062
203#define SSB_SPROM1_GPIOA 0x1064
204#define SSB_SPROM1_GPIOA_P0 0x00FF
205#define SSB_SPROM1_GPIOA_P1 0xFF00
206#define SSB_SPROM1_GPIOA_P1_SHIFT 8
207#define SSB_SPROM1_GPIOB 0x1066
208#define SSB_SPROM1_GPIOB_P2 0x00FF
209#define SSB_SPROM1_GPIOB_P3 0xFF00
210#define SSB_SPROM1_GPIOB_P3_SHIFT 8
211#define SSB_SPROM1_MAXPWR 0x1068
212#define SSB_SPROM1_MAXPWR_BG 0x00FF
213#define SSB_SPROM1_MAXPWR_A 0xFF00
214#define SSB_SPROM1_MAXPWR_A_SHIFT 8
215#define SSB_SPROM1_PA1B0 0x106A
216#define SSB_SPROM1_PA1B1 0x106C
217#define SSB_SPROM1_PA1B2 0x106E
218#define SSB_SPROM1_ITSSI 0x1070
219#define SSB_SPROM1_ITSSI_BG 0x00FF
220#define SSB_SPROM1_ITSSI_A 0xFF00
221#define SSB_SPROM1_ITSSI_A_SHIFT 8
222#define SSB_SPROM1_BFLLO 0x1072
223#define SSB_SPROM1_AGAIN 0x1074
224#define SSB_SPROM1_AGAIN_BG 0x00FF
225#define SSB_SPROM1_AGAIN_BG_SHIFT 0
226#define SSB_SPROM1_AGAIN_A 0xFF00
227#define SSB_SPROM1_AGAIN_A_SHIFT 8
228
229
230#define SSB_SPROM2_BFLHI 0x1038
231#define SSB_SPROM2_MAXP_A 0x103A
232#define SSB_SPROM2_MAXP_A_HI 0x00FF
233#define SSB_SPROM2_MAXP_A_LO 0xFF00
234#define SSB_SPROM2_MAXP_A_LO_SHIFT 8
235#define SSB_SPROM2_PA1LOB0 0x103C
236#define SSB_SPROM2_PA1LOB1 0x103E
237#define SSB_SPROM2_PA1LOB2 0x1040
238#define SSB_SPROM2_PA1HIB0 0x1042
239#define SSB_SPROM2_PA1HIB1 0x1044
240#define SSB_SPROM2_PA1HIB2 0x1046
241#define SSB_SPROM2_OPO 0x1078
242#define SSB_SPROM2_OPO_VALUE 0x00FF
243#define SSB_SPROM2_OPO_UNUSED 0xFF00
244#define SSB_SPROM2_CCODE 0x107C
245
246
247#define SSB_SPROM3_IL0MAC 0x104A
248#define SSB_SPROM3_OFDMAPO 0x102C
249#define SSB_SPROM3_OFDMALPO 0x1030
250#define SSB_SPROM3_OFDMAHPO 0x1034
251#define SSB_SPROM3_GPIOLDC 0x1042
252#define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00
253#define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
254#define SSB_SPROM3_GPIOLDC_ON 0x00FF0000
255#define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
256#define SSB_SPROM3_CCKPO 0x1078
257#define SSB_SPROM3_CCKPO_1M 0x000F
258#define SSB_SPROM3_CCKPO_2M 0x00F0
259#define SSB_SPROM3_CCKPO_2M_SHIFT 4
260#define SSB_SPROM3_CCKPO_55M 0x0F00
261#define SSB_SPROM3_CCKPO_55M_SHIFT 8
262#define SSB_SPROM3_CCKPO_11M 0xF000
263#define SSB_SPROM3_CCKPO_11M_SHIFT 12
264#define SSB_SPROM3_OFDMGPO 0x107A
265
266
267#define SSB_SPROM4_IL0MAC 0x104C
268#define SSB_SPROM4_ETHPHY 0x105A
269#define SSB_SPROM4_ETHPHY_ET0A 0x001F
270#define SSB_SPROM4_ETHPHY_ET1A 0x03E0
271#define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
272#define SSB_SPROM4_ETHPHY_ET0M (1<<14)
273#define SSB_SPROM4_ETHPHY_ET1M (1<<15)
274#define SSB_SPROM4_CCODE 0x1052
275#define SSB_SPROM4_ANTAVAIL 0x105D
276#define SSB_SPROM4_ANTAVAIL_A 0x00FF
277#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
278#define SSB_SPROM4_ANTAVAIL_BG 0xFF00
279#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
280#define SSB_SPROM4_BFLLO 0x1044
281#define SSB_SPROM4_AGAIN01 0x105E
282#define SSB_SPROM4_AGAIN0 0x00FF
283#define SSB_SPROM4_AGAIN0_SHIFT 0
284#define SSB_SPROM4_AGAIN1 0xFF00
285#define SSB_SPROM4_AGAIN1_SHIFT 8
286#define SSB_SPROM4_AGAIN23 0x1060
287#define SSB_SPROM4_AGAIN2 0x00FF
288#define SSB_SPROM4_AGAIN2_SHIFT 0
289#define SSB_SPROM4_AGAIN3 0xFF00
290#define SSB_SPROM4_AGAIN3_SHIFT 8
291#define SSB_SPROM4_BFLHI 0x1046
292#define SSB_SPROM4_MAXP_BG 0x1080
293#define SSB_SPROM4_MAXP_BG_MASK 0x00FF
294#define SSB_SPROM4_ITSSI_BG 0xFF00
295#define SSB_SPROM4_ITSSI_BG_SHIFT 8
296#define SSB_SPROM4_MAXP_A 0x108A
297#define SSB_SPROM4_MAXP_A_MASK 0x00FF
298#define SSB_SPROM4_ITSSI_A 0xFF00
299#define SSB_SPROM4_ITSSI_A_SHIFT 8
300#define SSB_SPROM4_GPIOA 0x1056
301#define SSB_SPROM4_GPIOA_P0 0x00FF
302#define SSB_SPROM4_GPIOA_P1 0xFF00
303#define SSB_SPROM4_GPIOA_P1_SHIFT 8
304#define SSB_SPROM4_GPIOB 0x1058
305#define SSB_SPROM4_GPIOB_P2 0x00FF
306#define SSB_SPROM4_GPIOB_P3 0xFF00
307#define SSB_SPROM4_GPIOB_P3_SHIFT 8
308#define SSB_SPROM4_PA0B0 0x1082
309#define SSB_SPROM4_PA0B1 0x1084
310#define SSB_SPROM4_PA0B2 0x1086
311#define SSB_SPROM4_PA1B0 0x108E
312#define SSB_SPROM4_PA1B1 0x1090
313#define SSB_SPROM4_PA1B2 0x1092
314
315
316#define SSB_SPROM5_BFLLO 0x104A
317#define SSB_SPROM5_BFLHI 0x104C
318#define SSB_SPROM5_IL0MAC 0x1052
319#define SSB_SPROM5_CCODE 0x1044
320#define SSB_SPROM5_GPIOA 0x1076
321#define SSB_SPROM5_GPIOA_P0 0x00FF
322#define SSB_SPROM5_GPIOA_P1 0xFF00
323#define SSB_SPROM5_GPIOA_P1_SHIFT 8
324#define SSB_SPROM5_GPIOB 0x1078
325#define SSB_SPROM5_GPIOB_P2 0x00FF
326#define SSB_SPROM5_GPIOB_P3 0xFF00
327#define SSB_SPROM5_GPIOB_P3_SHIFT 8
328
329
330#define SSB_SPROM8_BOARDREV 0x1082
331#define SSB_SPROM8_BFLLO 0x1084
332#define SSB_SPROM8_BFLHI 0x1086
333#define SSB_SPROM8_BFL2LO 0x1088
334#define SSB_SPROM8_BFL2HI 0x108A
335#define SSB_SPROM8_IL0MAC 0x108C
336#define SSB_SPROM8_CCODE 0x1092
337#define SSB_SPROM8_ANTAVAIL 0x109C
338#define SSB_SPROM8_ANTAVAIL_A 0xFF00
339#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
340#define SSB_SPROM8_ANTAVAIL_BG 0x00FF
341#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
342#define SSB_SPROM8_AGAIN01 0x109E
343#define SSB_SPROM8_AGAIN0 0x00FF
344#define SSB_SPROM8_AGAIN0_SHIFT 0
345#define SSB_SPROM8_AGAIN1 0xFF00
346#define SSB_SPROM8_AGAIN1_SHIFT 8
347#define SSB_SPROM8_AGAIN23 0x10A0
348#define SSB_SPROM8_AGAIN2 0x00FF
349#define SSB_SPROM8_AGAIN2_SHIFT 0
350#define SSB_SPROM8_AGAIN3 0xFF00
351#define SSB_SPROM8_AGAIN3_SHIFT 8
352#define SSB_SPROM8_GPIOA 0x1096
353#define SSB_SPROM8_GPIOA_P0 0x00FF
354#define SSB_SPROM8_GPIOA_P1 0xFF00
355#define SSB_SPROM8_GPIOA_P1_SHIFT 8
356#define SSB_SPROM8_GPIOB 0x1098
357#define SSB_SPROM8_GPIOB_P2 0x00FF
358#define SSB_SPROM8_GPIOB_P3 0xFF00
359#define SSB_SPROM8_GPIOB_P3_SHIFT 8
360#define SSB_SPROM8_RSSIPARM2G 0x10A4
361#define SSB_SPROM8_RSSISMF2G 0x000F
362#define SSB_SPROM8_RSSISMC2G 0x00F0
363#define SSB_SPROM8_RSSISMC2G_SHIFT 4
364#define SSB_SPROM8_RSSISAV2G 0x0700
365#define SSB_SPROM8_RSSISAV2G_SHIFT 8
366#define SSB_SPROM8_BXA2G 0x1800
367#define SSB_SPROM8_BXA2G_SHIFT 11
368#define SSB_SPROM8_RSSIPARM5G 0x10A6
369#define SSB_SPROM8_RSSISMF5G 0x000F
370#define SSB_SPROM8_RSSISMC5G 0x00F0
371#define SSB_SPROM8_RSSISMC5G_SHIFT 4
372#define SSB_SPROM8_RSSISAV5G 0x0700
373#define SSB_SPROM8_RSSISAV5G_SHIFT 8
374#define SSB_SPROM8_BXA5G 0x1800
375#define SSB_SPROM8_BXA5G_SHIFT 11
376#define SSB_SPROM8_TRI25G 0x10A8
377#define SSB_SPROM8_TRI2G 0x00FF
378#define SSB_SPROM8_TRI5G 0xFF00
379#define SSB_SPROM8_TRI5G_SHIFT 8
380#define SSB_SPROM8_TRI5GHL 0x10AA
381#define SSB_SPROM8_TRI5GL 0x00FF
382#define SSB_SPROM8_TRI5GH 0xFF00
383#define SSB_SPROM8_TRI5GH_SHIFT 8
384#define SSB_SPROM8_RXPO 0x10AC
385#define SSB_SPROM8_RXPO2G 0x00FF
386#define SSB_SPROM8_RXPO5G 0xFF00
387#define SSB_SPROM8_RXPO5G_SHIFT 8
388#define SSB_SPROM8_MAXP_BG 0x10C0
389#define SSB_SPROM8_MAXP_BG_MASK 0x00FF
390#define SSB_SPROM8_ITSSI_BG 0xFF00
391#define SSB_SPROM8_ITSSI_BG_SHIFT 8
392#define SSB_SPROM8_PA0B0 0x10C2
393#define SSB_SPROM8_PA0B1 0x10C4
394#define SSB_SPROM8_PA0B2 0x10C6
395#define SSB_SPROM8_MAXP_A 0x10C8
396#define SSB_SPROM8_MAXP_A_MASK 0x00FF
397#define SSB_SPROM8_ITSSI_A 0xFF00
398#define SSB_SPROM8_ITSSI_A_SHIFT 8
399#define SSB_SPROM8_MAXP_AHL 0x10CA
400#define SSB_SPROM8_MAXP_AH_MASK 0x00FF
401#define SSB_SPROM8_MAXP_AL_MASK 0xFF00
402#define SSB_SPROM8_MAXP_AL_SHIFT 8
403#define SSB_SPROM8_PA1B0 0x10CC
404#define SSB_SPROM8_PA1B1 0x10CE
405#define SSB_SPROM8_PA1B2 0x10D0
406#define SSB_SPROM8_PA1LOB0 0x10D2
407#define SSB_SPROM8_PA1LOB1 0x10D4
408#define SSB_SPROM8_PA1LOB2 0x10D6
409#define SSB_SPROM8_PA1HIB0 0x10D8
410#define SSB_SPROM8_PA1HIB1 0x10DA
411#define SSB_SPROM8_PA1HIB2 0x10DC
412#define SSB_SPROM8_CCK2GPO 0x1140
413#define SSB_SPROM8_OFDM2GPO 0x1142
414#define SSB_SPROM8_OFDM5GPO 0x1146
415#define SSB_SPROM8_OFDM5GLPO 0x114A
416#define SSB_SPROM8_OFDM5GHPO 0x114E
417
418
419enum {
420 SSB_SPROM1CCODE_WORLD = 0,
421 SSB_SPROM1CCODE_THAILAND,
422 SSB_SPROM1CCODE_ISRAEL,
423 SSB_SPROM1CCODE_JORDAN,
424 SSB_SPROM1CCODE_CHINA,
425 SSB_SPROM1CCODE_JAPAN,
426 SSB_SPROM1CCODE_USA_CANADA_ANZ,
427 SSB_SPROM1CCODE_EUROPE,
428 SSB_SPROM1CCODE_USA_LOW,
429 SSB_SPROM1CCODE_JAPAN_HIGH,
430 SSB_SPROM1CCODE_ALL,
431 SSB_SPROM1CCODE_NONE,
432};
433
434
435#define SSB_ADM_TYPE 0x00000003
436#define SSB_ADM_TYPE0 0
437#define SSB_ADM_TYPE1 1
438#define SSB_ADM_TYPE2 2
439#define SSB_ADM_AD64 0x00000004
440#define SSB_ADM_SZ0 0x000000F8
441#define SSB_ADM_SZ0_SHIFT 3
442#define SSB_ADM_SZ1 0x000001F8
443#define SSB_ADM_SZ1_SHIFT 3
444#define SSB_ADM_SZ2 0x000001F8
445#define SSB_ADM_SZ2_SHIFT 3
446#define SSB_ADM_EN 0x00000400
447#define SSB_ADM_NEG 0x00000800
448#define SSB_ADM_BASE0 0xFFFFFF00
449#define SSB_ADM_BASE0_SHIFT 8
450#define SSB_ADM_BASE1 0xFFFFF000
451#define SSB_ADM_BASE1_SHIFT 12
452#define SSB_ADM_BASE2 0xFFFF0000
453#define SSB_ADM_BASE2_SHIFT 16
454
455
456#endif
457