1#ifndef __SOUND_EMU10K1_H
2#define __SOUND_EMU10K1_H
3
4#include <linux/types.h>
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28#ifdef __KERNEL__
29
30#include <sound/pcm.h>
31#include <sound/rawmidi.h>
32#include <sound/hwdep.h>
33#include <sound/ac97_codec.h>
34#include <sound/util_mem.h>
35#include <sound/pcm-indirect.h>
36#include <sound/timer.h>
37#include <linux/interrupt.h>
38#include <linux/mutex.h>
39
40#include <asm/io.h>
41
42
43
44#define EMUPAGESIZE 4096
45#define MAXREQVOICES 8
46#define MAXPAGES 8192
47#define RESERVED 0
48#define NUM_MIDI 16
49#define NUM_G 64
50#define NUM_FXSENDS 4
51#define NUM_EFX_PLAYBACK 16
52
53
54#define EMU10K1_DMA_MASK 0x7fffffffUL
55#define AUDIGY_DMA_MASK 0x7fffffffUL
56
57
58#define TMEMSIZE 256*1024
59#define TMEMSIZEREG 4
60
61#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
62
63
64
65
66
67
68
69#define PTR 0x00
70
71
72#define PTR_CHANNELNUM_MASK 0x0000003f
73
74
75
76#define PTR_ADDRESS_MASK 0x07ff0000
77#define A_PTR_ADDRESS_MASK 0x0fff0000
78
79#define DATA 0x04
80
81#define IPR 0x08
82
83
84#define IPR_P16V 0x80000000
85
86#define IPR_GPIOMSG 0x20000000
87
88
89
90#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000
91#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000
92
93#define IPR_SPDIFBUFFULL 0x04000000
94#define IPR_SPDIFBUFHALFFULL 0x02000000
95
96#define IPR_SAMPLERATETRACKER 0x01000000
97#define IPR_FXDSP 0x00800000
98#define IPR_FORCEINT 0x00400000
99#define IPR_PCIERROR 0x00200000
100#define IPR_VOLINCR 0x00100000
101#define IPR_VOLDECR 0x00080000
102#define IPR_MUTE 0x00040000
103#define IPR_MICBUFFULL 0x00020000
104#define IPR_MICBUFHALFFULL 0x00010000
105#define IPR_ADCBUFFULL 0x00008000
106#define IPR_ADCBUFHALFFULL 0x00004000
107#define IPR_EFXBUFFULL 0x00002000
108#define IPR_EFXBUFHALFFULL 0x00001000
109#define IPR_GPSPDIFSTATUSCHANGE 0x00000800
110#define IPR_CDROMSTATUSCHANGE 0x00000400
111#define IPR_INTERVALTIMER 0x00000200
112#define IPR_MIDITRANSBUFEMPTY 0x00000100
113#define IPR_MIDIRECVBUFEMPTY 0x00000080
114#define IPR_CHANNELLOOP 0x00000040
115#define IPR_CHANNELNUMBERMASK 0x0000003f
116
117
118
119
120
121#define INTE 0x0c
122#define INTE_VIRTUALSB_MASK 0xc0000000
123#define INTE_VIRTUALSB_220 0x00000000
124#define INTE_VIRTUALSB_240 0x40000000
125#define INTE_VIRTUALSB_260 0x80000000
126#define INTE_VIRTUALSB_280 0xc0000000
127#define INTE_VIRTUALMPU_MASK 0x30000000
128#define INTE_VIRTUALMPU_300 0x00000000
129#define INTE_VIRTUALMPU_310 0x10000000
130#define INTE_VIRTUALMPU_320 0x20000000
131#define INTE_VIRTUALMPU_330 0x30000000
132#define INTE_MASTERDMAENABLE 0x08000000
133#define INTE_SLAVEDMAENABLE 0x04000000
134#define INTE_MASTERPICENABLE 0x02000000
135#define INTE_SLAVEPICENABLE 0x01000000
136#define INTE_VSBENABLE 0x00800000
137#define INTE_ADLIBENABLE 0x00400000
138#define INTE_MPUENABLE 0x00200000
139#define INTE_FORCEINT 0x00100000
140
141#define INTE_MRHANDENABLE 0x00080000
142
143
144
145
146
147
148#define INTE_A_MIDITXENABLE2 0x00020000
149#define INTE_A_MIDIRXENABLE2 0x00010000
150
151
152#define INTE_SAMPLERATETRACKER 0x00002000
153
154#define INTE_FXDSPENABLE 0x00001000
155#define INTE_PCIERRORENABLE 0x00000800
156#define INTE_VOLINCRENABLE 0x00000400
157#define INTE_VOLDECRENABLE 0x00000200
158#define INTE_MUTEENABLE 0x00000100
159#define INTE_MICBUFENABLE 0x00000080
160#define INTE_ADCBUFENABLE 0x00000040
161#define INTE_EFXBUFENABLE 0x00000020
162#define INTE_GPSPDIFENABLE 0x00000010
163#define INTE_CDSPDIFENABLE 0x00000008
164#define INTE_INTERVALTIMERENB 0x00000004
165#define INTE_MIDITXENABLE 0x00000002
166#define INTE_MIDIRXENABLE 0x00000001
167
168#define WC 0x10
169#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0
170#define WC_SAMPLECOUNTER 0x14060010
171#define WC_CURRENTCHANNEL 0x0000003F
172
173
174
175#define HCFG 0x14
176
177
178
179
180#define HCFG_LEGACYFUNC_MASK 0xe0000000
181#define HCFG_LEGACYFUNC_MPU 0x00000000
182#define HCFG_LEGACYFUNC_SB 0x40000000
183#define HCFG_LEGACYFUNC_AD 0x60000000
184#define HCFG_LEGACYFUNC_MPIC 0x80000000
185#define HCFG_LEGACYFUNC_MDMA 0xa0000000
186#define HCFG_LEGACYFUNC_SPCI 0xc0000000
187#define HCFG_LEGACYFUNC_SDMA 0xe0000000
188#define HCFG_IOCAPTUREADDR 0x1f000000
189#define HCFG_LEGACYWRITE 0x00800000
190#define HCFG_LEGACYWORD 0x00400000
191#define HCFG_LEGACYINT 0x00200000
192
193
194#define HCFG_PUSH_BUTTON_ENABLE 0x00100000
195#define HCFG_BAUD_RATE 0x00080000
196#define HCFG_EXPANDED_MEM 0x00040000
197#define HCFG_CODECFORMAT_MASK 0x00030000
198
199
200#define HCFG_CODECFORMAT_AC97_1 0x00000000
201#define HCFG_CODECFORMAT_AC97_2 0x00010000
202#define HCFG_AUTOMUTE_ASYNC 0x00008000
203
204
205
206#define HCFG_AUTOMUTE_SPDIF 0x00004000
207
208
209#define HCFG_EMU32_SLAVE 0x00002000
210#define HCFG_SLOW_RAMP 0x00001000
211
212#define HCFG_PHASE_TRACK_MASK 0x00000700
213
214
215#define HCFG_I2S_ASRC_ENABLE 0x00000070
216
217
218
219
220
221
222
223#define HCFG_CODECFORMAT_AC97 0x00000000
224#define HCFG_CODECFORMAT_I2S 0x00010000
225#define HCFG_GPINPUT0 0x00004000
226#define HCFG_GPINPUT1 0x00002000
227#define HCFG_GPOUTPUT_MASK 0x00001c00
228#define HCFG_GPOUT0 0x00001000
229#define HCFG_GPOUT1 0x00000800
230#define HCFG_GPOUT2 0x00000400
231#define HCFG_JOYENABLE 0x00000200
232#define HCFG_PHASETRACKENABLE 0x00000100
233
234
235#define HCFG_AC3ENABLE_MASK 0x000000e0
236#define HCFG_AC3ENABLE_ZVIDEO 0x00000080
237#define HCFG_AC3ENABLE_CDSPDIF 0x00000040
238#define HCFG_AC3ENABLE_GPSPDIF 0x00000020
239#define HCFG_AUTOMUTE 0x00000010
240
241
242
243#define HCFG_LOCKSOUNDCACHE 0x00000008
244
245#define HCFG_LOCKTANKCACHE_MASK 0x00000004
246
247#define HCFG_LOCKTANKCACHE 0x01020014
248#define HCFG_MUTEBUTTONENABLE 0x00000002
249
250
251
252
253
254#define HCFG_AUDIOENABLE 0x00000001
255
256
257
258
259
260#define MUDATA 0x18
261
262#define MUCMD 0x19
263#define MUCMD_RESET 0xff
264#define MUCMD_ENTERUARTMODE 0x3f
265
266
267#define MUSTAT MUCMD
268#define MUSTAT_IRDYN 0x80
269#define MUSTAT_ORDYN 0x40
270
271#define A_IOCFG 0x18
272#define A_GPINPUT_MASK 0xff00
273#define A_GPOUTPUT_MASK 0x00ff
274
275
276#define A_IOCFG_GPOUT0 0x0044
277#define A_IOCFG_DISABLE_ANALOG 0x0040
278#define A_IOCFG_ENABLE_DIGITAL 0x0004
279#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
280#define A_IOCFG_UNKNOWN_20 0x0020
281#define A_IOCFG_DISABLE_AC97_FRONT 0x0080
282#define A_IOCFG_GPOUT1 0x0002
283#define A_IOCFG_GPOUT2 0x0001
284#define A_IOCFG_MULTIPURPOSE_JACK 0x2000
285
286#define A_IOCFG_DIGITAL_JACK 0x1000
287#define A_IOCFG_FRONT_JACK 0x4000
288#define A_IOCFG_REAR_JACK 0x8000
289#define A_IOCFG_PHONES_JACK 0x0100
290
291
292
293
294
295
296
297#define TIMER 0x1a
298
299
300
301#define TIMER_RATE_MASK 0x000003ff
302
303#define TIMER_RATE 0x0a00001a
304
305#define AC97DATA 0x1c
306
307#define AC97ADDRESS 0x1e
308#define AC97ADDRESS_READY 0x80
309#define AC97ADDRESS_ADDRESS 0x7f
310
311
312#define PTR2 0x20
313#define DATA2 0x24
314#define IPR2 0x28
315#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000
316#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100
317#define IPR2_CAPTURE_CH_0_LOOP 0x00100000
318#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000
319
320
321
322#define INTE2 0x2c
323#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000
324#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100
325#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000
326#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200
327#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000
328#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400
329#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000
330#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800
331#define INTE2_CAPTURE_CH_0_LOOP 0x00100000
332#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000
333#define HCFG2 0x34
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349#define IPR3 0x38
350#define INTE3 0x3c
351
352
353
354
355#define JOYSTICK1 0x00
356#define JOYSTICK2 0x01
357#define JOYSTICK3 0x02
358#define JOYSTICK4 0x03
359#define JOYSTICK5 0x04
360#define JOYSTICK6 0x05
361#define JOYSTICK7 0x06
362#define JOYSTICK8 0x07
363
364
365
366#define JOYSTICK_BUTTONS 0x0f
367#define JOYSTICK_COMPARATOR 0xf0
368
369
370
371
372
373
374#define CPF 0x00
375#define CPF_CURRENTPITCH_MASK 0xffff0000
376#define CPF_CURRENTPITCH 0x10100000
377#define CPF_STEREO_MASK 0x00008000
378#define CPF_STOP_MASK 0x00004000
379#define CPF_FRACADDRESS_MASK 0x00003fff
380
381#define PTRX 0x01
382#define PTRX_PITCHTARGET_MASK 0xffff0000
383#define PTRX_PITCHTARGET 0x10100001
384#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00
385#define PTRX_FXSENDAMOUNT_A 0x08080001
386#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff
387#define PTRX_FXSENDAMOUNT_B 0x08000001
388
389#define CVCF 0x02
390#define CVCF_CURRENTVOL_MASK 0xffff0000
391#define CVCF_CURRENTVOL 0x10100002
392#define CVCF_CURRENTFILTER_MASK 0x0000ffff
393#define CVCF_CURRENTFILTER 0x10000002
394
395#define VTFT 0x03
396#define VTFT_VOLUMETARGET_MASK 0xffff0000
397#define VTFT_VOLUMETARGET 0x10100003
398#define VTFT_FILTERTARGET_MASK 0x0000ffff
399#define VTFT_FILTERTARGET 0x10000003
400
401#define Z1 0x05
402
403#define Z2 0x04
404
405#define PSST 0x06
406#define PSST_FXSENDAMOUNT_C_MASK 0xff000000
407
408#define PSST_FXSENDAMOUNT_C 0x08180006
409
410#define PSST_LOOPSTARTADDR_MASK 0x00ffffff
411#define PSST_LOOPSTARTADDR 0x18000006
412
413#define DSL 0x07
414#define DSL_FXSENDAMOUNT_D_MASK 0xff000000
415
416#define DSL_FXSENDAMOUNT_D 0x08180007
417
418#define DSL_LOOPENDADDR_MASK 0x00ffffff
419#define DSL_LOOPENDADDR 0x18000007
420
421#define CCCA 0x08
422#define CCCA_RESONANCE 0xf0000000
423#define CCCA_INTERPROMMASK 0x0e000000
424
425
426
427
428
429#define CCCA_INTERPROM_0 0x00000000
430#define CCCA_INTERPROM_1 0x02000000
431#define CCCA_INTERPROM_2 0x04000000
432#define CCCA_INTERPROM_3 0x06000000
433#define CCCA_INTERPROM_4 0x08000000
434#define CCCA_INTERPROM_5 0x0a000000
435#define CCCA_INTERPROM_6 0x0c000000
436#define CCCA_INTERPROM_7 0x0e000000
437#define CCCA_8BITSELECT 0x01000000
438#define CCCA_CURRADDR_MASK 0x00ffffff
439#define CCCA_CURRADDR 0x18000008
440
441#define CCR 0x09
442#define CCR_CACHEINVALIDSIZE 0x07190009
443#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000
444#define CCR_CACHELOOPFLAG 0x01000000
445#define CCR_INTERLEAVEDSAMPLES 0x00800000
446#define CCR_WORDSIZEDSAMPLES 0x00400000
447#define CCR_READADDRESS 0x06100009
448#define CCR_READADDRESS_MASK 0x003f0000
449#define CCR_LOOPINVALSIZE 0x0000fe00
450
451#define CCR_LOOPFLAG 0x00000100
452#define CCR_CACHELOOPADDRHI 0x000000ff
453
454#define CLP 0x0a
455
456#define CLP_CACHELOOPADDR 0x0000ffff
457
458#define FXRT 0x0b
459
460
461#define FXRT_CHANNELA 0x000f0000
462#define FXRT_CHANNELB 0x00f00000
463#define FXRT_CHANNELC 0x0f000000
464#define FXRT_CHANNELD 0xf0000000
465
466#define A_HR 0x0b
467#define MAPA 0x0c
468
469#define MAPB 0x0d
470
471#define MAP_PTE_MASK 0xffffe000
472#define MAP_PTI_MASK 0x00001fff
473
474
475
476#define ENVVOL 0x10
477#define ENVVOL_MASK 0x0000ffff
478
479
480#define ATKHLDV 0x11
481#define ATKHLDV_PHASE0 0x00008000
482#define ATKHLDV_HOLDTIME_MASK 0x00007f00
483#define ATKHLDV_ATTACKTIME_MASK 0x0000007f
484
485
486#define DCYSUSV 0x12
487#define DCYSUSV_PHASE1_MASK 0x00008000
488#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00
489#define DCYSUSV_CHANNELENABLE_MASK 0x00000080
490
491
492#define DCYSUSV_DECAYTIME_MASK 0x0000007f
493
494
495#define LFOVAL1 0x13
496#define LFOVAL_MASK 0x0000ffff
497
498
499#define ENVVAL 0x14
500#define ENVVAL_MASK 0x0000ffff
501
502
503#define ATKHLDM 0x15
504#define ATKHLDM_PHASE0 0x00008000
505#define ATKHLDM_HOLDTIME 0x00007f00
506#define ATKHLDM_ATTACKTIME 0x0000007f
507
508
509#define DCYSUSM 0x16
510#define DCYSUSM_PHASE1_MASK 0x00008000
511#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00
512#define DCYSUSM_DECAYTIME_MASK 0x0000007f
513
514
515#define LFOVAL2 0x17
516#define LFOVAL2_MASK 0x0000ffff
517
518
519#define IP 0x18
520#define IP_MASK 0x0000ffff
521
522#define IP_UNITY 0x0000e000
523
524#define IFATN 0x19
525#define IFATN_FILTERCUTOFF_MASK 0x0000ff00
526
527
528#define IFATN_FILTERCUTOFF 0x08080019
529#define IFATN_ATTENUATION_MASK 0x000000ff
530#define IFATN_ATTENUATION 0x08000019
531
532
533#define PEFE 0x1a
534#define PEFE_PITCHAMOUNT_MASK 0x0000ff00
535
536#define PEFE_PITCHAMOUNT 0x0808001a
537#define PEFE_FILTERAMOUNT_MASK 0x000000ff
538
539#define PEFE_FILTERAMOUNT 0x0800001a
540#define FMMOD 0x1b
541#define FMMOD_MODVIBRATO 0x0000ff00
542
543#define FMMOD_MOFILTER 0x000000ff
544
545
546
547#define TREMFRQ 0x1c
548#define TREMFRQ_DEPTH 0x0000ff00
549
550
551#define TREMFRQ_FREQUENCY 0x000000ff
552
553#define FM2FRQ2 0x1d
554#define FM2FRQ2_DEPTH 0x0000ff00
555
556#define FM2FRQ2_FREQUENCY 0x000000ff
557
558
559#define TEMPENV 0x1e
560#define TEMPENV_MASK 0x0000ffff
561
562
563
564
565
566#define CD0 0x20
567#define CD1 0x21
568#define CD2 0x22
569#define CD3 0x23
570#define CD4 0x24
571#define CD5 0x25
572#define CD6 0x26
573#define CD7 0x27
574#define CD8 0x28
575#define CD9 0x29
576#define CDA 0x2a
577#define CDB 0x2b
578#define CDC 0x2c
579#define CDD 0x2d
580#define CDE 0x2e
581#define CDF 0x2f
582
583
584
585#define PTB 0x40
586#define PTB_MASK 0xfffff000
587
588#define TCB 0x41
589#define TCB_MASK 0xfffff000
590
591#define ADCCR 0x42
592#define ADCCR_RCHANENABLE 0x00000010
593#define ADCCR_LCHANENABLE 0x00000008
594
595
596#define A_ADCCR_RCHANENABLE 0x00000020
597#define A_ADCCR_LCHANENABLE 0x00000010
598
599#define A_ADCCR_SAMPLERATE_MASK 0x0000000F
600#define ADCCR_SAMPLERATE_MASK 0x00000007
601#define ADCCR_SAMPLERATE_48 0x00000000
602#define ADCCR_SAMPLERATE_44 0x00000001
603#define ADCCR_SAMPLERATE_32 0x00000002
604#define ADCCR_SAMPLERATE_24 0x00000003
605#define ADCCR_SAMPLERATE_22 0x00000004
606#define ADCCR_SAMPLERATE_16 0x00000005
607#define ADCCR_SAMPLERATE_11 0x00000006
608#define ADCCR_SAMPLERATE_8 0x00000007
609#define A_ADCCR_SAMPLERATE_12 0x00000006
610#define A_ADCCR_SAMPLERATE_11 0x00000007
611#define A_ADCCR_SAMPLERATE_8 0x00000008
612
613#define FXWC 0x43
614
615
616
617
618
619
620#define FXWC_DEFAULTROUTE_C (1<<0)
621#define FXWC_DEFAULTROUTE_B (1<<1)
622#define FXWC_DEFAULTROUTE_A (1<<12)
623#define FXWC_DEFAULTROUTE_D (1<<13)
624#define FXWC_ADCLEFT (1<<18)
625#define FXWC_CDROMSPDIFLEFT (1<<18)
626#define FXWC_ADCRIGHT (1<<19)
627#define FXWC_CDROMSPDIFRIGHT (1<<19)
628#define FXWC_MIC (1<<20)
629#define FXWC_ZOOMLEFT (1<<20)
630#define FXWC_ZOOMRIGHT (1<<21)
631#define FXWC_SPDIFLEFT (1<<22)
632#define FXWC_SPDIFRIGHT (1<<23)
633
634#define A_TBLSZ 0x43
635
636#define TCBS 0x44
637#define TCBS_MASK 0x00000007
638#define TCBS_BUFFSIZE_16K 0x00000000
639#define TCBS_BUFFSIZE_32K 0x00000001
640#define TCBS_BUFFSIZE_64K 0x00000002
641#define TCBS_BUFFSIZE_128K 0x00000003
642#define TCBS_BUFFSIZE_256K 0x00000004
643#define TCBS_BUFFSIZE_512K 0x00000005
644#define TCBS_BUFFSIZE_1024K 0x00000006
645#define TCBS_BUFFSIZE_2048K 0x00000007
646
647#define MICBA 0x45
648#define MICBA_MASK 0xfffff000
649
650#define ADCBA 0x46
651#define ADCBA_MASK 0xfffff000
652
653#define FXBA 0x47
654#define FXBA_MASK 0xfffff000
655
656#define A_HWM 0x48
657
658#define MICBS 0x49
659
660#define ADCBS 0x4a
661
662#define FXBS 0x4b
663
664
665
666
667#define ADCBS_BUFSIZE_NONE 0x00000000
668#define ADCBS_BUFSIZE_384 0x00000001
669#define ADCBS_BUFSIZE_448 0x00000002
670#define ADCBS_BUFSIZE_512 0x00000003
671#define ADCBS_BUFSIZE_640 0x00000004
672#define ADCBS_BUFSIZE_768 0x00000005
673#define ADCBS_BUFSIZE_896 0x00000006
674#define ADCBS_BUFSIZE_1024 0x00000007
675#define ADCBS_BUFSIZE_1280 0x00000008
676#define ADCBS_BUFSIZE_1536 0x00000009
677#define ADCBS_BUFSIZE_1792 0x0000000a
678#define ADCBS_BUFSIZE_2048 0x0000000b
679#define ADCBS_BUFSIZE_2560 0x0000000c
680#define ADCBS_BUFSIZE_3072 0x0000000d
681#define ADCBS_BUFSIZE_3584 0x0000000e
682#define ADCBS_BUFSIZE_4096 0x0000000f
683#define ADCBS_BUFSIZE_5120 0x00000010
684#define ADCBS_BUFSIZE_6144 0x00000011
685#define ADCBS_BUFSIZE_7168 0x00000012
686#define ADCBS_BUFSIZE_8192 0x00000013
687#define ADCBS_BUFSIZE_10240 0x00000014
688#define ADCBS_BUFSIZE_12288 0x00000015
689#define ADCBS_BUFSIZE_14366 0x00000016
690#define ADCBS_BUFSIZE_16384 0x00000017
691#define ADCBS_BUFSIZE_20480 0x00000018
692#define ADCBS_BUFSIZE_24576 0x00000019
693#define ADCBS_BUFSIZE_28672 0x0000001a
694#define ADCBS_BUFSIZE_32768 0x0000001b
695#define ADCBS_BUFSIZE_40960 0x0000001c
696#define ADCBS_BUFSIZE_49152 0x0000001d
697#define ADCBS_BUFSIZE_57344 0x0000001e
698#define ADCBS_BUFSIZE_65536 0x0000001f
699
700
701#define A_CSBA 0x4c
702
703
704#define A_CSDC 0x4d
705
706
707#define A_CSFE 0x4e
708
709
710#define A_CSHG 0x4f
711
712
713#define CDCS 0x50
714
715#define GPSCS 0x51
716
717#define DBG 0x52
718
719
720#define A_SPSC 0x52
721
722#define REG53 0x53
723
724#define A_DBG 0x53
725#define A_DBG_SINGLE_STEP 0x00020000
726#define A_DBG_ZC 0x40000000
727#define A_DBG_STEP_ADDR 0x000003ff
728#define A_DBG_SATURATION_OCCURED 0x20000000
729#define A_DBG_SATURATION_ADDR 0x0ffc0000
730
731
732#define SPCS0 0x54
733
734#define SPCS1 0x55
735
736#define SPCS2 0x56
737
738#define SPCS_CLKACCYMASK 0x30000000
739#define SPCS_CLKACCY_1000PPM 0x00000000
740#define SPCS_CLKACCY_50PPM 0x10000000
741#define SPCS_CLKACCY_VARIABLE 0x20000000
742#define SPCS_SAMPLERATEMASK 0x0f000000
743#define SPCS_SAMPLERATE_44 0x00000000
744#define SPCS_SAMPLERATE_48 0x02000000
745#define SPCS_SAMPLERATE_32 0x03000000
746#define SPCS_CHANNELNUMMASK 0x00f00000
747#define SPCS_CHANNELNUM_UNSPEC 0x00000000
748#define SPCS_CHANNELNUM_LEFT 0x00100000
749#define SPCS_CHANNELNUM_RIGHT 0x00200000
750#define SPCS_SOURCENUMMASK 0x000f0000
751#define SPCS_SOURCENUM_UNSPEC 0x00000000
752#define SPCS_GENERATIONSTATUS 0x00008000
753#define SPCS_CATEGORYCODEMASK 0x00007f00
754#define SPCS_MODEMASK 0x000000c0
755#define SPCS_EMPHASISMASK 0x00000038
756#define SPCS_EMPHASIS_NONE 0x00000000
757#define SPCS_EMPHASIS_50_15 0x00000008
758#define SPCS_COPYRIGHT 0x00000004
759#define SPCS_NOTAUDIODATA 0x00000002
760#define SPCS_PROFESSIONAL 0x00000001
761
762
763
764
765#define CLIEL 0x58
766
767#define CLIEH 0x59
768
769#define CLIPL 0x5a
770
771#define CLIPH 0x5b
772
773#define SOLEL 0x5c
774
775#define SOLEH 0x5d
776
777#define SPBYPASS 0x5e
778#define SPBYPASS_SPDIF0_MASK 0x00000003
779#define SPBYPASS_SPDIF1_MASK 0x0000000c
780
781#define SPBYPASS_FORMAT 0x00000f00
782
783#define AC97SLOT 0x5f
784#define AC97SLOT_REAR_RIGHT 0x01
785#define AC97SLOT_REAR_LEFT 0x02
786#define AC97SLOT_CNTR 0x10
787#define AC97SLOT_LFE 0x20
788
789
790#define A_PCB 0x5f
791
792
793#define CDSRCS 0x60
794
795#define GPSRCS 0x61
796
797#define ZVSRCS 0x62
798
799
800
801
802#define SRCS_SPDIFVALID 0x04000000
803#define SRCS_SPDIFLOCKED 0x02000000
804#define SRCS_RATELOCKED 0x01000000
805#define SRCS_ESTSAMPLERATE 0x0007ffff
806
807
808#define SRCS_SPDIFRATE_44 0x0003acd9
809#define SRCS_SPDIFRATE_48 0x00040000
810#define SRCS_SPDIFRATE_96 0x00080000
811
812#define MICIDX 0x63
813#define MICIDX_MASK 0x0000ffff
814#define MICIDX_IDX 0x10000063
815
816#define ADCIDX 0x64
817#define ADCIDX_MASK 0x0000ffff
818#define ADCIDX_IDX 0x10000064
819
820#define A_ADCIDX 0x63
821#define A_ADCIDX_IDX 0x10000063
822
823#define A_MICIDX 0x64
824#define A_MICIDX_IDX 0x10000064
825
826#define FXIDX 0x65
827#define FXIDX_MASK 0x0000ffff
828#define FXIDX_IDX 0x10000065
829
830
831#define HLIEL 0x66
832
833#define HLIEH 0x67
834
835#define HLIPL 0x68
836
837#define HLIPH 0x69
838
839
840#define A_SPRI 0x6a
841
842#define A_SPRA 0x6b
843
844#define A_SPRC 0x6c
845
846#define A_DICE 0x6d
847
848#define A_TTB 0x6e
849
850#define A_TDOF 0x6f
851
852
853#define A_MUDATA1 0x70
854#define A_MUCMD1 0x71
855#define A_MUSTAT1 A_MUCMD1
856
857
858#define A_MUDATA2 0x72
859#define A_MUCMD2 0x73
860#define A_MUSTAT2 A_MUCMD2
861
862
863
864
865#define A_FXWC1 0x74
866#define A_FXWC2 0x75
867
868
869#define A_SPDIF_SAMPLERATE 0x76
870#define A_SAMPLE_RATE 0x76
871#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e
872#define A_SAMPLE_RATE_UNKNOWN 0xf0030001
873#define A_SPDIF_RATE_MASK 0x000000e0
874#define A_SPDIF_48000 0x00000000
875#define A_SPDIF_192000 0x00000020
876#define A_SPDIF_96000 0x00000040
877#define A_SPDIF_44100 0x00000080
878
879#define A_I2S_CAPTURE_RATE_MASK 0x00000e00
880#define A_I2S_CAPTURE_48000 0x00000000
881#define A_I2S_CAPTURE_192000 0x00000200
882#define A_I2S_CAPTURE_96000 0x00000400
883#define A_I2S_CAPTURE_44100 0x00000800
884
885#define A_PCM_RATE_MASK 0x0000e000
886#define A_PCM_48000 0x00000000
887#define A_PCM_192000 0x00002000
888#define A_PCM_96000 0x00004000
889#define A_PCM_44100 0x00008000
890
891
892#define A_SRT3 0x77
893
894
895#define A_SRT4 0x78
896
897
898#define A_SRT5 0x79
899
900
901
902#define A_TTDA 0x7a
903
904#define A_TTDD 0x7b
905
906#define A_FXRT2 0x7c
907#define A_FXRT_CHANNELE 0x0000003f
908#define A_FXRT_CHANNELF 0x00003f00
909#define A_FXRT_CHANNELG 0x003f0000
910#define A_FXRT_CHANNELH 0x3f000000
911
912#define A_SENDAMOUNTS 0x7d
913#define A_FXSENDAMOUNT_E_MASK 0xFF000000
914#define A_FXSENDAMOUNT_F_MASK 0x00FF0000
915#define A_FXSENDAMOUNT_G_MASK 0x0000FF00
916#define A_FXSENDAMOUNT_H_MASK 0x000000FF
917
918
919
920#define A_FXRT1 0x7e
921#define A_FXRT_CHANNELA 0x0000003f
922#define A_FXRT_CHANNELB 0x00003f00
923#define A_FXRT_CHANNELC 0x003f0000
924#define A_FXRT_CHANNELD 0x3f000000
925
926
927
928#define FXGPREGBASE 0x100
929#define A_FXGPREGBASE 0x400
930
931#define A_TANKMEMCTLREGBASE 0x100
932#define A_TANKMEMCTLREG_MASK 0x1f
933
934
935
936
937#define TANKMEMDATAREGBASE 0x200
938#define TANKMEMDATAREG_MASK 0x000fffff
939
940
941#define TANKMEMADDRREGBASE 0x300
942#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
943#define TANKMEMADDRREG_CLEAR 0x00800000
944#define TANKMEMADDRREG_ALIGN 0x00400000
945#define TANKMEMADDRREG_WRITE 0x00200000
946#define TANKMEMADDRREG_READ 0x00100000
947
948#define MICROCODEBASE 0x400
949
950
951
952#define LOWORD_OPX_MASK 0x000ffc00
953#define LOWORD_OPY_MASK 0x000003ff
954#define HIWORD_OPCODE_MASK 0x00f00000
955#define HIWORD_RESULT_MASK 0x000ffc00
956#define HIWORD_OPA_MASK 0x000003ff
957
958
959
960#define A_MICROCODEBASE 0x600
961#define A_LOWORD_OPY_MASK 0x000007ff
962#define A_LOWORD_OPX_MASK 0x007ff000
963#define A_HIWORD_OPCODE_MASK 0x0f000000
964#define A_HIWORD_RESULT_MASK 0x007ff000
965#define A_HIWORD_OPA_MASK 0x000007ff
966
967
968
969
970#define EMU_HANA_DESTHI 0x00
971#define EMU_HANA_DESTLO 0x01
972#define EMU_HANA_SRCHI 0x02
973#define EMU_HANA_SRCLO 0x03
974#define EMU_HANA_DOCK_PWR 0x04
975#define EMU_HANA_DOCK_PWR_ON 0x01
976#define EMU_HANA_WCLOCK 0x05
977
978
979#define EMU_HANA_WCLOCK_SRC_MASK 0x07
980#define EMU_HANA_WCLOCK_INT_48K 0x00
981#define EMU_HANA_WCLOCK_INT_44_1K 0x01
982#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
983#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
984#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
985#define EMU_HANA_WCLOCK_2ND_HANA 0x05
986#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
987#define EMU_HANA_WCLOCK_OFF 0x07
988#define EMU_HANA_WCLOCK_MULT_MASK 0x18
989#define EMU_HANA_WCLOCK_1X 0x00
990#define EMU_HANA_WCLOCK_2X 0x08
991#define EMU_HANA_WCLOCK_4X 0x10
992#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
993
994#define EMU_HANA_DEFCLOCK 0x06
995#define EMU_HANA_DEFCLOCK_48K 0x00
996#define EMU_HANA_DEFCLOCK_44_1K 0x01
997
998#define EMU_HANA_UNMUTE 0x07
999#define EMU_MUTE 0x00
1000#define EMU_UNMUTE 0x01
1001
1002#define EMU_HANA_FPGA_CONFIG 0x08
1003#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01
1004#define EMU_HANA_FPGA_CONFIG_HANA 0x02
1005
1006#define EMU_HANA_IRQ_ENABLE 0x09
1007#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1008#define EMU_HANA_IRQ_ADAT 0x02
1009#define EMU_HANA_IRQ_DOCK 0x04
1010#define EMU_HANA_IRQ_DOCK_LOST 0x08
1011
1012#define EMU_HANA_SPDIF_MODE 0x0a
1013#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
1014#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1015#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1016#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
1017#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1018#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1019#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1020
1021#define EMU_HANA_OPTICAL_TYPE 0x0b
1022#define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1023#define EMU_HANA_OPTICAL_IN_ADAT 0x01
1024#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1025#define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1026
1027#define EMU_HANA_MIDI_IN 0x0c
1028#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00
1029#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01
1030
1031#define EMU_HANA_DOCK_LEDS_1 0x0d
1032#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01
1033#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02
1034#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04
1035#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08
1036
1037#define EMU_HANA_DOCK_LEDS_2 0x0e
1038#define EMU_HANA_DOCK_LEDS_2_44K 0x01
1039#define EMU_HANA_DOCK_LEDS_2_48K 0x02
1040#define EMU_HANA_DOCK_LEDS_2_96K 0x04
1041#define EMU_HANA_DOCK_LEDS_2_192K 0x08
1042#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10
1043#define EMU_HANA_DOCK_LEDS_2_EXT 0x20
1044
1045#define EMU_HANA_DOCK_LEDS_3 0x0f
1046#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01
1047#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02
1048#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04
1049#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08
1050#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10
1051#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20
1052
1053#define EMU_HANA_ADC_PADS 0x10
1054#define EMU_HANA_DOCK_ADC_PAD1 0x01
1055#define EMU_HANA_DOCK_ADC_PAD2 0x02
1056#define EMU_HANA_DOCK_ADC_PAD3 0x04
1057#define EMU_HANA_0202_ADC_PAD1 0x08
1058
1059#define EMU_HANA_DOCK_MISC 0x11
1060#define EMU_HANA_DOCK_DAC1_MUTE 0x01
1061#define EMU_HANA_DOCK_DAC2_MUTE 0x02
1062#define EMU_HANA_DOCK_DAC3_MUTE 0x04
1063#define EMU_HANA_DOCK_DAC4_MUTE 0x08
1064#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00
1065#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10
1066#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20
1067#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30
1068
1069#define EMU_HANA_MIDI_OUT 0x12
1070#define EMU_HANA_MIDI_OUT_0202 0x01
1071#define EMU_HANA_MIDI_OUT_DOCK1 0x02
1072#define EMU_HANA_MIDI_OUT_DOCK2 0x04
1073#define EMU_HANA_MIDI_OUT_SYNC2 0x08
1074#define EMU_HANA_MIDI_OUT_LOOP 0x10
1075
1076#define EMU_HANA_DAC_PADS 0x13
1077#define EMU_HANA_DOCK_DAC_PAD1 0x01
1078#define EMU_HANA_DOCK_DAC_PAD2 0x02
1079#define EMU_HANA_DOCK_DAC_PAD3 0x04
1080#define EMU_HANA_DOCK_DAC_PAD4 0x08
1081#define EMU_HANA_0202_DAC_PAD1 0x10
1082
1083
1084#define EMU_HANA_IRQ_STATUS 0x20
1085#if 0
1086#define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1087#define EMU_HANA_IRQ_ADAT 0x02
1088#define EMU_HANA_IRQ_DOCK 0x04
1089#define EMU_HANA_IRQ_DOCK_LOST 0x08
1090#endif
1091
1092#define EMU_HANA_OPTION_CARDS 0x21
1093#define EMU_HANA_OPTION_HAMOA 0x01
1094#define EMU_HANA_OPTION_SYNC 0x02
1095#define EMU_HANA_OPTION_DOCK_ONLINE 0x04
1096#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08
1097
1098#define EMU_HANA_ID 0x22
1099
1100#define EMU_HANA_MAJOR_REV 0x23
1101#define EMU_HANA_MINOR_REV 0x24
1102
1103#define EMU_DOCK_MAJOR_REV 0x25
1104#define EMU_DOCK_MINOR_REV 0x26
1105
1106#define EMU_DOCK_BOARD_ID 0x27
1107#define EMU_DOCK_BOARD_ID0 0x00
1108#define EMU_DOCK_BOARD_ID1 0x03
1109
1110#define EMU_HANA_WC_SPDIF_HI 0x28
1111#define EMU_HANA_WC_SPDIF_LO 0x29
1112
1113#define EMU_HANA_WC_ADAT_HI 0x2a
1114#define EMU_HANA_WC_ADAT_LO 0x2b
1115
1116#define EMU_HANA_WC_BNC_LO 0x2c
1117#define EMU_HANA_WC_BNC_HI 0x2d
1118
1119#define EMU_HANA2_WC_SPDIF_HI 0x2e
1120#define EMU_HANA2_WC_SPDIF_LO 0x2f
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229#define EMU_DST_ALICE2_EMU32_0 0x000f
1230#define EMU_DST_ALICE2_EMU32_1 0x0000
1231#define EMU_DST_ALICE2_EMU32_2 0x0001
1232#define EMU_DST_ALICE2_EMU32_3 0x0002
1233#define EMU_DST_ALICE2_EMU32_4 0x0003
1234#define EMU_DST_ALICE2_EMU32_5 0x0004
1235#define EMU_DST_ALICE2_EMU32_6 0x0005
1236#define EMU_DST_ALICE2_EMU32_7 0x0006
1237#define EMU_DST_ALICE2_EMU32_8 0x0007
1238#define EMU_DST_ALICE2_EMU32_9 0x0008
1239#define EMU_DST_ALICE2_EMU32_A 0x0009
1240#define EMU_DST_ALICE2_EMU32_B 0x000a
1241#define EMU_DST_ALICE2_EMU32_C 0x000b
1242#define EMU_DST_ALICE2_EMU32_D 0x000c
1243#define EMU_DST_ALICE2_EMU32_E 0x000d
1244#define EMU_DST_ALICE2_EMU32_F 0x000e
1245#define EMU_DST_DOCK_DAC1_LEFT1 0x0100
1246#define EMU_DST_DOCK_DAC1_LEFT2 0x0101
1247#define EMU_DST_DOCK_DAC1_LEFT3 0x0102
1248#define EMU_DST_DOCK_DAC1_LEFT4 0x0103
1249#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104
1250#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105
1251#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106
1252#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107
1253#define EMU_DST_DOCK_DAC2_LEFT1 0x0108
1254#define EMU_DST_DOCK_DAC2_LEFT2 0x0109
1255#define EMU_DST_DOCK_DAC2_LEFT3 0x010a
1256#define EMU_DST_DOCK_DAC2_LEFT4 0x010b
1257#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c
1258#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d
1259#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e
1260#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f
1261#define EMU_DST_DOCK_DAC3_LEFT1 0x0110
1262#define EMU_DST_DOCK_DAC3_LEFT2 0x0111
1263#define EMU_DST_DOCK_DAC3_LEFT3 0x0112
1264#define EMU_DST_DOCK_DAC3_LEFT4 0x0113
1265#define EMU_DST_DOCK_PHONES_LEFT1 0x0112
1266#define EMU_DST_DOCK_PHONES_LEFT2 0x0113
1267#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114
1268#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115
1269#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116
1270#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117
1271#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116
1272#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117
1273#define EMU_DST_DOCK_DAC4_LEFT1 0x0118
1274#define EMU_DST_DOCK_DAC4_LEFT2 0x0119
1275#define EMU_DST_DOCK_DAC4_LEFT3 0x011a
1276#define EMU_DST_DOCK_DAC4_LEFT4 0x011b
1277#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a
1278#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b
1279#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c
1280#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d
1281#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e
1282#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f
1283#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e
1284#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f
1285#define EMU_DST_HANA_SPDIF_LEFT1 0x0200
1286#define EMU_DST_HANA_SPDIF_LEFT2 0x0202
1287#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201
1288#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203
1289#define EMU_DST_HAMOA_DAC_LEFT1 0x0300
1290#define EMU_DST_HAMOA_DAC_LEFT2 0x0302
1291#define EMU_DST_HAMOA_DAC_LEFT3 0x0304
1292#define EMU_DST_HAMOA_DAC_LEFT4 0x0306
1293#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301
1294#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303
1295#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305
1296#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307
1297#define EMU_DST_HANA_ADAT 0x0400
1298#define EMU_DST_ALICE_I2S0_LEFT 0x0500
1299#define EMU_DST_ALICE_I2S0_RIGHT 0x0501
1300#define EMU_DST_ALICE_I2S1_LEFT 0x0600
1301#define EMU_DST_ALICE_I2S1_RIGHT 0x0601
1302#define EMU_DST_ALICE_I2S2_LEFT 0x0700
1303#define EMU_DST_ALICE_I2S2_RIGHT 0x0701
1304
1305
1306
1307#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
1308
1309#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
1310
1311#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
1312
1313#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
1314
1315#define EMU_DST_MDOCK_ADAT 0x0118
1316
1317
1318#define EMU_DST_MANA_DAC_LEFT 0x0300
1319
1320#define EMU_DST_MANA_DAC_RIGHT 0x0301
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427#define EMU_SRC_SILENCE 0x0000
1428#define EMU_SRC_DOCK_MIC_A1 0x0100
1429#define EMU_SRC_DOCK_MIC_A2 0x0101
1430#define EMU_SRC_DOCK_MIC_A3 0x0102
1431#define EMU_SRC_DOCK_MIC_A4 0x0103
1432#define EMU_SRC_DOCK_MIC_B1 0x0104
1433#define EMU_SRC_DOCK_MIC_B2 0x0105
1434#define EMU_SRC_DOCK_MIC_B3 0x0106
1435#define EMU_SRC_DOCK_MIC_B4 0x0107
1436#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108
1437#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109
1438#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a
1439#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b
1440#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c
1441#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d
1442#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e
1443#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f
1444#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110
1445#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111
1446#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112
1447#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113
1448#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114
1449#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115
1450#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116
1451#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117
1452#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118
1453#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119
1454#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a
1455#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b
1456#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c
1457#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d
1458#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e
1459#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f
1460#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200
1461#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202
1462#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204
1463#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206
1464#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201
1465#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203
1466#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205
1467#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207
1468#define EMU_SRC_ALICE_EMU32A 0x0300
1469#define EMU_SRC_ALICE_EMU32B 0x0310
1470#define EMU_SRC_HANA_ADAT 0x0400
1471#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500
1472#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502
1473#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501
1474#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503
1475
1476
1477
1478#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
1479
1480#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
1481
1482#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
1483
1484#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
1485
1486#define EMU_SRC_MDOCK_ADAT 0x0118
1487
1488
1489
1490
1491
1492enum {
1493 EMU10K1_EFX,
1494 EMU10K1_PCM,
1495 EMU10K1_SYNTH,
1496 EMU10K1_MIDI
1497};
1498
1499struct snd_emu10k1;
1500
1501struct snd_emu10k1_voice {
1502 struct snd_emu10k1 *emu;
1503 int number;
1504 unsigned int use: 1,
1505 pcm: 1,
1506 efx: 1,
1507 synth: 1,
1508 midi: 1;
1509 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1510
1511 struct snd_emu10k1_pcm *epcm;
1512};
1513
1514enum {
1515 PLAYBACK_EMUVOICE,
1516 PLAYBACK_EFX,
1517 CAPTURE_AC97ADC,
1518 CAPTURE_AC97MIC,
1519 CAPTURE_EFX
1520};
1521
1522struct snd_emu10k1_pcm {
1523 struct snd_emu10k1 *emu;
1524 int type;
1525 struct snd_pcm_substream *substream;
1526 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1527 struct snd_emu10k1_voice *extra;
1528 unsigned short running;
1529 unsigned short first_ptr;
1530 struct snd_util_memblk *memblk;
1531 unsigned int start_addr;
1532 unsigned int ccca_start_addr;
1533 unsigned int capture_ipr;
1534 unsigned int capture_inte;
1535 unsigned int capture_ba_reg;
1536 unsigned int capture_bs_reg;
1537 unsigned int capture_idx_reg;
1538 unsigned int capture_cr_val;
1539 unsigned int capture_cr_val2;
1540 unsigned int capture_bs_val;
1541 unsigned int capture_bufsize;
1542};
1543
1544struct snd_emu10k1_pcm_mixer {
1545
1546 unsigned char send_routing[3][8];
1547 unsigned char send_volume[3][8];
1548 unsigned short attn[3];
1549 struct snd_emu10k1_pcm *epcm;
1550};
1551
1552#define snd_emu10k1_compose_send_routing(route) \
1553((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1554
1555#define snd_emu10k1_compose_audigy_fxrt1(route) \
1556((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1557
1558#define snd_emu10k1_compose_audigy_fxrt2(route) \
1559((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1560
1561struct snd_emu10k1_memblk {
1562 struct snd_util_memblk mem;
1563
1564 int first_page, last_page, pages, mapped_page;
1565 unsigned int map_locked;
1566 struct list_head mapped_link;
1567 struct list_head mapped_order_link;
1568};
1569
1570#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1571
1572#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1573
1574struct snd_emu10k1_fx8010_ctl {
1575 struct list_head list;
1576 unsigned int vcount;
1577 unsigned int count;
1578 unsigned short gpr[32];
1579 unsigned int value[32];
1580 unsigned int min;
1581 unsigned int max;
1582 unsigned int translation;
1583 struct snd_kcontrol *kcontrol;
1584};
1585
1586typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1587
1588struct snd_emu10k1_fx8010_irq {
1589 struct snd_emu10k1_fx8010_irq *next;
1590 snd_fx8010_irq_handler_t *handler;
1591 unsigned short gpr_running;
1592 void *private_data;
1593};
1594
1595struct snd_emu10k1_fx8010_pcm {
1596 unsigned int valid: 1,
1597 opened: 1,
1598 active: 1;
1599 unsigned int channels;
1600 unsigned int tram_start;
1601 unsigned int buffer_size;
1602 unsigned short gpr_size;
1603 unsigned short gpr_ptr;
1604 unsigned short gpr_count;
1605 unsigned short gpr_tmpcount;
1606 unsigned short gpr_trigger;
1607 unsigned short gpr_running;
1608 unsigned char etram[32];
1609 struct snd_pcm_indirect pcm_rec;
1610 unsigned int tram_pos;
1611 unsigned int tram_shift;
1612 struct snd_emu10k1_fx8010_irq *irq;
1613};
1614
1615struct snd_emu10k1_fx8010 {
1616 unsigned short fxbus_mask;
1617 unsigned short extin_mask;
1618 unsigned short extout_mask;
1619 unsigned short pad1;
1620 unsigned int itram_size;
1621 struct snd_dma_buffer etram_pages;
1622 unsigned int dbg;
1623 unsigned char name[128];
1624 int gpr_size;
1625 int gpr_count;
1626 struct list_head gpr_ctl;
1627 struct mutex lock;
1628 struct snd_emu10k1_fx8010_pcm pcm[8];
1629 spinlock_t irq_lock;
1630 struct snd_emu10k1_fx8010_irq *irq_handlers;
1631};
1632
1633struct snd_emu10k1_midi {
1634 struct snd_emu10k1 *emu;
1635 struct snd_rawmidi *rmidi;
1636 struct snd_rawmidi_substream *substream_input;
1637 struct snd_rawmidi_substream *substream_output;
1638 unsigned int midi_mode;
1639 spinlock_t input_lock;
1640 spinlock_t output_lock;
1641 spinlock_t open_lock;
1642 int tx_enable, rx_enable;
1643 int port;
1644 int ipr_tx, ipr_rx;
1645 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1646};
1647
1648enum {
1649 EMU_MODEL_SB,
1650 EMU_MODEL_EMU1010,
1651 EMU_MODEL_EMU1010B,
1652 EMU_MODEL_EMU1616,
1653 EMU_MODEL_EMU0404,
1654};
1655
1656struct snd_emu_chip_details {
1657 u32 vendor;
1658 u32 device;
1659 u32 subsystem;
1660 unsigned char revision;
1661 unsigned char emu10k1_chip;
1662 unsigned char emu10k2_chip;
1663 unsigned char ca0102_chip;
1664 unsigned char ca0108_chip;
1665 unsigned char ca_cardbus_chip;
1666 unsigned char ca0151_chip;
1667 unsigned char spk71;
1668 unsigned char sblive51;
1669 unsigned char spdif_bug;
1670 unsigned char ac97_chip;
1671 unsigned char ecard;
1672 unsigned char emu_model;
1673 unsigned char spi_dac;
1674 unsigned char i2c_adc;
1675 unsigned char adc_1361t;
1676 unsigned char invert_shared_spdif;
1677 const char *driver;
1678 const char *name;
1679 const char *id;
1680};
1681
1682struct snd_emu1010 {
1683 unsigned int output_source[64];
1684 unsigned int input_source[64];
1685 unsigned int adc_pads;
1686 unsigned int dac_pads;
1687 unsigned int internal_clock;
1688 unsigned int optical_in;
1689 unsigned int optical_out;
1690 struct task_struct *firmware_thread;
1691};
1692
1693struct snd_emu10k1 {
1694 int irq;
1695
1696 unsigned long port;
1697 unsigned int tos_link: 1,
1698 rear_ac97: 1,
1699 enable_ir: 1;
1700 unsigned int support_tlv :1;
1701
1702 const struct snd_emu_chip_details *card_capabilities;
1703 unsigned int audigy;
1704 unsigned int revision;
1705 unsigned int serial;
1706 unsigned short model;
1707 unsigned int card_type;
1708 unsigned int ecard_ctrl;
1709 unsigned long dma_mask;
1710 int max_cache_pages;
1711 struct snd_dma_buffer silent_page;
1712 struct snd_dma_buffer ptb_pages;
1713 struct snd_dma_device p16v_dma_dev;
1714 struct snd_dma_buffer p16v_buffer;
1715
1716 struct snd_util_memhdr *memhdr;
1717 struct snd_emu10k1_memblk *reserved_page;
1718
1719 struct list_head mapped_link_head;
1720 struct list_head mapped_order_link_head;
1721 void **page_ptr_table;
1722 unsigned long *page_addr_table;
1723 spinlock_t memblk_lock;
1724
1725 unsigned int spdif_bits[3];
1726 unsigned int i2c_capture_source;
1727 u8 i2c_capture_volume[4][2];
1728
1729 struct snd_emu10k1_fx8010 fx8010;
1730 int gpr_base;
1731
1732 struct snd_ac97 *ac97;
1733
1734 struct pci_dev *pci;
1735 struct snd_card *card;
1736 struct snd_pcm *pcm;
1737 struct snd_pcm *pcm_mic;
1738 struct snd_pcm *pcm_efx;
1739 struct snd_pcm *pcm_multi;
1740 struct snd_pcm *pcm_p16v;
1741
1742 spinlock_t synth_lock;
1743 void *synth;
1744 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1745
1746 spinlock_t reg_lock;
1747 spinlock_t emu_lock;
1748 spinlock_t voice_lock;
1749 spinlock_t spi_lock;
1750 spinlock_t i2c_lock;
1751
1752 struct snd_emu10k1_voice voices[NUM_G];
1753 struct snd_emu10k1_voice p16v_voices[4];
1754 struct snd_emu10k1_voice p16v_capture_voice;
1755 int p16v_device_offset;
1756 u32 p16v_capture_source;
1757 u32 p16v_capture_channel;
1758 struct snd_emu1010 emu1010;
1759 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1760 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1761 struct snd_kcontrol *ctl_send_routing;
1762 struct snd_kcontrol *ctl_send_volume;
1763 struct snd_kcontrol *ctl_attn;
1764 struct snd_kcontrol *ctl_efx_send_routing;
1765 struct snd_kcontrol *ctl_efx_send_volume;
1766 struct snd_kcontrol *ctl_efx_attn;
1767
1768 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1769 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1770 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1771 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1772 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1773 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1774
1775 struct snd_pcm_substream *pcm_capture_substream;
1776 struct snd_pcm_substream *pcm_capture_mic_substream;
1777 struct snd_pcm_substream *pcm_capture_efx_substream;
1778 struct snd_pcm_substream *pcm_playback_efx_substream;
1779
1780 struct snd_timer *timer;
1781
1782 struct snd_emu10k1_midi midi;
1783 struct snd_emu10k1_midi midi2;
1784
1785 unsigned int efx_voices_mask[2];
1786 unsigned int next_free_voice;
1787
1788#ifdef CONFIG_PM
1789 unsigned int *saved_ptr;
1790 unsigned int *saved_gpr;
1791 unsigned int *tram_val_saved;
1792 unsigned int *tram_addr_saved;
1793 unsigned int *saved_icode;
1794 unsigned int *p16v_saved;
1795 unsigned int saved_a_iocfg, saved_hcfg;
1796#endif
1797
1798};
1799
1800int snd_emu10k1_create(struct snd_card *card,
1801 struct pci_dev *pci,
1802 unsigned short extin_mask,
1803 unsigned short extout_mask,
1804 long max_cache_bytes,
1805 int enable_ir,
1806 uint subsystem,
1807 struct snd_emu10k1 ** remu);
1808
1809int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1810int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1811int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1812int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1813int snd_p16v_free(struct snd_emu10k1 * emu);
1814int snd_p16v_mixer(struct snd_emu10k1 * emu);
1815int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1816int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
1817int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1818int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1819int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
1820
1821irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1822
1823void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1824int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1825void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1826int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1827int snd_emu10k1_done(struct snd_emu10k1 * emu);
1828
1829
1830unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1831void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1832unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1833void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1834int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1835int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1836int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);
1837int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);
1838int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);
1839unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1840void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1841void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1842void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1843void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1844void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1845void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1846void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1847void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1848void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1849void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1850void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
1851static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1852unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1853void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1854unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1855
1856#ifdef CONFIG_PM
1857void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1858void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1859void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1860int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1861void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1862void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1863void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1864int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1865void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1866void snd_p16v_suspend(struct snd_emu10k1 *emu);
1867void snd_p16v_resume(struct snd_emu10k1 *emu);
1868#endif
1869
1870
1871struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1872int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1873struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1874int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1875int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1876int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1877int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1878
1879
1880int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1881int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1882
1883
1884int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1885int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1886
1887
1888int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1889
1890
1891int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1892 snd_fx8010_irq_handler_t *handler,
1893 unsigned char gpr_running,
1894 void *private_data,
1895 struct snd_emu10k1_fx8010_irq **r_irq);
1896int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1897 struct snd_emu10k1_fx8010_irq *irq);
1898
1899#endif
1900
1901
1902
1903
1904
1905#define EMU10K1_CARD_CREATIVE 0x00000000
1906#define EMU10K1_CARD_EMUAPS 0x00000001
1907
1908#define EMU10K1_FX8010_PCM_COUNT 8
1909
1910
1911#define iMAC0 0x00
1912#define iMAC1 0x01
1913#define iMAC2 0x02
1914#define iMAC3 0x03
1915#define iMACINT0 0x04
1916#define iMACINT1 0x05
1917#define iACC3 0x06
1918#define iMACMV 0x07
1919#define iANDXOR 0x08
1920#define iTSTNEG 0x09
1921#define iLIMITGE 0x0a
1922#define iLIMITLT 0x0b
1923#define iLOG 0x0c
1924#define iEXP 0x0d
1925#define iINTERP 0x0e
1926#define iSKIP 0x0f
1927
1928
1929#define FXBUS(x) (0x00 + (x))
1930#define EXTIN(x) (0x10 + (x))
1931#define EXTOUT(x) (0x20 + (x))
1932#define FXBUS2(x) (0x30 + (x))
1933
1934
1935#define C_00000000 0x40
1936#define C_00000001 0x41
1937#define C_00000002 0x42
1938#define C_00000003 0x43
1939#define C_00000004 0x44
1940#define C_00000008 0x45
1941#define C_00000010 0x46
1942#define C_00000020 0x47
1943#define C_00000100 0x48
1944#define C_00010000 0x49
1945#define C_00080000 0x4a
1946#define C_10000000 0x4b
1947#define C_20000000 0x4c
1948#define C_40000000 0x4d
1949#define C_80000000 0x4e
1950#define C_7fffffff 0x4f
1951#define C_ffffffff 0x50
1952#define C_fffffffe 0x51
1953#define C_c0000000 0x52
1954#define C_4f1bbcdc 0x53
1955#define C_5a7ef9db 0x54
1956#define C_00100000 0x55
1957#define GPR_ACCU 0x56
1958#define GPR_COND 0x57
1959#define GPR_NOISE0 0x58
1960#define GPR_NOISE1 0x59
1961#define GPR_IRQ 0x5a
1962#define GPR_DBAC 0x5b
1963#define GPR(x) (FXGPREGBASE + (x))
1964#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
1965#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x))
1966#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
1967#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x))
1968
1969#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x))
1970#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x))
1971#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x))
1972#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x))
1973#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x))
1974#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x))
1975
1976#define A_FXBUS(x) (0x00 + (x))
1977#define A_EXTIN(x) (0x40 + (x))
1978#define A_P16VIN(x) (0x50 + (x))
1979#define A_EXTOUT(x) (0x60 + (x))
1980#define A_FXBUS2(x) (0x80 + (x))
1981#define A_EMU32OUTH(x) (0xa0 + (x))
1982#define A_EMU32OUTL(x) (0xb0 + (x))
1983#define A3_EMU32IN(x) (0x160 + (x))
1984#define A3_EMU32OUT(x) (0x1E0 + (x))
1985#define A_GPR(x) (A_FXGPREGBASE + (x))
1986
1987
1988#define CC_REG_NORMALIZED C_00000001
1989#define CC_REG_BORROW C_00000002
1990#define CC_REG_MINUS C_00000004
1991#define CC_REG_ZERO C_00000008
1992#define CC_REG_SATURATE C_00000010
1993#define CC_REG_NONZERO C_00000100
1994
1995
1996#define FXBUS_PCM_LEFT 0x00
1997#define FXBUS_PCM_RIGHT 0x01
1998#define FXBUS_PCM_LEFT_REAR 0x02
1999#define FXBUS_PCM_RIGHT_REAR 0x03
2000#define FXBUS_MIDI_LEFT 0x04
2001#define FXBUS_MIDI_RIGHT 0x05
2002#define FXBUS_PCM_CENTER 0x06
2003#define FXBUS_PCM_LFE 0x07
2004#define FXBUS_PCM_LEFT_FRONT 0x08
2005#define FXBUS_PCM_RIGHT_FRONT 0x09
2006#define FXBUS_MIDI_REVERB 0x0c
2007#define FXBUS_MIDI_CHORUS 0x0d
2008#define FXBUS_PCM_LEFT_SIDE 0x0e
2009#define FXBUS_PCM_RIGHT_SIDE 0x0f
2010#define FXBUS_PT_LEFT 0x14
2011#define FXBUS_PT_RIGHT 0x15
2012
2013
2014#define EXTIN_AC97_L 0x00
2015#define EXTIN_AC97_R 0x01
2016#define EXTIN_SPDIF_CD_L 0x02
2017#define EXTIN_SPDIF_CD_R 0x03
2018#define EXTIN_ZOOM_L 0x04
2019#define EXTIN_ZOOM_R 0x05
2020#define EXTIN_TOSLINK_L 0x06
2021#define EXTIN_TOSLINK_R 0x07
2022#define EXTIN_LINE1_L 0x08
2023#define EXTIN_LINE1_R 0x09
2024#define EXTIN_COAX_SPDIF_L 0x0a
2025#define EXTIN_COAX_SPDIF_R 0x0b
2026#define EXTIN_LINE2_L 0x0c
2027#define EXTIN_LINE2_R 0x0d
2028
2029
2030#define EXTOUT_AC97_L 0x00
2031#define EXTOUT_AC97_R 0x01
2032#define EXTOUT_TOSLINK_L 0x02
2033#define EXTOUT_TOSLINK_R 0x03
2034#define EXTOUT_AC97_CENTER 0x04
2035#define EXTOUT_AC97_LFE 0x05
2036#define EXTOUT_HEADPHONE_L 0x06
2037#define EXTOUT_HEADPHONE_R 0x07
2038#define EXTOUT_REAR_L 0x08
2039#define EXTOUT_REAR_R 0x09
2040#define EXTOUT_ADC_CAP_L 0x0a
2041#define EXTOUT_ADC_CAP_R 0x0b
2042#define EXTOUT_MIC_CAP 0x0c
2043#define EXTOUT_AC97_REAR_L 0x0d
2044#define EXTOUT_AC97_REAR_R 0x0e
2045#define EXTOUT_ACENTER 0x11
2046#define EXTOUT_ALFE 0x12
2047
2048
2049#define A_EXTIN_AC97_L 0x00
2050#define A_EXTIN_AC97_R 0x01
2051#define A_EXTIN_SPDIF_CD_L 0x02
2052#define A_EXTIN_SPDIF_CD_R 0x03
2053#define A_EXTIN_OPT_SPDIF_L 0x04
2054#define A_EXTIN_OPT_SPDIF_R 0x05
2055#define A_EXTIN_LINE2_L 0x08
2056#define A_EXTIN_LINE2_R 0x09
2057#define A_EXTIN_ADC_L 0x0a
2058#define A_EXTIN_ADC_R 0x0b
2059#define A_EXTIN_AUX2_L 0x0c
2060#define A_EXTIN_AUX2_R 0x0d
2061
2062
2063#define A_EXTOUT_FRONT_L 0x00
2064#define A_EXTOUT_FRONT_R 0x01
2065#define A_EXTOUT_CENTER 0x02
2066#define A_EXTOUT_LFE 0x03
2067#define A_EXTOUT_HEADPHONE_L 0x04
2068#define A_EXTOUT_HEADPHONE_R 0x05
2069#define A_EXTOUT_REAR_L 0x06
2070#define A_EXTOUT_REAR_R 0x07
2071#define A_EXTOUT_AFRONT_L 0x08
2072#define A_EXTOUT_AFRONT_R 0x09
2073#define A_EXTOUT_ACENTER 0x0a
2074#define A_EXTOUT_ALFE 0x0b
2075#define A_EXTOUT_ASIDE_L 0x0c
2076#define A_EXTOUT_ASIDE_R 0x0d
2077#define A_EXTOUT_AREAR_L 0x0e
2078#define A_EXTOUT_AREAR_R 0x0f
2079#define A_EXTOUT_AC97_L 0x10
2080#define A_EXTOUT_AC97_R 0x11
2081#define A_EXTOUT_ADC_CAP_L 0x16
2082#define A_EXTOUT_ADC_CAP_R 0x17
2083#define A_EXTOUT_MIC_CAP 0x18
2084
2085
2086#define A_C_00000000 0xc0
2087#define A_C_00000001 0xc1
2088#define A_C_00000002 0xc2
2089#define A_C_00000003 0xc3
2090#define A_C_00000004 0xc4
2091#define A_C_00000008 0xc5
2092#define A_C_00000010 0xc6
2093#define A_C_00000020 0xc7
2094#define A_C_00000100 0xc8
2095#define A_C_00010000 0xc9
2096#define A_C_00000800 0xca
2097#define A_C_10000000 0xcb
2098#define A_C_20000000 0xcc
2099#define A_C_40000000 0xcd
2100#define A_C_80000000 0xce
2101#define A_C_7fffffff 0xcf
2102#define A_C_ffffffff 0xd0
2103#define A_C_fffffffe 0xd1
2104#define A_C_c0000000 0xd2
2105#define A_C_4f1bbcdc 0xd3
2106#define A_C_5a7ef9db 0xd4
2107#define A_C_00100000 0xd5
2108#define A_GPR_ACCU 0xd6
2109#define A_GPR_COND 0xd7
2110#define A_GPR_NOISE0 0xd8
2111#define A_GPR_NOISE1 0xd9
2112#define A_GPR_IRQ 0xda
2113#define A_GPR_DBAC 0xdb
2114#define A_GPR_DBACE 0xde
2115
2116
2117#define EMU10K1_DBG_ZC 0x80000000
2118#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000
2119#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000
2120#define EMU10K1_DBG_SINGLE_STEP 0x00008000
2121#define EMU10K1_DBG_STEP 0x00004000
2122#define EMU10K1_DBG_CONDITION_CODE 0x00003e00
2123#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff
2124
2125
2126#ifndef __KERNEL__
2127#define TANKMEMADDRREG_ADDR_MASK 0x000fffff
2128#define TANKMEMADDRREG_CLEAR 0x00800000
2129#define TANKMEMADDRREG_ALIGN 0x00400000
2130#define TANKMEMADDRREG_WRITE 0x00200000
2131#define TANKMEMADDRREG_READ 0x00100000
2132#endif
2133
2134struct snd_emu10k1_fx8010_info {
2135 unsigned int internal_tram_size;
2136 unsigned int external_tram_size;
2137 char fxbus_names[16][32];
2138 char extin_names[16][32];
2139 char extout_names[32][32];
2140 unsigned int gpr_controls;
2141};
2142
2143#define EMU10K1_GPR_TRANSLATION_NONE 0
2144#define EMU10K1_GPR_TRANSLATION_TABLE100 1
2145#define EMU10K1_GPR_TRANSLATION_BASS 2
2146#define EMU10K1_GPR_TRANSLATION_TREBLE 3
2147#define EMU10K1_GPR_TRANSLATION_ONOFF 4
2148
2149struct snd_emu10k1_fx8010_control_gpr {
2150 struct snd_ctl_elem_id id;
2151 unsigned int vcount;
2152 unsigned int count;
2153 unsigned short gpr[32];
2154 unsigned int value[32];
2155 unsigned int min;
2156 unsigned int max;
2157 unsigned int translation;
2158 const unsigned int *tlv;
2159};
2160
2161
2162struct snd_emu10k1_fx8010_control_old_gpr {
2163 struct snd_ctl_elem_id id;
2164 unsigned int vcount;
2165 unsigned int count;
2166 unsigned short gpr[32];
2167 unsigned int value[32];
2168 unsigned int min;
2169 unsigned int max;
2170 unsigned int translation;
2171};
2172
2173struct snd_emu10k1_fx8010_code {
2174 char name[128];
2175
2176 DECLARE_BITMAP(gpr_valid, 0x200);
2177 __u32 __user *gpr_map;
2178
2179 unsigned int gpr_add_control_count;
2180 struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls;
2181
2182 unsigned int gpr_del_control_count;
2183 struct snd_ctl_elem_id __user *gpr_del_controls;
2184
2185 unsigned int gpr_list_control_count;
2186 unsigned int gpr_list_control_total;
2187 struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls;
2188
2189 DECLARE_BITMAP(tram_valid, 0x100);
2190 __u32 __user *tram_data_map;
2191 __u32 __user *tram_addr_map;
2192
2193 DECLARE_BITMAP(code_valid, 1024);
2194 __u32 __user *code;
2195};
2196
2197struct snd_emu10k1_fx8010_tram {
2198 unsigned int address;
2199 unsigned int size;
2200 unsigned int *samples;
2201
2202};
2203
2204struct snd_emu10k1_fx8010_pcm_rec {
2205 unsigned int substream;
2206 unsigned int res1;
2207 unsigned int channels;
2208 unsigned int tram_start;
2209 unsigned int buffer_size;
2210 unsigned short gpr_size;
2211 unsigned short gpr_ptr;
2212 unsigned short gpr_count;
2213 unsigned short gpr_tmpcount;
2214 unsigned short gpr_trigger;
2215 unsigned short gpr_running;
2216 unsigned char pad;
2217 unsigned char etram[32];
2218 unsigned int res2;
2219};
2220
2221#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
2222
2223#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
2224#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
2225#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
2226#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
2227#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
2228#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
2229#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
2230#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
2231#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
2232#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
2233#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
2234#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
2235#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
2236#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
2237
2238
2239typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
2240typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
2241typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
2242typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
2243typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
2244
2245#endif
2246