1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef __SOUND_VX_COMMON_H
24#define __SOUND_VX_COMMON_H
25
26#include <sound/pcm.h>
27#include <sound/hwdep.h>
28#include <linux/interrupt.h>
29
30#if defined(CONFIG_FW_LOADER) || defined(CONFIG_FW_LOADER_MODULE)
31#if !defined(CONFIG_USE_VXLOADER) && !defined(CONFIG_SND_VX_LIB)
32#define SND_VX_FW_LOADER
33#endif
34#endif
35
36struct firmware;
37struct device;
38
39#define VX_DRIVER_VERSION 0x010000
40
41
42
43#define SIZE_MAX_CMD 0x10
44#define SIZE_MAX_STATUS 0x10
45
46struct vx_rmh {
47 u16 LgCmd;
48 u16 LgStat;
49 u32 Cmd[SIZE_MAX_CMD];
50 u32 Stat[SIZE_MAX_STATUS];
51 u16 DspStat;
52};
53
54typedef u64 pcx_time_t;
55
56#define VX_MAX_PIPES 16
57#define VX_MAX_PERIODS 32
58#define VX_MAX_CODECS 2
59
60struct vx_ibl_info {
61 int size;
62 int max_size;
63 int min_size;
64 int granularity;
65};
66
67struct vx_pipe {
68 int number;
69 unsigned int is_capture: 1;
70 unsigned int data_mode: 1;
71 unsigned int running: 1;
72 unsigned int prepared: 1;
73 int channels;
74 unsigned int differed_type;
75 pcx_time_t pcx_time;
76 struct snd_pcm_substream *substream;
77
78 int hbuf_size;
79 int buffer_bytes;
80 int period_bytes;
81 int hw_ptr;
82 int position;
83 int transferred;
84 int align;
85 u64 cur_count;
86
87 unsigned int references;
88 struct vx_pipe *monitoring_pipe;
89
90 struct tasklet_struct start_tq;
91};
92
93struct vx_core;
94
95struct snd_vx_ops {
96
97 unsigned char (*in8)(struct vx_core *chip, int reg);
98 unsigned int (*in32)(struct vx_core *chip, int reg);
99 void (*out8)(struct vx_core *chip, int reg, unsigned char val);
100 void (*out32)(struct vx_core *chip, int reg, unsigned int val);
101
102 int (*test_and_ack)(struct vx_core *chip);
103 void (*validate_irq)(struct vx_core *chip, int enable);
104
105 void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
106 void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
107 void (*reset_codec)(struct vx_core *chip);
108 void (*change_audio_source)(struct vx_core *chip, int src);
109 void (*set_clock_source)(struct vx_core *chp, int src);
110
111 int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
112 void (*reset_dsp)(struct vx_core *chip);
113 void (*reset_board)(struct vx_core *chip, int cold_reset);
114 int (*add_controls)(struct vx_core *chip);
115
116 void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
117 struct vx_pipe *pipe, int count);
118 void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
119 struct vx_pipe *pipe, int count);
120};
121
122struct snd_vx_hardware {
123 const char *name;
124 int type;
125
126
127 unsigned int num_codecs;
128 unsigned int num_ins;
129 unsigned int num_outs;
130 unsigned int output_level_max;
131 const unsigned int *output_level_db_scale;
132};
133
134
135#define SND_VX_HWDEP_ID "VX Loader"
136
137
138enum {
139
140 VX_TYPE_BOARD,
141 VX_TYPE_V2,
142 VX_TYPE_MIC,
143
144 VX_TYPE_VXPOCKET,
145 VX_TYPE_VXP440,
146 VX_TYPE_NUMS
147};
148
149
150enum {
151 VX_STAT_XILINX_LOADED = (1 << 0),
152 VX_STAT_DEVICE_INIT = (1 << 1),
153 VX_STAT_CHIP_INIT = (1 << 2),
154 VX_STAT_IN_SUSPEND = (1 << 10),
155 VX_STAT_IS_STALE = (1 << 15)
156};
157
158
159#define VX_ANALOG_OUT_LEVEL_MAX 0xe3
160
161struct vx_core {
162
163 struct snd_card *card;
164 struct snd_pcm *pcm[VX_MAX_CODECS];
165 int type;
166
167 int irq;
168
169
170
171 struct snd_vx_hardware *hw;
172 struct snd_vx_ops *ops;
173
174 spinlock_t lock;
175 spinlock_t irq_lock;
176 struct tasklet_struct tq;
177
178 unsigned int chip_status;
179 unsigned int pcm_running;
180
181 struct device *dev;
182 struct snd_hwdep *hwdep;
183
184 struct vx_rmh irq_rmh;
185
186 unsigned int audio_info;
187 unsigned int audio_ins;
188 unsigned int audio_outs;
189 struct vx_pipe **playback_pipes;
190 struct vx_pipe **capture_pipes;
191
192
193 unsigned int audio_source;
194 unsigned int audio_source_target;
195 unsigned int clock_mode;
196 unsigned int clock_source;
197 unsigned int freq;
198 unsigned int freq_detected;
199 unsigned int uer_detected;
200 unsigned int uer_bits;
201 struct vx_ibl_info ibl;
202
203
204 int output_level[VX_MAX_CODECS][2];
205 int audio_gain[2][4];
206 unsigned char audio_active[4];
207 int audio_monitor[4];
208 unsigned char audio_monitor_active[4];
209
210 struct mutex mixer_mutex;
211
212 const struct firmware *firmware[4];
213};
214
215
216
217
218
219struct vx_core *snd_vx_create(struct snd_card *card, struct snd_vx_hardware *hw,
220 struct snd_vx_ops *ops, int extra_size);
221int snd_vx_setup_firmware(struct vx_core *chip);
222int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
223int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
224int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
225
226void snd_vx_free_firmware(struct vx_core *chip);
227
228
229
230
231irqreturn_t snd_vx_irq_handler(int irq, void *dev);
232
233
234
235
236static inline int vx_test_and_ack(struct vx_core *chip)
237{
238 return chip->ops->test_and_ack(chip);
239}
240
241static inline void vx_validate_irq(struct vx_core *chip, int enable)
242{
243 chip->ops->validate_irq(chip, enable);
244}
245
246static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
247{
248 return chip->ops->in8(chip, reg);
249}
250
251static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
252{
253 return chip->ops->in32(chip, reg);
254}
255
256static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
257{
258 chip->ops->out8(chip, reg, val);
259}
260
261static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
262{
263 chip->ops->out32(chip, reg, val);
264}
265
266#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg)
267#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val)
268#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg)
269#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val)
270
271static inline void vx_reset_dsp(struct vx_core *chip)
272{
273 chip->ops->reset_dsp(chip);
274}
275
276int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
277int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
278int vx_send_rih(struct vx_core *chip, int cmd);
279int vx_send_rih_nolock(struct vx_core *chip, int cmd);
280
281void vx_reset_codec(struct vx_core *chip, int cold_reset);
282
283
284
285
286
287
288int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
289#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
290#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
291#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
292
293
294
295
296
297static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
298 struct vx_pipe *pipe, int count)
299{
300 chip->ops->dma_write(chip, runtime, pipe, count);
301}
302
303static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
304 struct vx_pipe *pipe, int count)
305{
306 chip->ops->dma_read(chip, runtime, pipe, count);
307}
308
309
310
311
312
313
314#define VX_ERR_MASK 0x1000000
315#define vx_get_error(err) (-(err) & ~VX_ERR_MASK)
316
317
318
319
320
321int snd_vx_pcm_new(struct vx_core *chip);
322void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
323
324
325
326
327int snd_vx_mixer_new(struct vx_core *chip);
328void vx_toggle_dac_mute(struct vx_core *chip, int mute);
329int vx_sync_audio_source(struct vx_core *chip);
330int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
331
332
333
334
335void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
336int vx_set_clock(struct vx_core *chip, unsigned int freq);
337void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
338int vx_change_frequency(struct vx_core *chip);
339
340
341
342
343
344int snd_vx_suspend(struct vx_core *card, pm_message_t state);
345int snd_vx_resume(struct vx_core *card);
346
347
348
349
350
351#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD)
352#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET)
353
354
355enum {
356 VX_AUDIO_SRC_DIGITAL,
357 VX_AUDIO_SRC_LINE,
358 VX_AUDIO_SRC_MIC
359};
360
361
362enum {
363 INTERNAL_QUARTZ,
364 UER_SYNC
365};
366
367
368enum {
369 VX_CLOCK_MODE_AUTO,
370 VX_CLOCK_MODE_INTERNAL,
371 VX_CLOCK_MODE_EXTERNAL
372};
373
374
375enum {
376 VX_UER_MODE_CONSUMER,
377 VX_UER_MODE_PROFESSIONAL,
378 VX_UER_MODE_NOT_PRESENT,
379};
380
381
382enum {
383 VX_ICR,
384 VX_CVR,
385 VX_ISR,
386 VX_IVR,
387 VX_RXH,
388 VX_TXH = VX_RXH,
389 VX_RXM,
390 VX_TXM = VX_RXM,
391 VX_RXL,
392 VX_TXL = VX_RXL,
393 VX_DMA,
394 VX_CDSP,
395 VX_RFREQ,
396 VX_RUER_V2,
397 VX_GAIN,
398 VX_DATA = VX_GAIN,
399 VX_MEMIRQ,
400 VX_ACQ,
401 VX_BIT0,
402 VX_BIT1,
403 VX_MIC0,
404 VX_MIC1,
405 VX_MIC2,
406 VX_MIC3,
407 VX_PLX0,
408 VX_PLX1,
409 VX_PLX2,
410
411 VX_LOFREQ,
412 VX_HIFREQ,
413 VX_CSUER,
414 VX_RUER,
415
416 VX_REG_MAX,
417
418
419 VX_RESET_DMA = VX_ISR,
420 VX_CFG = VX_RFREQ,
421 VX_STATUS = VX_MEMIRQ,
422 VX_SELMIC = VX_MIC0,
423 VX_COMPOT = VX_MIC1,
424 VX_SCOMPR = VX_MIC2,
425 VX_GLIMIT = VX_MIC3,
426 VX_INTCSR = VX_PLX0,
427 VX_CNTRL = VX_PLX1,
428 VX_GPIOC = VX_PLX2,
429
430
431 VX_MICRO = VX_MEMIRQ,
432 VX_CODEC2 = VX_MEMIRQ,
433 VX_DIALOG = VX_ACQ,
434
435};
436
437
438enum {
439 RMH_SSIZE_FIXED = 0,
440 RMH_SSIZE_ARG = 1,
441 RMH_SSIZE_MASK = 2,
442};
443
444
445
446#define ICR_HF1 0x10
447#define ICR_HF0 0x08
448#define ICR_TREQ 0x02
449#define ICR_RREQ 0x01
450
451
452#define CVR_HC 0x80
453
454
455#define ISR_HF3 0x10
456#define ISR_HF2 0x08
457#define ISR_CHK 0x10
458#define ISR_ERR 0x08
459#define ISR_TX_READY 0x04
460#define ISR_TX_EMPTY 0x02
461#define ISR_RX_FULL 0x01
462
463
464#define VX_DATA_CODEC_MASK 0x80
465#define VX_DATA_XICOR_MASK 0x80
466
467
468#define VX_SUER_FREQ_MASK 0x0c
469#define VX_SUER_FREQ_32KHz_MASK 0x0c
470#define VX_SUER_FREQ_44KHz_MASK 0x00
471#define VX_SUER_FREQ_48KHz_MASK 0x04
472#define VX_SUER_DATA_PRESENT_MASK 0x02
473#define VX_SUER_CLOCK_PRESENT_MASK 0x01
474
475#define VX_CUER_HH_BITC_SEL_MASK 0x08
476#define VX_CUER_MH_BITC_SEL_MASK 0x04
477#define VX_CUER_ML_BITC_SEL_MASK 0x02
478#define VX_CUER_LL_BITC_SEL_MASK 0x01
479
480#define XX_UER_CBITS_OFFSET_MASK 0x1f
481
482
483
484#define VX_AUDIO_INFO_REAL_TIME (1<<0)
485#define VX_AUDIO_INFO_OFFLINE (1<<1)
486#define VX_AUDIO_INFO_MPEG1 (1<<5)
487#define VX_AUDIO_INFO_MPEG2 (1<<6)
488#define VX_AUDIO_INFO_LINEAR_8 (1<<7)
489#define VX_AUDIO_INFO_LINEAR_16 (1<<8)
490#define VX_AUDIO_INFO_LINEAR_24 (1<<9)
491
492
493#define VXP_IRQ_OFFSET 0x40
494
495#define IRQ_MESS_WRITE_END 0x30
496#define IRQ_MESS_WRITE_NEXT 0x32
497#define IRQ_MESS_READ_NEXT 0x34
498#define IRQ_MESS_READ_END 0x36
499#define IRQ_MESSAGE 0x38
500#define IRQ_RESET_CHK 0x3A
501#define IRQ_CONNECT_STREAM_NEXT 0x26
502#define IRQ_CONNECT_STREAM_END 0x28
503#define IRQ_PAUSE_START_CONNECT 0x2A
504#define IRQ_END_CONNECTION 0x2C
505
506
507#define ASYNC_EVENTS_PENDING 0x008000
508#define HBUFFER_EVENTS_PENDING 0x004000
509#define NOTIF_EVENTS_PENDING 0x002000
510#define TIME_CODE_EVENT_PENDING 0x001000
511#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800
512#define END_OF_BUFFER_EVENTS_PENDING 0x000400
513#define FATAL_DSP_ERROR 0xff0000
514
515
516#define HEADER_FMT_BASE 0xFED00000
517#define HEADER_FMT_MONO 0x000000C0
518#define HEADER_FMT_INTEL 0x00008000
519#define HEADER_FMT_16BITS 0x00002000
520#define HEADER_FMT_24BITS 0x00004000
521#define HEADER_FMT_UPTO11 0x00000200
522#define HEADER_FMT_UPTO32 0x00000100
523
524
525#define XX_CODEC_SELECTOR 0x20
526
527#define XX_CODEC_ADC_CONTROL_REGISTER 0x01
528#define XX_CODEC_DAC_CONTROL_REGISTER 0x02
529#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03
530#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04
531#define XX_CODEC_PORT_MODE_REGISTER 0x05
532#define XX_CODEC_STATUS_REPORT_REGISTER 0x06
533#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
534
535
536
537
538#define CVAL_M110DB 0x000
539#define CVAL_M99DB 0x02C
540#define CVAL_M21DB 0x163
541#define CVAL_M18DB 0x16F
542#define CVAL_M10DB 0x18F
543#define CVAL_0DB 0x1B7
544#define CVAL_18DB 0x1FF
545#define CVAL_MAX 0x1FF
546
547#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000
548#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000
549#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000
550#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01
551#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02
552#define VALID_AUDIO_IO_MUTE_LEVEL 0x04
553#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08
554#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10
555
556
557#endif
558