1#ifndef __sis7019_h__ 2#define __sis7019_h__ 3 4/* 5 * Definitions for SiS7019 Audio Accelerator 6 * 7 * Copyright (C) 2004-2007, David Dillow 8 * Written by David Dillow <dave@thedillows.org> 9 * Inspired by the Trident 4D-WaveDX/NX driver. 10 * 11 * All rights reserved. 12 * 13 * This program is free software; you can redistribute it and/or modify 14 * it under the terms of the GNU General Public License as published by 15 * the Free Software Foundation, version 2. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 */ 26 27 28/* General Control Register */ 29#define SIS_GCR 0x00 30#define SIS_GCR_MACRO_POWER_DOWN 0x80000000 31#define SIS_GCR_MODEM_ENABLE 0x00010000 32#define SIS_GCR_SOFTWARE_RESET 0x00000001 33 34/* General Interrupt Enable Register */ 35#define SIS_GIER 0x04 36#define SIS_GIER_MODEM_TIMER_IRQ_ENABLE 0x00100000 37#define SIS_GIER_MODEM_RX_DMA_IRQ_ENABLE 0x00080000 38#define SIS_GIER_MODEM_TX_DMA_IRQ_ENABLE 0x00040000 39#define SIS_GIER_AC97_GPIO1_IRQ_ENABLE 0x00020000 40#define SIS_GIER_AC97_GPIO0_IRQ_ENABLE 0x00010000 41#define SIS_GIER_AC97_SAMPLE_TIMER_IRQ_ENABLE 0x00000010 42#define SIS_GIER_AUDIO_GLOBAL_TIMER_IRQ_ENABLE 0x00000008 43#define SIS_GIER_AUDIO_RECORD_DMA_IRQ_ENABLE 0x00000004 44#define SIS_GIER_AUDIO_PLAY_DMA_IRQ_ENABLE 0x00000002 45#define SIS_GIER_AUDIO_WAVE_ENGINE_IRQ_ENABLE 0x00000001 46 47/* General Interrupt Status Register */ 48#define SIS_GISR 0x08 49#define SIS_GISR_MODEM_TIMER_IRQ_STATUS 0x00100000 50#define SIS_GISR_MODEM_RX_DMA_IRQ_STATUS 0x00080000 51#define SIS_GISR_MODEM_TX_DMA_IRQ_STATUS 0x00040000 52#define SIS_GISR_AC97_GPIO1_IRQ_STATUS 0x00020000 53#define SIS_GISR_AC97_GPIO0_IRQ_STATUS 0x00010000 54#define SIS_GISR_AC97_SAMPLE_TIMER_IRQ_STATUS 0x00000010 55#define SIS_GISR_AUDIO_GLOBAL_TIMER_IRQ_STATUS 0x00000008 56#define SIS_GISR_AUDIO_RECORD_DMA_IRQ_STATUS 0x00000004 57#define SIS_GISR_AUDIO_PLAY_DMA_IRQ_STATUS 0x00000002 58#define SIS_GISR_AUDIO_WAVE_ENGINE_IRQ_STATUS 0x00000001 59 60/* DMA Control Register */ 61#define SIS_DMA_CSR 0x10 62#define SIS_DMA_CSR_PCI_SETTINGS 0x0000001d 63#define SIS_DMA_CSR_CONCURRENT_ENABLE 0x00000200 64#define SIS_DMA_CSR_PIPELINE_ENABLE 0x00000100 65#define SIS_DMA_CSR_RX_DRAIN_ENABLE 0x00000010 66#define SIS_DMA_CSR_RX_FILL_ENABLE 0x00000008 67#define SIS_DMA_CSR_TX_DRAIN_ENABLE 0x00000004 68#define SIS_DMA_CSR_TX_LOWPRI_FILL_ENABLE 0x00000002 69#define SIS_DMA_CSR_TX_HIPRI_FILL_ENABLE 0x00000001 70 71/* Playback Channel Start Registers */ 72#define SIS_PLAY_START_A_REG 0x14 73#define SIS_PLAY_START_B_REG 0x18 74 75/* Playback Channel Stop Registers */ 76#define SIS_PLAY_STOP_A_REG 0x1c 77#define SIS_PLAY_STOP_B_REG 0x20 78 79/* Recording Channel Start Register */ 80#define SIS_RECORD_START_REG 0x24 81 82/* Recording Channel Stop Register */ 83#define SIS_RECORD_STOP_REG 0x28 84 85/* Playback Interrupt Status Registers */ 86#define SIS_PISR_A 0x2c 87#define SIS_PISR_B 0x30 88 89/* Recording Interrupt Status Register */ 90#define SIS_RISR 0x34 91 92/* AC97 AC-link Playback Source Register */ 93#define SIS_AC97_PSR 0x40 94#define SIS_AC97_PSR_MODEM_HEADSET_SRC_MIXER 0x0f000000 95#define SIS_AC97_PSR_MODEM_LINE2_SRC_MIXER 0x00f00000 96#define SIS_AC97_PSR_MODEM_LINE1_SRC_MIXER 0x000f0000 97#define SIS_AC97_PSR_PCM_LFR_SRC_MIXER 0x0000f000 98#define SIS_AC97_PSR_PCM_SURROUND_SRC_MIXER 0x00000f00 99#define SIS_AC97_PSR_PCM_CENTER_SRC_MIXER 0x000000f0 100#define SIS_AC97_PSR_PCM_LR_SRC_MIXER 0x0000000f 101 102/* AC97 AC-link Command Register */ 103#define SIS_AC97_CMD 0x50 104#define SIS_AC97_CMD_DATA_MASK 0xffff0000 105#define SIS_AC97_CMD_REG_MASK 0x0000ff00 106#define SIS_AC97_CMD_CODEC3_READ 0x0000000d 107#define SIS_AC97_CMD_CODEC3_WRITE 0x0000000c 108#define SIS_AC97_CMD_CODEC2_READ 0x0000000b 109#define SIS_AC97_CMD_CODEC2_WRITE 0x0000000a 110#define SIS_AC97_CMD_CODEC_READ 0x00000009 111#define SIS_AC97_CMD_CODEC_WRITE 0x00000008 112#define SIS_AC97_CMD_CODEC_WARM_RESET 0x00000005 113#define SIS_AC97_CMD_CODEC_COLD_RESET 0x00000004 114#define SIS_AC97_CMD_DONE 0x00000000 115 116/* AC97 AC-link Semaphore Register */ 117#define SIS_AC97_SEMA 0x54 118#define SIS_AC97_SEMA_BUSY 0x00000001 119#define SIS_AC97_SEMA_RELEASE 0x00000000 120 121/* AC97 AC-link Status Register */ 122#define SIS_AC97_STATUS 0x58 123#define SIS_AC97_STATUS_AUDIO_D2_INACT_SECS 0x03f00000 124#define SIS_AC97_STATUS_MODEM_ALIVE 0x00002000 125#define SIS_AC97_STATUS_AUDIO_ALIVE 0x00001000 126#define SIS_AC97_STATUS_CODEC3_READY 0x00000400 127#define SIS_AC97_STATUS_CODEC2_READY 0x00000200 128#define SIS_AC97_STATUS_CODEC_READY 0x00000100 129#define SIS_AC97_STATUS_WARM_RESET 0x00000080 130#define SIS_AC97_STATUS_COLD_RESET 0x00000040 131#define SIS_AC97_STATUS_POWERED_DOWN 0x00000020 132#define SIS_AC97_STATUS_NORMAL 0x00000010 133#define SIS_AC97_STATUS_READ_EXPIRED 0x00000004 134#define SIS_AC97_STATUS_SEMAPHORE 0x00000002 135#define SIS_AC97_STATUS_BUSY 0x00000001 136 137/* AC97 AC-link Audio Configuration Register */ 138#define SIS_AC97_CONF 0x5c 139#define SIS_AC97_CONF_AUDIO_ALIVE 0x80000000 140#define SIS_AC97_CONF_WARM_RESET_ENABLE 0x40000000 141#define SIS_AC97_CONF_PR6_ENABLE 0x20000000 142#define SIS_AC97_CONF_PR5_ENABLE 0x10000000 143#define SIS_AC97_CONF_PR4_ENABLE 0x08000000 144#define SIS_AC97_CONF_PR3_ENABLE 0x04000000 145#define SIS_AC97_CONF_PR2_PR7_ENABLE 0x02000000 146#define SIS_AC97_CONF_PR0_PR1_ENABLE 0x01000000 147#define SIS_AC97_CONF_AUTO_PM_ENABLE 0x00800000 148#define SIS_AC97_CONF_PCM_LFE_ENABLE 0x00080000 149#define SIS_AC97_CONF_PCM_SURROUND_ENABLE 0x00040000 150#define SIS_AC97_CONF_PCM_CENTER_ENABLE 0x00020000 151#define SIS_AC97_CONF_PCM_LR_ENABLE 0x00010000 152#define SIS_AC97_CONF_PCM_CAP_MIC_ENABLE 0x00002000 153#define SIS_AC97_CONF_PCM_CAP_LR_ENABLE 0x00001000 154#define SIS_AC97_CONF_PCM_CAP_MIC_FROM_CODEC3 0x00000200 155#define SIS_AC97_CONF_PCM_CAP_LR_FROM_CODEC3 0x00000100 156#define SIS_AC97_CONF_CODEC3_PM_VRM 0x00000080 157#define SIS_AC97_CONF_CODEC_PM_VRM 0x00000040 158#define SIS_AC97_CONF_CODEC3_VRA_ENABLE 0x00000020 159#define SIS_AC97_CONF_CODEC_VRA_ENABLE 0x00000010 160#define SIS_AC97_CONF_CODEC3_PM_EAC 0x00000008 161#define SIS_AC97_CONF_CODEC_PM_EAC 0x00000004 162#define SIS_AC97_CONF_CODEC3_EXISTS 0x00000002 163#define SIS_AC97_CONF_CODEC_EXISTS 0x00000001 164 165/* Playback Channel Sync Group registers */ 166#define SIS_PLAY_SYNC_GROUP_A 0x80 167#define SIS_PLAY_SYNC_GROUP_B 0x84 168#define SIS_PLAY_SYNC_GROUP_C 0x88 169#define SIS_PLAY_SYNC_GROUP_D 0x8c 170#define SIS_MIXER_SYNC_GROUP 0x90 171 172/* Wave Engine Config and Control Register */ 173#define SIS_WECCR 0xa0 174#define SIS_WECCR_TESTMODE_MASK 0x00300000 175#define SIS_WECCR_TESTMODE_NORMAL 0x00000000 176#define SIS_WECCR_TESTMODE_BYPASS_NSO_ALPHA 0x00100000 177#define SIS_WECCR_TESTMODE_BYPASS_FC 0x00200000 178#define SIS_WECCR_TESTMODE_BYPASS_WOL 0x00300000 179#define SIS_WECCR_RESONANCE_DELAY_MASK 0x00060000 180#define SIS_WECCR_RESONANCE_DELAY_NONE 0x00000000 181#define SIS_WECCR_RESONANCE_DELAY_FC_1F00 0x00020000 182#define SIS_WECCR_RESONANCE_DELAY_FC_1E00 0x00040000 183#define SIS_WECCR_RESONANCE_DELAY_FC_1C00 0x00060000 184#define SIS_WECCR_IGNORE_CHANNEL_PARMS 0x00010000 185#define SIS_WECCR_COMMAND_CHANNEL_ID_MASK 0x0003ff00 186#define SIS_WECCR_COMMAND_MASK 0x00000007 187#define SIS_WECCR_COMMAND_NONE 0x00000000 188#define SIS_WECCR_COMMAND_DONE 0x00000000 189#define SIS_WECCR_COMMAND_PAUSE 0x00000001 190#define SIS_WECCR_COMMAND_TOGGLE_VEG 0x00000002 191#define SIS_WECCR_COMMAND_TOGGLE_MEG 0x00000003 192#define SIS_WECCR_COMMAND_TOGGLE_VEG_MEG 0x00000004 193 194/* Wave Engine Volume Control Register */ 195#define SIS_WEVCR 0xa4 196#define SIS_WEVCR_LEFT_MUSIC_ATTENUATION_MASK 0xff000000 197#define SIS_WEVCR_RIGHT_MUSIC_ATTENUATION_MASK 0x00ff0000 198#define SIS_WEVCR_LEFT_WAVE_ATTENUATION_MASK 0x0000ff00 199#define SIS_WEVCR_RIGHT_WAVE_ATTENUATION_MASK 0x000000ff 200 201/* Wave Engine Interrupt Status Registers */ 202#define SIS_WEISR_A 0xa8 203#define SIS_WEISR_B 0xac 204 205 206/* Playback DMA parameters (parameter RAM) */ 207#define SIS_PLAY_DMA_OFFSET 0x0000 208#define SIS_PLAY_DMA_SIZE 0x10 209#define SIS_PLAY_DMA_ADDR(addr, num) \ 210 ((num * SIS_PLAY_DMA_SIZE) + (addr) + SIS_PLAY_DMA_OFFSET) 211 212#define SIS_PLAY_DMA_FORMAT_CSO 0x00 213#define SIS_PLAY_DMA_FORMAT_UNSIGNED 0x00080000 214#define SIS_PLAY_DMA_FORMAT_8BIT 0x00040000 215#define SIS_PLAY_DMA_FORMAT_MONO 0x00020000 216#define SIS_PLAY_DMA_CSO_MASK 0x0000ffff 217#define SIS_PLAY_DMA_BASE 0x04 218#define SIS_PLAY_DMA_CONTROL 0x08 219#define SIS_PLAY_DMA_STOP_AT_SSO 0x04000000 220#define SIS_PLAY_DMA_RELEASE 0x02000000 221#define SIS_PLAY_DMA_LOOP 0x01000000 222#define SIS_PLAY_DMA_INTR_AT_SSO 0x00080000 223#define SIS_PLAY_DMA_INTR_AT_ESO 0x00040000 224#define SIS_PLAY_DMA_INTR_AT_LEO 0x00020000 225#define SIS_PLAY_DMA_INTR_AT_MLP 0x00010000 226#define SIS_PLAY_DMA_LEO_MASK 0x0000ffff 227#define SIS_PLAY_DMA_SSO_ESO 0x0c 228#define SIS_PLAY_DMA_SSO_MASK 0xffff0000 229#define SIS_PLAY_DMA_ESO_MASK 0x0000ffff 230 231/* Capture DMA parameters (parameter RAM) */ 232#define SIS_CAPTURE_DMA_OFFSET 0x0800 233#define SIS_CAPTURE_DMA_SIZE 0x10 234#define SIS_CAPTURE_DMA_ADDR(addr, num) \ 235 ((num * SIS_CAPTURE_DMA_SIZE) + (addr) + SIS_CAPTURE_DMA_OFFSET) 236 237#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_0 0 238#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_1 1 239#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_2 2 240#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_3 3 241#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_4 4 242#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_5 5 243#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_6 6 244#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_7 7 245#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_8 8 246#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_9 9 247#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_10 10 248#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_11 11 249#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_12 12 250#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_13 13 251#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_14 14 252#define SIS_CAPTURE_CHAN_MIXER_ROUTE_BACK_15 15 253#define SIS_CAPTURE_CHAN_AC97_PCM_IN 16 254#define SIS_CAPTURE_CHAN_AC97_MIC_IN 17 255#define SIS_CAPTURE_CHAN_AC97_LINE1_IN 18 256#define SIS_CAPTURE_CHAN_AC97_LINE2_IN 19 257#define SIS_CAPTURE_CHAN_AC97_HANDSE_IN 20 258 259#define SIS_CAPTURE_DMA_FORMAT_CSO 0x00 260#define SIS_CAPTURE_DMA_MONO_MODE_MASK 0xc0000000 261#define SIS_CAPTURE_DMA_MONO_MODE_AVG 0x00000000 262#define SIS_CAPTURE_DMA_MONO_MODE_LEFT 0x40000000 263#define SIS_CAPTURE_DMA_MONO_MODE_RIGHT 0x80000000 264#define SIS_CAPTURE_DMA_FORMAT_UNSIGNED 0x00080000 265#define SIS_CAPTURE_DMA_FORMAT_8BIT 0x00040000 266#define SIS_CAPTURE_DMA_FORMAT_MONO 0x00020000 267#define SIS_CAPTURE_DMA_CSO_MASK 0x0000ffff 268#define SIS_CAPTURE_DMA_BASE 0x04 269#define SIS_CAPTURE_DMA_CONTROL 0x08 270#define SIS_CAPTURE_DMA_STOP_AT_SSO 0x04000000 271#define SIS_CAPTURE_DMA_RELEASE 0x02000000 272#define SIS_CAPTURE_DMA_LOOP 0x01000000 273#define SIS_CAPTURE_DMA_INTR_AT_LEO 0x00020000 274#define SIS_CAPTURE_DMA_INTR_AT_MLP 0x00010000 275#define SIS_CAPTURE_DMA_LEO_MASK 0x0000ffff 276#define SIS_CAPTURE_DMA_RESERVED 0x0c 277 278 279/* Mixer routing list start pointer (parameter RAM) */ 280#define SIS_MIXER_START_OFFSET 0x1000 281#define SIS_MIXER_START_SIZE 0x04 282#define SIS_MIXER_START_ADDR(addr, num) \ 283 ((num * SIS_MIXER_START_SIZE) + (addr) + SIS_MIXER_START_OFFSET) 284 285#define SIS_MIXER_START_MASK 0x0000007f 286 287/* Mixer routing table (parameter RAM) */ 288#define SIS_MIXER_OFFSET 0x1400 289#define SIS_MIXER_SIZE 0x04 290#define SIS_MIXER_ADDR(addr, num) \ 291 ((num * SIS_MIXER_SIZE) + (addr) + SIS_MIXER_OFFSET) 292 293#define SIS_MIXER_RIGHT_ATTENUTATION_MASK 0xff000000 294#define SIS_MIXER_RIGHT_NO_ATTEN 0xff000000 295#define SIS_MIXER_LEFT_ATTENUTATION_MASK 0x00ff0000 296#define SIS_MIXER_LEFT_NO_ATTEN 0x00ff0000 297#define SIS_MIXER_NEXT_ENTRY_MASK 0x00007f00 298#define SIS_MIXER_NEXT_ENTRY_NONE 0x00000000 299#define SIS_MIXER_DEST_MASK 0x0000007f 300#define SIS_MIXER_DEST_0 0x00000020 301#define SIS_MIXER_DEST_1 0x00000021 302#define SIS_MIXER_DEST_2 0x00000022 303#define SIS_MIXER_DEST_3 0x00000023 304#define SIS_MIXER_DEST_4 0x00000024 305#define SIS_MIXER_DEST_5 0x00000025 306#define SIS_MIXER_DEST_6 0x00000026 307#define SIS_MIXER_DEST_7 0x00000027 308#define SIS_MIXER_DEST_8 0x00000028 309#define SIS_MIXER_DEST_9 0x00000029 310#define SIS_MIXER_DEST_10 0x0000002a 311#define SIS_MIXER_DEST_11 0x0000002b 312#define SIS_MIXER_DEST_12 0x0000002c 313#define SIS_MIXER_DEST_13 0x0000002d 314#define SIS_MIXER_DEST_14 0x0000002e 315#define SIS_MIXER_DEST_15 0x0000002f 316 317/* Wave Engine Control Parameters (parameter RAM) */ 318#define SIS_WAVE_OFFSET 0x2000 319#define SIS_WAVE_SIZE 0x40 320#define SIS_WAVE_ADDR(addr, num) \ 321 ((num * SIS_WAVE_SIZE) + (addr) + SIS_WAVE_OFFSET) 322 323#define SIS_WAVE_GENERAL 0x00 324#define SIS_WAVE_GENERAL_WAVE_VOLUME 0x80000000 325#define SIS_WAVE_GENERAL_MUSIC_VOLUME 0x00000000 326#define SIS_WAVE_GENERAL_VOLUME_MASK 0x7f000000 327#define SIS_WAVE_GENERAL_ARTICULATION 0x04 328#define SIS_WAVE_GENERAL_ARTICULATION_DELTA_MASK 0x3fff0000 329#define SIS_WAVE_ARTICULATION 0x08 330#define SIS_WAVE_TIMER 0x0c 331#define SIS_WAVE_GENERATOR 0x10 332#define SIS_WAVE_CHANNEL_CONTROL 0x14 333#define SIS_WAVE_CHANNEL_CONTROL_FIRST_SAMPLE 0x80000000 334#define SIS_WAVE_CHANNEL_CONTROL_AMP_ENABLE 0x40000000 335#define SIS_WAVE_CHANNEL_CONTROL_FILTER_ENABLE 0x20000000 336#define SIS_WAVE_CHANNEL_CONTROL_INTERPOLATE_ENABLE 0x10000000 337#define SIS_WAVE_LFO_EG_CONTROL 0x18 338#define SIS_WAVE_LFO_EG_CONTROL_2 0x1c 339#define SIS_WAVE_LFO_EG_CONTROL_3 0x20 340#define SIS_WAVE_LFO_EG_CONTROL_4 0x24 341 342#endif /* __sis7019_h__ */ 343