LXR linux/sound/soc/codecs/tlv320aic3x.h

   1/*
   2 * ALSA SoC TLV320AIC3X codec driver
   3 *
   4 * Author:      Vladimir Barinov, <vbarinov@embeddedalley.com>
   5 * Copyright:   (C) 2007 MontaVista Software, Inc., <source@mvista.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License version 2 as
   9 * published by the Free Software Foundation.
  10 */
  11
  12#ifndef _AIC3X_H
  13#define _AIC3X_H
  14
  15/* AIC3X register space */
  16#define AIC3X_CACHEREGNUM               103
  17
  18/* Page select register */
  19#define AIC3X_PAGE_SELECT               0
  20/* Software reset register */
  21#define AIC3X_RESET                     1
  22/* Codec Sample rate select register */
  23#define AIC3X_SAMPLE_RATE_SEL_REG       2
  24/* PLL progrramming register A */
  25#define AIC3X_PLL_PROGA_REG             3
  26/* PLL progrramming register B */
  27#define AIC3X_PLL_PROGB_REG             4
  28/* PLL progrramming register C */
  29#define AIC3X_PLL_PROGC_REG             5
  30/* PLL progrramming register D */
  31#define AIC3X_PLL_PROGD_REG             6
  32/* Codec datapath setup register */
  33#define AIC3X_CODEC_DATAPATH_REG        7
  34/* Audio serial data interface control register A */
  35#define AIC3X_ASD_INTF_CTRLA            8
  36/* Audio serial data interface control register B */
  37#define AIC3X_ASD_INTF_CTRLB            9
  38/* Audio serial data interface control register C */
  39#define AIC3X_ASD_INTF_CTRLC            10
  40/* Audio overflow status and PLL R value programming register */
  41#define AIC3X_OVRF_STATUS_AND_PLLR_REG  11
  42/* Audio codec digital filter control register */
  43#define AIC3X_CODEC_DFILT_CTRL          12
  44/* Headset/button press detection register */
  45#define AIC3X_HEADSET_DETECT_CTRL_A     13
  46#define AIC3X_HEADSET_DETECT_CTRL_B     14
  47/* ADC PGA Gain control registers */
  48#define LADC_VOL                        15
  49#define RADC_VOL                        16
  50/* MIC3 control registers */
  51#define MIC3LR_2_LADC_CTRL              17
  52#define MIC3LR_2_RADC_CTRL              18
  53/* Line1 Input control registers */
  54#define LINE1L_2_LADC_CTRL              19
  55#define LINE1R_2_LADC_CTRL              21
  56#define LINE1R_2_RADC_CTRL              22
  57#define LINE1L_2_RADC_CTRL              24
  58/* Line2 Input control registers */
  59#define LINE2L_2_LADC_CTRL              20
  60#define LINE2R_2_RADC_CTRL              23
  61/* MICBIAS Control Register */
  62#define MICBIAS_CTRL                    25
  63
  64/* AGC Control Registers A, B, C */
  65#define LAGC_CTRL_A                     26
  66#define LAGC_CTRL_B                     27
  67#define LAGC_CTRL_C                     28
  68#define RAGC_CTRL_A                     29
  69#define RAGC_CTRL_B                     30
  70#define RAGC_CTRL_C                     31
  71
  72/* DAC Power and Left High Power Output control registers */
  73#define DAC_PWR                         37
  74#define HPLCOM_CFG                      37
  75/* Right High Power Output control registers */
  76#define HPRCOM_CFG                      38
  77/* DAC Output Switching control registers */
  78#define DAC_LINE_MUX                    41
  79/* High Power Output Driver Pop Reduction registers */
  80#define HPOUT_POP_REDUCTION             42
  81/* DAC Digital control registers */
  82#define LDAC_VOL                        43
  83#define RDAC_VOL                        44
  84/* High Power Output control registers */
  85#define LINE2L_2_HPLOUT_VOL             45
  86#define LINE2R_2_HPROUT_VOL             62
  87#define PGAL_2_HPLOUT_VOL               46
  88#define PGAL_2_HPROUT_VOL               60
  89#define PGAR_2_HPLOUT_VOL               49
  90#define PGAR_2_HPROUT_VOL               63
  91#define DACL1_2_HPLOUT_VOL              47
  92#define DACR1_2_HPROUT_VOL              64
  93#define HPLOUT_CTRL                     51
  94#define HPROUT_CTRL                     65
  95/* High Power COM control registers */
  96#define LINE2L_2_HPLCOM_VOL             52
  97#define LINE2R_2_HPRCOM_VOL             69
  98#define PGAL_2_HPLCOM_VOL               53
  99#define PGAR_2_HPLCOM_VOL               56
 100#define PGAL_2_HPRCOM_VOL               67
 101#define PGAR_2_HPRCOM_VOL               70
 102#define DACL1_2_HPLCOM_VOL              54
 103#define DACR1_2_HPRCOM_VOL              71
 104#define HPLCOM_CTRL                     58
 105#define HPRCOM_CTRL                     72
 106/* Mono Line Output Plus/Minus control registers */
 107#define LINE2L_2_MONOLOPM_VOL           73
 108#define LINE2R_2_MONOLOPM_VOL           76
 109#define PGAL_2_MONOLOPM_VOL             74
 110#define PGAR_2_MONOLOPM_VOL             77
 111#define DACL1_2_MONOLOPM_VOL            75
 112#define DACR1_2_MONOLOPM_VOL            78
 113#define MONOLOPM_CTRL                   79
 114/* Line Output Plus/Minus control registers */
 115#define LINE2L_2_LLOPM_VOL              80
 116#define LINE2L_2_RLOPM_VOL              87
 117#define LINE2R_2_LLOPM_VOL              83
 118#define LINE2R_2_RLOPM_VOL              90
 119#define PGAL_2_LLOPM_VOL                81
 120#define PGAL_2_RLOPM_VOL                88
 121#define PGAR_2_LLOPM_VOL                84
 122#define PGAR_2_RLOPM_VOL                91
 123#define DACL1_2_LLOPM_VOL               82
 124#define DACL1_2_RLOPM_VOL               89
 125#define DACR1_2_RLOPM_VOL               92
 126#define DACR1_2_LLOPM_VOL               85
 127#define LLOPM_CTRL                      86
 128#define RLOPM_CTRL                      93
 129/* GPIO/IRQ registers */
 130#define AIC3X_STICKY_IRQ_FLAGS_REG      96
 131#define AIC3X_RT_IRQ_FLAGS_REG          97
 132#define AIC3X_GPIO1_REG                 98
 133#define AIC3X_GPIO2_REG                 99
 134#define AIC3X_GPIOA_REG                 100
 135#define AIC3X_GPIOB_REG                 101
 136/* Clock generation control register */
 137#define AIC3X_CLKGEN_CTRL_REG           102
 138
 139/* Page select register bits */
 140#define PAGE0_SELECT            0
 141#define PAGE1_SELECT            1
 142
 143/* Audio serial data interface control register A bits */
 144#define BIT_CLK_MASTER          0x80
 145#define WORD_CLK_MASTER         0x40
 146
 147/* Codec Datapath setup register 7 */
 148#define FSREF_44100             (1 << 7)
 149#define FSREF_48000             (0 << 7)
 150#define DUAL_RATE_MODE          ((1 << 5) | (1 << 6))
 151#define LDAC2LCH                (0x1 << 3)
 152#define RDAC2RCH                (0x1 << 1)
 153
 154/* PLL registers bitfields */
 155#define PLLP_SHIFT              0
 156#define PLLQ_SHIFT              3
 157#define PLLR_SHIFT              0
 158#define PLLJ_SHIFT              2
 159#define PLLD_MSB_SHIFT          0
 160#define PLLD_LSB_SHIFT          2
 161
 162/* Clock generation register bits */
 163#define CODEC_CLKIN_PLLDIV      0
 164#define CODEC_CLKIN_CLKDIV      1
 165#define PLL_CLKIN_SHIFT         4
 166#define MCLK_SOURCE             0x0
 167#define PLL_CLKDIV_SHIFT        0
 168
 169/* Software reset register bits */
 170#define SOFT_RESET              0x80
 171
 172/* PLL progrramming register A bits */
 173#define PLL_ENABLE              0x80
 174
 175/* Route bits */
 176#define ROUTE_ON                0x80
 177
 178/* Mute bits */
 179#define UNMUTE                  0x08
 180#define MUTE_ON                 0x80
 181
 182/* Power bits */
 183#define LADC_PWR_ON             0x04
 184#define RADC_PWR_ON             0x04
 185#define LDAC_PWR_ON             0x80
 186#define RDAC_PWR_ON             0x40
 187#define HPLOUT_PWR_ON           0x01
 188#define HPROUT_PWR_ON           0x01
 189#define HPLCOM_PWR_ON           0x01
 190#define HPRCOM_PWR_ON           0x01
 191#define MONOLOPM_PWR_ON         0x01
 192#define LLOPM_PWR_ON            0x01
 193#define RLOPM_PWR_ON    0x01
 194
 195#define INVERT_VOL(val)   (0x7f - val)
 196
 197/* Default output volume (inverted) */
 198#define DEFAULT_VOL     INVERT_VOL(0x50)
 199/* Default input volume */
 200#define DEFAULT_GAIN    0x20
 201
 202/* GPIO API */
 203enum {
 204        AIC3X_GPIO1_FUNC_DISABLED               = 0,
 205        AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC      = 1,
 206        AIC3X_GPIO1_FUNC_CLOCK_MUX              = 2,
 207        AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2         = 3,
 208        AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4         = 4,
 209        AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8         = 5,
 210        AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ      = 6,
 211        AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ          = 7,
 212        AIC3X_GPIO1_FUNC_INPUT                  = 8,
 213        AIC3X_GPIO1_FUNC_OUTPUT                 = 9,
 214        AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK     = 10,
 215        AIC3X_GPIO1_FUNC_AUDIO_WORDCLK          = 11,
 216        AIC3X_GPIO1_FUNC_BUTTON_IRQ             = 12,
 217        AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ     = 13,
 218        AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ   = 14,
 219        AIC3X_GPIO1_FUNC_ALL_IRQ                = 16
 220};
 221
 222enum {
 223        AIC3X_GPIO2_FUNC_DISABLED               = 0,
 224        AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ     = 2,
 225        AIC3X_GPIO2_FUNC_INPUT                  = 3,
 226        AIC3X_GPIO2_FUNC_OUTPUT                 = 4,
 227        AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT      = 5,
 228        AIC3X_GPIO2_FUNC_AUDIO_BITCLK           = 8,
 229        AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9,
 230        AIC3X_GPIO2_FUNC_ALL_IRQ                = 10,
 231        AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11,
 232        AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12,
 233        AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ      = 13,
 234        AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ          = 14,
 235        AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ       = 15
 236};
 237
 238void aic3x_set_gpio(struct snd_soc_codec *codec, int gpio, int state);
 239int aic3x_get_gpio(struct snd_soc_codec *codec, int gpio);
 240
 241/* headset detection / button API */
 242
 243/* The AIC3x supports detection of stereo headsets (GND + left + right signal)
 244 * and cellular headsets (GND + speaker output + microphone input).
 245 * It is recommended to enable MIC bias for this function to work properly.
 246 * For more information, please refer to the datasheet. */
 247enum {
 248        AIC3X_HEADSET_DETECT_OFF        = 0,
 249        AIC3X_HEADSET_DETECT_STEREO     = 1,
 250        AIC3X_HEADSET_DETECT_CELLULAR   = 2,
 251        AIC3X_HEADSET_DETECT_BOTH       = 3
 252};
 253
 254enum {
 255        AIC3X_HEADSET_DEBOUNCE_16MS     = 0,
 256        AIC3X_HEADSET_DEBOUNCE_32MS     = 1,
 257        AIC3X_HEADSET_DEBOUNCE_64MS     = 2,
 258        AIC3X_HEADSET_DEBOUNCE_128MS    = 3,
 259        AIC3X_HEADSET_DEBOUNCE_256MS    = 4,
 260        AIC3X_HEADSET_DEBOUNCE_512MS    = 5
 261};
 262
 263enum {
 264        AIC3X_BUTTON_DEBOUNCE_0MS       = 0,
 265        AIC3X_BUTTON_DEBOUNCE_8MS       = 1,
 266        AIC3X_BUTTON_DEBOUNCE_16MS      = 2,
 267        AIC3X_BUTTON_DEBOUNCE_32MS      = 3
 268};
 269
 270#define AIC3X_HEADSET_DETECT_ENABLED    0x80
 271#define AIC3X_HEADSET_DETECT_SHIFT      5
 272#define AIC3X_HEADSET_DETECT_MASK       3
 273#define AIC3X_HEADSET_DEBOUNCE_SHIFT    2
 274#define AIC3X_HEADSET_DEBOUNCE_MASK     7
 275#define AIC3X_BUTTON_DEBOUNCE_SHIFT     0
 276#define AIC3X_BUTTON_DEBOUNCE_MASK      3
 277
 278/* see the enums above for valid parameters to this function */
 279void aic3x_set_headset_detection(struct snd_soc_codec *codec, int detect,
 280                                 int headset_debounce, int button_debounce);
 281int aic3x_headset_detected(struct snd_soc_codec *codec);
 282int aic3x_button_pressed(struct snd_soc_codec *codec);
 283
 284struct aic3x_setup_data {
 285        unsigned int gpio_func[2];
 286};
 287
 288extern struct snd_soc_dai aic3x_dai;
 289extern struct snd_soc_codec_device soc_codec_dev_aic3x;
 290
 291#endif /* _AIC3X_H */
 292