1/* 2 * wm8903.h - WM8903 audio codec interface 3 * 4 * Copyright 2008 Wolfson Microelectronics PLC. 5 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13#ifndef _WM8903_H 14#define _WM8903_H 15 16#include <linux/i2c.h> 17 18extern struct snd_soc_dai wm8903_dai; 19extern struct snd_soc_codec_device soc_codec_dev_wm8903; 20 21#define WM8903_MCLK_DIV_2 1 22#define WM8903_CLK_SYS 2 23#define WM8903_BCLK 3 24#define WM8903_LRCLK 4 25 26/* 27 * Register values. 28 */ 29#define WM8903_SW_RESET_AND_ID 0x00 30#define WM8903_REVISION_NUMBER 0x01 31#define WM8903_BIAS_CONTROL_0 0x04 32#define WM8903_VMID_CONTROL_0 0x05 33#define WM8903_MIC_BIAS_CONTROL_0 0x06 34#define WM8903_ANALOGUE_DAC_0 0x08 35#define WM8903_ANALOGUE_ADC_0 0x0A 36#define WM8903_POWER_MANAGEMENT_0 0x0C 37#define WM8903_POWER_MANAGEMENT_1 0x0D 38#define WM8903_POWER_MANAGEMENT_2 0x0E 39#define WM8903_POWER_MANAGEMENT_3 0x0F 40#define WM8903_POWER_MANAGEMENT_4 0x10 41#define WM8903_POWER_MANAGEMENT_5 0x11 42#define WM8903_POWER_MANAGEMENT_6 0x12 43#define WM8903_CLOCK_RATES_0 0x14 44#define WM8903_CLOCK_RATES_1 0x15 45#define WM8903_CLOCK_RATES_2 0x16 46#define WM8903_AUDIO_INTERFACE_0 0x18 47#define WM8903_AUDIO_INTERFACE_1 0x19 48#define WM8903_AUDIO_INTERFACE_2 0x1A 49#define WM8903_AUDIO_INTERFACE_3 0x1B 50#define WM8903_DAC_DIGITAL_VOLUME_LEFT 0x1E 51#define WM8903_DAC_DIGITAL_VOLUME_RIGHT 0x1F 52#define WM8903_DAC_DIGITAL_0 0x20 53#define WM8903_DAC_DIGITAL_1 0x21 54#define WM8903_ADC_DIGITAL_VOLUME_LEFT 0x24 55#define WM8903_ADC_DIGITAL_VOLUME_RIGHT 0x25 56#define WM8903_ADC_DIGITAL_0 0x26 57#define WM8903_DIGITAL_MICROPHONE_0 0x27 58#define WM8903_DRC_0 0x28 59#define WM8903_DRC_1 0x29 60#define WM8903_DRC_2 0x2A 61#define WM8903_DRC_3 0x2B 62#define WM8903_ANALOGUE_LEFT_INPUT_0 0x2C 63#define WM8903_ANALOGUE_RIGHT_INPUT_0 0x2D 64#define WM8903_ANALOGUE_LEFT_INPUT_1 0x2E 65#define WM8903_ANALOGUE_RIGHT_INPUT_1 0x2F 66#define WM8903_ANALOGUE_LEFT_MIX_0 0x32 67#define WM8903_ANALOGUE_RIGHT_MIX_0 0x33 68#define WM8903_ANALOGUE_SPK_MIX_LEFT_0 0x34 69#define WM8903_ANALOGUE_SPK_MIX_LEFT_1 0x35 70#define WM8903_ANALOGUE_SPK_MIX_RIGHT_0 0x36 71#define WM8903_ANALOGUE_SPK_MIX_RIGHT_1 0x37 72#define WM8903_ANALOGUE_OUT1_LEFT 0x39 73#define WM8903_ANALOGUE_OUT1_RIGHT 0x3A 74#define WM8903_ANALOGUE_OUT2_LEFT 0x3B 75#define WM8903_ANALOGUE_OUT2_RIGHT 0x3C 76#define WM8903_ANALOGUE_OUT3_LEFT 0x3E 77#define WM8903_ANALOGUE_OUT3_RIGHT 0x3F 78#define WM8903_ANALOGUE_SPK_OUTPUT_CONTROL_0 0x41 79#define WM8903_DC_SERVO_0 0x43 80#define WM8903_DC_SERVO_2 0x45 81#define WM8903_ANALOGUE_HP_0 0x5A 82#define WM8903_ANALOGUE_LINEOUT_0 0x5E 83#define WM8903_CHARGE_PUMP_0 0x62 84#define WM8903_CLASS_W_0 0x68 85#define WM8903_WRITE_SEQUENCER_0 0x6C 86#define WM8903_WRITE_SEQUENCER_1 0x6D 87#define WM8903_WRITE_SEQUENCER_2 0x6E 88#define WM8903_WRITE_SEQUENCER_3 0x6F 89#define WM8903_WRITE_SEQUENCER_4 0x70 90#define WM8903_CONTROL_INTERFACE 0x72 91#define WM8903_GPIO_CONTROL_1 0x74 92#define WM8903_GPIO_CONTROL_2 0x75 93#define WM8903_GPIO_CONTROL_3 0x76 94#define WM8903_GPIO_CONTROL_4 0x77 95#define WM8903_GPIO_CONTROL_5 0x78 96#define WM8903_INTERRUPT_STATUS_1 0x79 97#define WM8903_INTERRUPT_STATUS_1_MASK 0x7A 98#define WM8903_INTERRUPT_POLARITY_1 0x7B 99#define WM8903_INTERRUPT_CONTROL 0x7E 100#define WM8903_CONTROL_INTERFACE_TEST_1 0x81 101#define WM8903_CHARGE_PUMP_TEST_1 0x95 102#define WM8903_CLOCK_RATE_TEST_4 0xA4 103#define WM8903_ANALOGUE_OUTPUT_BIAS_0 0xAC 104 105#define WM8903_REGISTER_COUNT 75 106#define WM8903_MAX_REGISTER 0xAC 107 108/* 109 * Field Definitions. 110 */ 111 112/* 113 * R0 (0x00) - SW Reset and ID 114 */ 115#define WM8903_SW_RESET_DEV_ID1_MASK 0xFFFF /* SW_RESET_DEV_ID1 - [15:0] */ 116#define WM8903_SW_RESET_DEV_ID1_SHIFT 0 /* SW_RESET_DEV_ID1 - [15:0] */ 117#define WM8903_SW_RESET_DEV_ID1_WIDTH 16 /* SW_RESET_DEV_ID1 - [15:0] */ 118 119/* 120 * R1 (0x01) - Revision Number 121 */ 122#define WM8903_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 123#define WM8903_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 124#define WM8903_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 125 126/* 127 * R4 (0x04) - Bias Control 0 128 */ 129#define WM8903_POBCTRL 0x0010 /* POBCTRL */ 130#define WM8903_POBCTRL_MASK 0x0010 /* POBCTRL */ 131#define WM8903_POBCTRL_SHIFT 4 /* POBCTRL */ 132#define WM8903_POBCTRL_WIDTH 1 /* POBCTRL */ 133#define WM8903_ISEL_MASK 0x000C /* ISEL - [3:2] */ 134#define WM8903_ISEL_SHIFT 2 /* ISEL - [3:2] */ 135#define WM8903_ISEL_WIDTH 2 /* ISEL - [3:2] */ 136#define WM8903_STARTUP_BIAS_ENA 0x0002 /* STARTUP_BIAS_ENA */ 137#define WM8903_STARTUP_BIAS_ENA_MASK 0x0002 /* STARTUP_BIAS_ENA */ 138#define WM8903_STARTUP_BIAS_ENA_SHIFT 1 /* STARTUP_BIAS_ENA */ 139#define WM8903_STARTUP_BIAS_ENA_WIDTH 1 /* STARTUP_BIAS_ENA */ 140#define WM8903_BIAS_ENA 0x0001 /* BIAS_ENA */ 141#define WM8903_BIAS_ENA_MASK 0x0001 /* BIAS_ENA */ 142#define WM8903_BIAS_ENA_SHIFT 0 /* BIAS_ENA */ 143#define WM8903_BIAS_ENA_WIDTH 1 /* BIAS_ENA */ 144 145/* 146 * R5 (0x05) - VMID Control 0 147 */ 148#define WM8903_VMID_TIE_ENA 0x0080 /* VMID_TIE_ENA */ 149#define WM8903_VMID_TIE_ENA_MASK 0x0080 /* VMID_TIE_ENA */ 150#define WM8903_VMID_TIE_ENA_SHIFT 7 /* VMID_TIE_ENA */ 151#define WM8903_VMID_TIE_ENA_WIDTH 1 /* VMID_TIE_ENA */ 152#define WM8903_BUFIO_ENA 0x0040 /* BUFIO_ENA */ 153#define WM8903_BUFIO_ENA_MASK 0x0040 /* BUFIO_ENA */ 154#define WM8903_BUFIO_ENA_SHIFT 6 /* BUFIO_ENA */ 155#define WM8903_BUFIO_ENA_WIDTH 1 /* BUFIO_ENA */ 156#define WM8903_VMID_IO_ENA 0x0020 /* VMID_IO_ENA */ 157#define WM8903_VMID_IO_ENA_MASK 0x0020 /* VMID_IO_ENA */ 158#define WM8903_VMID_IO_ENA_SHIFT 5 /* VMID_IO_ENA */ 159#define WM8903_VMID_IO_ENA_WIDTH 1 /* VMID_IO_ENA */ 160#define WM8903_VMID_SOFT_MASK 0x0018 /* VMID_SOFT - [4:3] */ 161#define WM8903_VMID_SOFT_SHIFT 3 /* VMID_SOFT - [4:3] */ 162#define WM8903_VMID_SOFT_WIDTH 2 /* VMID_SOFT - [4:3] */ 163#define WM8903_VMID_RES_MASK 0x0006 /* VMID_RES - [2:1] */ 164#define WM8903_VMID_RES_SHIFT 1 /* VMID_RES - [2:1] */ 165#define WM8903_VMID_RES_WIDTH 2 /* VMID_RES - [2:1] */ 166#define WM8903_VMID_BUF_ENA 0x0001 /* VMID_BUF_ENA */ 167#define WM8903_VMID_BUF_ENA_MASK 0x0001 /* VMID_BUF_ENA */ 168#define WM8903_VMID_BUF_ENA_SHIFT 0 /* VMID_BUF_ENA */ 169#define WM8903_VMID_BUF_ENA_WIDTH 1 /* VMID_BUF_ENA */ 170 171#define WM8903_VMID_RES_50K 2 172#define WM8903_VMID_RES_250K 3 173#define WM8903_VMID_RES_5K 4 174 175/* 176 * R6 (0x06) - Mic Bias Control 0 177 */ 178#define WM8903_MICDET_HYST_ENA 0x0080 /* MICDET_HYST_ENA */ 179#define WM8903_MICDET_HYST_ENA_MASK 0x0080 /* MICDET_HYST_ENA */ 180#define WM8903_MICDET_HYST_ENA_SHIFT 7 /* MICDET_HYST_ENA */ 181#define WM8903_MICDET_HYST_ENA_WIDTH 1 /* MICDET_HYST_ENA */ 182#define WM8903_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */ 183#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */ 184#define WM8903_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */ 185#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ 186#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ 187#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ 188#define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ 189#define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ 190#define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ 191#define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ 192#define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ 193#define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ 194#define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ 195#define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ 196 197/* 198 * R8 (0x08) - Analogue DAC 0 199 */ 200#define WM8903_DACBIAS_SEL_MASK 0x0018 /* DACBIAS_SEL - [4:3] */ 201#define WM8903_DACBIAS_SEL_SHIFT 3 /* DACBIAS_SEL - [4:3] */ 202#define WM8903_DACBIAS_SEL_WIDTH 2 /* DACBIAS_SEL - [4:3] */ 203#define WM8903_DACVMID_BIAS_SEL_MASK 0x0006 /* DACVMID_BIAS_SEL - [2:1] */ 204#define WM8903_DACVMID_BIAS_SEL_SHIFT 1 /* DACVMID_BIAS_SEL - [2:1] */ 205#define WM8903_DACVMID_BIAS_SEL_WIDTH 2 /* DACVMID_BIAS_SEL - [2:1] */ 206 207/* 208 * R10 (0x0A) - Analogue ADC 0 209 */ 210#define WM8903_ADC_OSR128 0x0001 /* ADC_OSR128 */ 211#define WM8903_ADC_OSR128_MASK 0x0001 /* ADC_OSR128 */ 212#define WM8903_ADC_OSR128_SHIFT 0 /* ADC_OSR128 */ 213#define WM8903_ADC_OSR128_WIDTH 1 /* ADC_OSR128 */ 214 215/* 216 * R12 (0x0C) - Power Management 0 217 */ 218#define WM8903_INL_ENA 0x0002 /* INL_ENA */ 219#define WM8903_INL_ENA_MASK 0x0002 /* INL_ENA */ 220#define WM8903_INL_ENA_SHIFT 1 /* INL_ENA */ 221#define WM8903_INL_ENA_WIDTH 1 /* INL_ENA */ 222#define WM8903_INR_ENA 0x0001 /* INR_ENA */ 223#define WM8903_INR_ENA_MASK 0x0001 /* INR_ENA */ 224#define WM8903_INR_ENA_SHIFT 0 /* INR_ENA */ 225#define WM8903_INR_ENA_WIDTH 1 /* INR_ENA */ 226 227/* 228 * R13 (0x0D) - Power Management 1 229 */ 230#define WM8903_MIXOUTL_ENA 0x0002 /* MIXOUTL_ENA */ 231#define WM8903_MIXOUTL_ENA_MASK 0x0002 /* MIXOUTL_ENA */ 232#define WM8903_MIXOUTL_ENA_SHIFT 1 /* MIXOUTL_ENA */ 233#define WM8903_MIXOUTL_ENA_WIDTH 1 /* MIXOUTL_ENA */ 234#define WM8903_MIXOUTR_ENA 0x0001 /* MIXOUTR_ENA */ 235#define WM8903_MIXOUTR_ENA_MASK 0x0001 /* MIXOUTR_ENA */ 236#define WM8903_MIXOUTR_ENA_SHIFT 0 /* MIXOUTR_ENA */ 237#define WM8903_MIXOUTR_ENA_WIDTH 1 /* MIXOUTR_ENA */ 238 239/* 240 * R14 (0x0E) - Power Management 2 241 */ 242#define WM8903_HPL_PGA_ENA 0x0002 /* HPL_PGA_ENA */ 243#define WM8903_HPL_PGA_ENA_MASK 0x0002 /* HPL_PGA_ENA */ 244#define WM8903_HPL_PGA_ENA_SHIFT 1 /* HPL_PGA_ENA */ 245#define WM8903_HPL_PGA_ENA_WIDTH 1 /* HPL_PGA_ENA */ 246#define WM8903_HPR_PGA_ENA 0x0001 /* HPR_PGA_ENA */ 247#define WM8903_HPR_PGA_ENA_MASK 0x0001 /* HPR_PGA_ENA */ 248#define WM8903_HPR_PGA_ENA_SHIFT 0 /* HPR_PGA_ENA */ 249#define WM8903_HPR_PGA_ENA_WIDTH 1 /* HPR_PGA_ENA */ 250 251/* 252 * R15 (0x0F) - Power Management 3 253 */ 254#define WM8903_LINEOUTL_PGA_ENA 0x0002 /* LINEOUTL_PGA_ENA */ 255#define WM8903_LINEOUTL_PGA_ENA_MASK 0x0002 /* LINEOUTL_PGA_ENA */ 256#define WM8903_LINEOUTL_PGA_ENA_SHIFT 1 /* LINEOUTL_PGA_ENA */ 257#define WM8903_LINEOUTL_PGA_ENA_WIDTH 1 /* LINEOUTL_PGA_ENA */ 258#define WM8903_LINEOUTR_PGA_ENA 0x0001 /* LINEOUTR_PGA_ENA */ 259#define WM8903_LINEOUTR_PGA_ENA_MASK 0x0001 /* LINEOUTR_PGA_ENA */ 260#define WM8903_LINEOUTR_PGA_ENA_SHIFT 0 /* LINEOUTR_PGA_ENA */ 261#define WM8903_LINEOUTR_PGA_ENA_WIDTH 1 /* LINEOUTR_PGA_ENA */ 262 263/* 264 * R16 (0x10) - Power Management 4 265 */ 266#define WM8903_MIXSPKL_ENA 0x0002 /* MIXSPKL_ENA */ 267#define WM8903_MIXSPKL_ENA_MASK 0x0002 /* MIXSPKL_ENA */ 268#define WM8903_MIXSPKL_ENA_SHIFT 1 /* MIXSPKL_ENA */ 269#define WM8903_MIXSPKL_ENA_WIDTH 1 /* MIXSPKL_ENA */ 270#define WM8903_MIXSPKR_ENA 0x0001 /* MIXSPKR_ENA */ 271#define WM8903_MIXSPKR_ENA_MASK 0x0001 /* MIXSPKR_ENA */ 272#define WM8903_MIXSPKR_ENA_SHIFT 0 /* MIXSPKR_ENA */ 273#define WM8903_MIXSPKR_ENA_WIDTH 1 /* MIXSPKR_ENA */ 274 275/* 276 * R17 (0x11) - Power Management 5 277 */ 278#define WM8903_SPKL_ENA 0x0002 /* SPKL_ENA */ 279#define WM8903_SPKL_ENA_MASK 0x0002 /* SPKL_ENA */ 280#define WM8903_SPKL_ENA_SHIFT 1 /* SPKL_ENA */ 281#define WM8903_SPKL_ENA_WIDTH 1 /* SPKL_ENA */ 282#define WM8903_SPKR_ENA 0x0001 /* SPKR_ENA */ 283#define WM8903_SPKR_ENA_MASK 0x0001 /* SPKR_ENA */ 284#define WM8903_SPKR_ENA_SHIFT 0 /* SPKR_ENA */ 285#define WM8903_SPKR_ENA_WIDTH 1 /* SPKR_ENA */ 286 287/* 288 * R18 (0x12) - Power Management 6 289 */ 290#define WM8903_DACL_ENA 0x0008 /* DACL_ENA */ 291#define WM8903_DACL_ENA_MASK 0x0008 /* DACL_ENA */ 292#define WM8903_DACL_ENA_SHIFT 3 /* DACL_ENA */ 293#define WM8903_DACL_ENA_WIDTH 1 /* DACL_ENA */ 294#define WM8903_DACR_ENA 0x0004 /* DACR_ENA */ 295#define WM8903_DACR_ENA_MASK 0x0004 /* DACR_ENA */ 296#define WM8903_DACR_ENA_SHIFT 2 /* DACR_ENA */ 297#define WM8903_DACR_ENA_WIDTH 1 /* DACR_ENA */ 298#define WM8903_ADCL_ENA 0x0002 /* ADCL_ENA */ 299#define WM8903_ADCL_ENA_MASK 0x0002 /* ADCL_ENA */ 300#define WM8903_ADCL_ENA_SHIFT 1 /* ADCL_ENA */ 301#define WM8903_ADCL_ENA_WIDTH 1 /* ADCL_ENA */ 302#define WM8903_ADCR_ENA 0x0001 /* ADCR_ENA */ 303#define WM8903_ADCR_ENA_MASK 0x0001 /* ADCR_ENA */ 304#define WM8903_ADCR_ENA_SHIFT 0 /* ADCR_ENA */ 305#define WM8903_ADCR_ENA_WIDTH 1 /* ADCR_ENA */ 306 307/* 308 * R20 (0x14) - Clock Rates 0 309 */ 310#define WM8903_MCLKDIV2 0x0001 /* MCLKDIV2 */ 311#define WM8903_MCLKDIV2_MASK 0x0001 /* MCLKDIV2 */ 312#define WM8903_MCLKDIV2_SHIFT 0 /* MCLKDIV2 */ 313#define WM8903_MCLKDIV2_WIDTH 1 /* MCLKDIV2 */ 314 315/* 316 * R21 (0x15) - Clock Rates 1 317 */ 318#define WM8903_CLK_SYS_RATE_MASK 0x3C00 /* CLK_SYS_RATE - [13:10] */ 319#define WM8903_CLK_SYS_RATE_SHIFT 10 /* CLK_SYS_RATE - [13:10] */ 320#define WM8903_CLK_SYS_RATE_WIDTH 4 /* CLK_SYS_RATE - [13:10] */ 321#define WM8903_CLK_SYS_MODE_MASK 0x0300 /* CLK_SYS_MODE - [9:8] */ 322#define WM8903_CLK_SYS_MODE_SHIFT 8 /* CLK_SYS_MODE - [9:8] */ 323#define WM8903_CLK_SYS_MODE_WIDTH 2 /* CLK_SYS_MODE - [9:8] */ 324#define WM8903_SAMPLE_RATE_MASK 0x000F /* SAMPLE_RATE - [3:0] */ 325#define WM8903_SAMPLE_RATE_SHIFT 0 /* SAMPLE_RATE - [3:0] */ 326#define WM8903_SAMPLE_RATE_WIDTH 4 /* SAMPLE_RATE - [3:0] */ 327 328/* 329 * R22 (0x16) - Clock Rates 2 330 */ 331#define WM8903_CLK_SYS_ENA 0x0004 /* CLK_SYS_ENA */ 332#define WM8903_CLK_SYS_ENA_MASK 0x0004 /* CLK_SYS_ENA */ 333#define WM8903_CLK_SYS_ENA_SHIFT 2 /* CLK_SYS_ENA */ 334#define WM8903_CLK_SYS_ENA_WIDTH 1 /* CLK_SYS_ENA */ 335#define WM8903_CLK_DSP_ENA 0x0002 /* CLK_DSP_ENA */ 336#define WM8903_CLK_DSP_ENA_MASK 0x0002 /* CLK_DSP_ENA */ 337#define WM8903_CLK_DSP_ENA_SHIFT 1 /* CLK_DSP_ENA */ 338#define WM8903_CLK_DSP_ENA_WIDTH 1 /* CLK_DSP_ENA */ 339#define WM8903_TO_ENA 0x0001 /* TO_ENA */ 340#define WM8903_TO_ENA_MASK 0x0001 /* TO_ENA */ 341#define WM8903_TO_ENA_SHIFT 0 /* TO_ENA */ 342#define WM8903_TO_ENA_WIDTH 1 /* TO_ENA */ 343 344/* 345 * R24 (0x18) - Audio Interface 0 346 */ 347#define WM8903_DACL_DATINV 0x1000 /* DACL_DATINV */ 348#define WM8903_DACL_DATINV_MASK 0x1000 /* DACL_DATINV */ 349#define WM8903_DACL_DATINV_SHIFT 12 /* DACL_DATINV */ 350#define WM8903_DACL_DATINV_WIDTH 1 /* DACL_DATINV */ 351#define WM8903_DACR_DATINV 0x0800 /* DACR_DATINV */ 352#define WM8903_DACR_DATINV_MASK 0x0800 /* DACR_DATINV */ 353#define WM8903_DACR_DATINV_SHIFT 11 /* DACR_DATINV */ 354#define WM8903_DACR_DATINV_WIDTH 1 /* DACR_DATINV */ 355#define WM8903_DAC_BOOST_MASK 0x0600 /* DAC_BOOST - [10:9] */ 356#define WM8903_DAC_BOOST_SHIFT 9 /* DAC_BOOST - [10:9] */ 357#define WM8903_DAC_BOOST_WIDTH 2 /* DAC_BOOST - [10:9] */ 358#define WM8903_LOOPBACK 0x0100 /* LOOPBACK */ 359#define WM8903_LOOPBACK_MASK 0x0100 /* LOOPBACK */ 360#define WM8903_LOOPBACK_SHIFT 8 /* LOOPBACK */ 361#define WM8903_LOOPBACK_WIDTH 1 /* LOOPBACK */ 362#define WM8903_AIFADCL_SRC 0x0080 /* AIFADCL_SRC */ 363#define WM8903_AIFADCL_SRC_MASK 0x0080 /* AIFADCL_SRC */ 364#define WM8903_AIFADCL_SRC_SHIFT 7 /* AIFADCL_SRC */ 365#define WM8903_AIFADCL_SRC_WIDTH 1 /* AIFADCL_SRC */ 366#define WM8903_AIFADCR_SRC 0x0040 /* AIFADCR_SRC */ 367#define WM8903_AIFADCR_SRC_MASK 0x0040 /* AIFADCR_SRC */ 368#define WM8903_AIFADCR_SRC_SHIFT 6 /* AIFADCR_SRC */ 369#define WM8903_AIFADCR_SRC_WIDTH 1 /* AIFADCR_SRC */ 370#define WM8903_AIFDACL_SRC 0x0020 /* AIFDACL_SRC */ 371#define WM8903_AIFDACL_SRC_MASK 0x0020 /* AIFDACL_SRC */ 372#define WM8903_AIFDACL_SRC_SHIFT 5 /* AIFDACL_SRC */ 373#define WM8903_AIFDACL_SRC_WIDTH 1 /* AIFDACL_SRC */ 374#define WM8903_AIFDACR_SRC 0x0010 /* AIFDACR_SRC */ 375#define WM8903_AIFDACR_SRC_MASK 0x0010 /* AIFDACR_SRC */ 376#define WM8903_AIFDACR_SRC_SHIFT 4 /* AIFDACR_SRC */ 377#define WM8903_AIFDACR_SRC_WIDTH 1 /* AIFDACR_SRC */ 378#define WM8903_ADC_COMP 0x0008 /* ADC_COMP */ 379#define WM8903_ADC_COMP_MASK 0x0008 /* ADC_COMP */ 380#define WM8903_ADC_COMP_SHIFT 3 /* ADC_COMP */ 381#define WM8903_ADC_COMP_WIDTH 1 /* ADC_COMP */ 382#define WM8903_ADC_COMPMODE 0x0004 /* ADC_COMPMODE */ 383#define WM8903_ADC_COMPMODE_MASK 0x0004 /* ADC_COMPMODE */ 384#define WM8903_ADC_COMPMODE_SHIFT 2 /* ADC_COMPMODE */ 385#define WM8903_ADC_COMPMODE_WIDTH 1 /* ADC_COMPMODE */ 386#define WM8903_DAC_COMP 0x0002 /* DAC_COMP */ 387#define WM8903_DAC_COMP_MASK 0x0002 /* DAC_COMP */ 388#define WM8903_DAC_COMP_SHIFT 1 /* DAC_COMP */ 389#define WM8903_DAC_COMP_WIDTH 1 /* DAC_COMP */ 390#define WM8903_DAC_COMPMODE 0x0001 /* DAC_COMPMODE */ 391#define WM8903_DAC_COMPMODE_MASK 0x0001 /* DAC_COMPMODE */ 392#define WM8903_DAC_COMPMODE_SHIFT 0 /* DAC_COMPMODE */ 393#define WM8903_DAC_COMPMODE_WIDTH 1 /* DAC_COMPMODE */ 394 395/* 396 * R25 (0x19) - Audio Interface 1 397 */ 398#define WM8903_AIFDAC_TDM 0x2000 /* AIFDAC_TDM */ 399#define WM8903_AIFDAC_TDM_MASK 0x2000 /* AIFDAC_TDM */ 400#define WM8903_AIFDAC_TDM_SHIFT 13 /* AIFDAC_TDM */ 401#define WM8903_AIFDAC_TDM_WIDTH 1 /* AIFDAC_TDM */ 402#define WM8903_AIFDAC_TDM_CHAN 0x1000 /* AIFDAC_TDM_CHAN */ 403#define WM8903_AIFDAC_TDM_CHAN_MASK 0x1000 /* AIFDAC_TDM_CHAN */ 404#define WM8903_AIFDAC_TDM_CHAN_SHIFT 12 /* AIFDAC_TDM_CHAN */ 405#define WM8903_AIFDAC_TDM_CHAN_WIDTH 1 /* AIFDAC_TDM_CHAN */ 406#define WM8903_AIFADC_TDM 0x0800 /* AIFADC_TDM */ 407#define WM8903_AIFADC_TDM_MASK 0x0800 /* AIFADC_TDM */ 408#define WM8903_AIFADC_TDM_SHIFT 11 /* AIFADC_TDM */ 409#define WM8903_AIFADC_TDM_WIDTH 1 /* AIFADC_TDM */ 410#define WM8903_AIFADC_TDM_CHAN 0x0400 /* AIFADC_TDM_CHAN */ 411#define WM8903_AIFADC_TDM_CHAN_MASK 0x0400 /* AIFADC_TDM_CHAN */ 412#define WM8903_AIFADC_TDM_CHAN_SHIFT 10 /* AIFADC_TDM_CHAN */ 413#define WM8903_AIFADC_TDM_CHAN_WIDTH 1 /* AIFADC_TDM_CHAN */ 414#define WM8903_LRCLK_DIR 0x0200 /* LRCLK_DIR */ 415#define WM8903_LRCLK_DIR_MASK 0x0200 /* LRCLK_DIR */ 416#define WM8903_LRCLK_DIR_SHIFT 9 /* LRCLK_DIR */ 417#define WM8903_LRCLK_DIR_WIDTH 1 /* LRCLK_DIR */ 418#define WM8903_AIF_BCLK_INV 0x0080 /* AIF_BCLK_INV */ 419#define WM8903_AIF_BCLK_INV_MASK 0x0080 /* AIF_BCLK_INV */ 420#define WM8903_AIF_BCLK_INV_SHIFT 7 /* AIF_BCLK_INV */ 421#define WM8903_AIF_BCLK_INV_WIDTH 1 /* AIF_BCLK_INV */ 422#define WM8903_BCLK_DIR 0x0040 /* BCLK_DIR */ 423#define WM8903_BCLK_DIR_MASK 0x0040 /* BCLK_DIR */ 424#define WM8903_BCLK_DIR_SHIFT 6 /* BCLK_DIR */ 425#define WM8903_BCLK_DIR_WIDTH 1 /* BCLK_DIR */ 426#define WM8903_AIF_LRCLK_INV 0x0010 /* AIF_LRCLK_INV */ 427#define WM8903_AIF_LRCLK_INV_MASK 0x0010 /* AIF_LRCLK_INV */ 428#define WM8903_AIF_LRCLK_INV_SHIFT 4 /* AIF_LRCLK_INV */ 429#define WM8903_AIF_LRCLK_INV_WIDTH 1 /* AIF_LRCLK_INV */ 430#define WM8903_AIF_WL_MASK 0x000C /* AIF_WL - [3:2] */ 431#define WM8903_AIF_WL_SHIFT 2 /* AIF_WL - [3:2] */ 432#define WM8903_AIF_WL_WIDTH 2 /* AIF_WL - [3:2] */ 433#define WM8903_AIF_FMT_MASK 0x0003 /* AIF_FMT - [1:0] */ 434#define WM8903_AIF_FMT_SHIFT 0 /* AIF_FMT - [1:0] */ 435#define WM8903_AIF_FMT_WIDTH 2 /* AIF_FMT - [1:0] */ 436 437/* 438 * R26 (0x1A) - Audio Interface 2 439 */ 440#define WM8903_BCLK_DIV_MASK 0x001F /* BCLK_DIV - [4:0] */ 441#define WM8903_BCLK_DIV_SHIFT 0 /* BCLK_DIV - [4:0] */ 442#define WM8903_BCLK_DIV_WIDTH 5 /* BCLK_DIV - [4:0] */ 443 444/* 445 * R27 (0x1B) - Audio Interface 3 446 */ 447#define WM8903_LRCLK_RATE_MASK 0x07FF /* LRCLK_RATE - [10:0] */ 448#define WM8903_LRCLK_RATE_SHIFT 0 /* LRCLK_RATE - [10:0] */ 449#define WM8903_LRCLK_RATE_WIDTH 11 /* LRCLK_RATE - [10:0] */ 450 451/* 452 * R30 (0x1E) - DAC Digital Volume Left 453 */ 454#define WM8903_DACVU 0x0100 /* DACVU */ 455#define WM8903_DACVU_MASK 0x0100 /* DACVU */ 456#define WM8903_DACVU_SHIFT 8 /* DACVU */ 457#define WM8903_DACVU_WIDTH 1 /* DACVU */ 458#define WM8903_DACL_VOL_MASK 0x00FF /* DACL_VOL - [7:0] */ 459#define WM8903_DACL_VOL_SHIFT 0 /* DACL_VOL - [7:0] */ 460#define WM8903_DACL_VOL_WIDTH 8 /* DACL_VOL - [7:0] */ 461 462/* 463 * R31 (0x1F) - DAC Digital Volume Right 464 */ 465#define WM8903_DACVU 0x0100 /* DACVU */ 466#define WM8903_DACVU_MASK 0x0100 /* DACVU */ 467#define WM8903_DACVU_SHIFT 8 /* DACVU */ 468#define WM8903_DACVU_WIDTH 1 /* DACVU */ 469#define WM8903_DACR_VOL_MASK 0x00FF /* DACR_VOL - [7:0] */ 470#define WM8903_DACR_VOL_SHIFT 0 /* DACR_VOL - [7:0] */ 471#define WM8903_DACR_VOL_WIDTH 8 /* DACR_VOL - [7:0] */ 472 473/* 474 * R32 (0x20) - DAC Digital 0 475 */ 476#define WM8903_ADCL_DAC_SVOL_MASK 0x0F00 /* ADCL_DAC_SVOL - [11:8] */ 477#define WM8903_ADCL_DAC_SVOL_SHIFT 8 /* ADCL_DAC_SVOL - [11:8] */ 478#define WM8903_ADCL_DAC_SVOL_WIDTH 4 /* ADCL_DAC_SVOL - [11:8] */ 479#define WM8903_ADCR_DAC_SVOL_MASK 0x00F0 /* ADCR_DAC_SVOL - [7:4] */ 480#define WM8903_ADCR_DAC_SVOL_SHIFT 4 /* ADCR_DAC_SVOL - [7:4] */ 481#define WM8903_ADCR_DAC_SVOL_WIDTH 4 /* ADCR_DAC_SVOL - [7:4] */ 482#define WM8903_ADC_TO_DACL_MASK 0x000C /* ADC_TO_DACL - [3:2] */ 483#define WM8903_ADC_TO_DACL_SHIFT 2 /* ADC_TO_DACL - [3:2] */ 484#define WM8903_ADC_TO_DACL_WIDTH 2 /* ADC_TO_DACL - [3:2] */ 485#define WM8903_ADC_TO_DACR_MASK 0x0003 /* ADC_TO_DACR - [1:0] */ 486#define WM8903_ADC_TO_DACR_SHIFT 0 /* ADC_TO_DACR - [1:0] */ 487#define WM8903_ADC_TO_DACR_WIDTH 2 /* ADC_TO_DACR - [1:0] */ 488 489/* 490 * R33 (0x21) - DAC Digital 1 491 */ 492#define WM8903_DAC_MONO 0x1000 /* DAC_MONO */ 493#define WM8903_DAC_MONO_MASK 0x1000 /* DAC_MONO */ 494#define WM8903_DAC_MONO_SHIFT 12 /* DAC_MONO */ 495#define WM8903_DAC_MONO_WIDTH 1 /* DAC_MONO */ 496#define WM8903_DAC_SB_FILT 0x0800 /* DAC_SB_FILT */ 497#define WM8903_DAC_SB_FILT_MASK 0x0800 /* DAC_SB_FILT */ 498#define WM8903_DAC_SB_FILT_SHIFT 11 /* DAC_SB_FILT */ 499#define WM8903_DAC_SB_FILT_WIDTH 1 /* DAC_SB_FILT */ 500#define WM8903_DAC_MUTERATE 0x0400 /* DAC_MUTERATE */ 501#define WM8903_DAC_MUTERATE_MASK 0x0400 /* DAC_MUTERATE */ 502#define WM8903_DAC_MUTERATE_SHIFT 10 /* DAC_MUTERATE */ 503#define WM8903_DAC_MUTERATE_WIDTH 1 /* DAC_MUTERATE */ 504#define WM8903_DAC_MUTEMODE 0x0200 /* DAC_MUTEMODE */ 505#define WM8903_DAC_MUTEMODE_MASK 0x0200 /* DAC_MUTEMODE */ 506#define WM8903_DAC_MUTEMODE_SHIFT 9 /* DAC_MUTEMODE */ 507#define WM8903_DAC_MUTEMODE_WIDTH 1 /* DAC_MUTEMODE */ 508#define WM8903_DAC_MUTE 0x0008 /* DAC_MUTE */ 509#define WM8903_DAC_MUTE_MASK 0x0008 /* DAC_MUTE */ 510#define WM8903_DAC_MUTE_SHIFT 3 /* DAC_MUTE */ 511#define WM8903_DAC_MUTE_WIDTH 1 /* DAC_MUTE */ 512#define WM8903_DEEMPH_MASK 0x0006 /* DEEMPH - [2:1] */ 513#define WM8903_DEEMPH_SHIFT 1 /* DEEMPH - [2:1] */ 514#define WM8903_DEEMPH_WIDTH 2 /* DEEMPH - [2:1] */ 515 516/* 517 * R36 (0x24) - ADC Digital Volume Left 518 */ 519#define WM8903_ADCVU 0x0100 /* ADCVU */ 520#define WM8903_ADCVU_MASK 0x0100 /* ADCVU */ 521#define WM8903_ADCVU_SHIFT 8 /* ADCVU */ 522#define WM8903_ADCVU_WIDTH 1 /* ADCVU */ 523#define WM8903_ADCL_VOL_MASK 0x00FF /* ADCL_VOL - [7:0] */ 524#define WM8903_ADCL_VOL_SHIFT 0 /* ADCL_VOL - [7:0] */ 525#define WM8903_ADCL_VOL_WIDTH 8 /* ADCL_VOL - [7:0] */ 526 527/* 528 * R37 (0x25) - ADC Digital Volume Right 529 */ 530#define WM8903_ADCVU 0x0100 /* ADCVU */ 531#define WM8903_ADCVU_MASK 0x0100 /* ADCVU */ 532#define WM8903_ADCVU_SHIFT 8 /* ADCVU */ 533#define WM8903_ADCVU_WIDTH 1 /* ADCVU */ 534#define WM8903_ADCR_VOL_MASK 0x00FF /* ADCR_VOL - [7:0] */ 535#define WM8903_ADCR_VOL_SHIFT 0 /* ADCR_VOL - [7:0] */ 536#define WM8903_ADCR_VOL_WIDTH 8 /* ADCR_VOL - [7:0] */ 537 538/* 539 * R38 (0x26) - ADC Digital 0 540 */ 541#define WM8903_ADC_HPF_CUT_MASK 0x0060 /* ADC_HPF_CUT - [6:5] */ 542#define WM8903_ADC_HPF_CUT_SHIFT 5 /* ADC_HPF_CUT - [6:5] */ 543#define WM8903_ADC_HPF_CUT_WIDTH 2 /* ADC_HPF_CUT - [6:5] */ 544#define WM8903_ADC_HPF_ENA 0x0010 /* ADC_HPF_ENA */ 545#define WM8903_ADC_HPF_ENA_MASK 0x0010 /* ADC_HPF_ENA */ 546#define WM8903_ADC_HPF_ENA_SHIFT 4 /* ADC_HPF_ENA */ 547#define WM8903_ADC_HPF_ENA_WIDTH 1 /* ADC_HPF_ENA */ 548#define WM8903_ADCL_DATINV 0x0002 /* ADCL_DATINV */ 549#define WM8903_ADCL_DATINV_MASK 0x0002 /* ADCL_DATINV */ 550#define WM8903_ADCL_DATINV_SHIFT 1 /* ADCL_DATINV */ 551#define WM8903_ADCL_DATINV_WIDTH 1 /* ADCL_DATINV */ 552#define WM8903_ADCR_DATINV 0x0001 /* ADCR_DATINV */ 553#define WM8903_ADCR_DATINV_MASK 0x0001 /* ADCR_DATINV */ 554#define WM8903_ADCR_DATINV_SHIFT 0 /* ADCR_DATINV */ 555#define WM8903_ADCR_DATINV_WIDTH 1 /* ADCR_DATINV */ 556 557/* 558 * R39 (0x27) - Digital Microphone 0 559 */ 560#define WM8903_DIGMIC_MODE_SEL 0x0100 /* DIGMIC_MODE_SEL */ 561#define WM8903_DIGMIC_MODE_SEL_MASK 0x0100 /* DIGMIC_MODE_SEL */ 562#define WM8903_DIGMIC_MODE_SEL_SHIFT 8 /* DIGMIC_MODE_SEL */ 563#define WM8903_DIGMIC_MODE_SEL_WIDTH 1 /* DIGMIC_MODE_SEL */ 564#define WM8903_DIGMIC_CLK_SEL_L_MASK 0x00C0 /* DIGMIC_CLK_SEL_L - [7:6] */ 565#define WM8903_DIGMIC_CLK_SEL_L_SHIFT 6 /* DIGMIC_CLK_SEL_L - [7:6] */ 566#define WM8903_DIGMIC_CLK_SEL_L_WIDTH 2 /* DIGMIC_CLK_SEL_L - [7:6] */ 567#define WM8903_DIGMIC_CLK_SEL_R_MASK 0x0030 /* DIGMIC_CLK_SEL_R - [5:4] */ 568#define WM8903_DIGMIC_CLK_SEL_R_SHIFT 4 /* DIGMIC_CLK_SEL_R - [5:4] */ 569#define WM8903_DIGMIC_CLK_SEL_R_WIDTH 2 /* DIGMIC_CLK_SEL_R - [5:4] */ 570#define WM8903_DIGMIC_CLK_SEL_RT_MASK 0x000C /* DIGMIC_CLK_SEL_RT - [3:2] */ 571#define WM8903_DIGMIC_CLK_SEL_RT_SHIFT 2 /* DIGMIC_CLK_SEL_RT - [3:2] */ 572#define WM8903_DIGMIC_CLK_SEL_RT_WIDTH 2 /* DIGMIC_CLK_SEL_RT - [3:2] */ 573#define WM8903_DIGMIC_CLK_SEL_MASK 0x0003 /* DIGMIC_CLK_SEL - [1:0] */ 574#define WM8903_DIGMIC_CLK_SEL_SHIFT 0 /* DIGMIC_CLK_SEL - [1:0] */ 575#define WM8903_DIGMIC_CLK_SEL_WIDTH 2 /* DIGMIC_CLK_SEL - [1:0] */ 576 577/* 578 * R40 (0x28) - DRC 0 579 */ 580#define WM8903_DRC_ENA 0x8000 /* DRC_ENA */ 581#define WM8903_DRC_ENA_MASK 0x8000 /* DRC_ENA */ 582#define WM8903_DRC_ENA_SHIFT 15 /* DRC_ENA */ 583#define WM8903_DRC_ENA_WIDTH 1 /* DRC_ENA */ 584#define WM8903_DRC_THRESH_HYST_MASK 0x1800 /* DRC_THRESH_HYST - [12:11] */ 585#define WM8903_DRC_THRESH_HYST_SHIFT 11 /* DRC_THRESH_HYST - [12:11] */ 586#define WM8903_DRC_THRESH_HYST_WIDTH 2 /* DRC_THRESH_HYST - [12:11] */ 587#define WM8903_DRC_STARTUP_GAIN_MASK 0x07C0 /* DRC_STARTUP_GAIN - [10:6] */ 588#define WM8903_DRC_STARTUP_GAIN_SHIFT 6 /* DRC_STARTUP_GAIN - [10:6] */ 589#define WM8903_DRC_STARTUP_GAIN_WIDTH 5 /* DRC_STARTUP_GAIN - [10:6] */ 590#define WM8903_DRC_FF_DELAY 0x0020 /* DRC_FF_DELAY */ 591#define WM8903_DRC_FF_DELAY_MASK 0x0020 /* DRC_FF_DELAY */ 592#define WM8903_DRC_FF_DELAY_SHIFT 5 /* DRC_FF_DELAY */ 593#define WM8903_DRC_FF_DELAY_WIDTH 1 /* DRC_FF_DELAY */ 594#define WM8903_DRC_SMOOTH_ENA 0x0008 /* DRC_SMOOTH_ENA */ 595#define WM8903_DRC_SMOOTH_ENA_MASK 0x0008 /* DRC_SMOOTH_ENA */ 596#define WM8903_DRC_SMOOTH_ENA_SHIFT 3 /* DRC_SMOOTH_ENA */ 597#define WM8903_DRC_SMOOTH_ENA_WIDTH 1 /* DRC_SMOOTH_ENA */ 598#define WM8903_DRC_QR_ENA 0x0004 /* DRC_QR_ENA */ 599#define WM8903_DRC_QR_ENA_MASK 0x0004 /* DRC_QR_ENA */ 600#define WM8903_DRC_QR_ENA_SHIFT 2 /* DRC_QR_ENA */ 601#define WM8903_DRC_QR_ENA_WIDTH 1 /* DRC_QR_ENA */ 602#define WM8903_DRC_ANTICLIP_ENA 0x0002 /* DRC_ANTICLIP_ENA */ 603#define WM8903_DRC_ANTICLIP_ENA_MASK 0x0002 /* DRC_ANTICLIP_ENA */ 604#define WM8903_DRC_ANTICLIP_ENA_SHIFT 1 /* DRC_ANTICLIP_ENA */ 605#define WM8903_DRC_ANTICLIP_ENA_WIDTH 1 /* DRC_ANTICLIP_ENA */ 606#define WM8903_DRC_HYST_ENA 0x0001 /* DRC_HYST_ENA */ 607#define WM8903_DRC_HYST_ENA_MASK 0x0001 /* DRC_HYST_ENA */ 608#define WM8903_DRC_HYST_ENA_SHIFT 0 /* DRC_HYST_ENA */ 609#define WM8903_DRC_HYST_ENA_WIDTH 1 /* DRC_HYST_ENA */ 610 611/* 612 * R41 (0x29) - DRC 1 613 */ 614#define WM8903_DRC_ATTACK_RATE_MASK 0xF000 /* DRC_ATTACK_RATE - [15:12] */ 615#define WM8903_DRC_ATTACK_RATE_SHIFT 12 /* DRC_ATTACK_RATE - [15:12] */ 616#define WM8903_DRC_ATTACK_RATE_WIDTH 4 /* DRC_ATTACK_RATE - [15:12] */ 617#define WM8903_DRC_DECAY_RATE_MASK 0x0F00 /* DRC_DECAY_RATE - [11:8] */ 618#define WM8903_DRC_DECAY_RATE_SHIFT 8 /* DRC_DECAY_RATE - [11:8] */ 619#define WM8903_DRC_DECAY_RATE_WIDTH 4 /* DRC_DECAY_RATE - [11:8] */ 620#define WM8903_DRC_THRESH_QR_MASK 0x00C0 /* DRC_THRESH_QR - [7:6] */ 621#define WM8903_DRC_THRESH_QR_SHIFT 6 /* DRC_THRESH_QR - [7:6] */ 622#define WM8903_DRC_THRESH_QR_WIDTH 2 /* DRC_THRESH_QR - [7:6] */ 623#define WM8903_DRC_RATE_QR_MASK 0x0030 /* DRC_RATE_QR - [5:4] */ 624#define WM8903_DRC_RATE_QR_SHIFT 4 /* DRC_RATE_QR - [5:4] */ 625#define WM8903_DRC_RATE_QR_WIDTH 2 /* DRC_RATE_QR - [5:4] */ 626#define WM8903_DRC_MINGAIN_MASK 0x000C /* DRC_MINGAIN - [3:2] */ 627#define WM8903_DRC_MINGAIN_SHIFT 2 /* DRC_MINGAIN - [3:2] */ 628#define WM8903_DRC_MINGAIN_WIDTH 2 /* DRC_MINGAIN - [3:2] */ 629#define WM8903_DRC_MAXGAIN_MASK 0x0003 /* DRC_MAXGAIN - [1:0] */ 630#define WM8903_DRC_MAXGAIN_SHIFT 0 /* DRC_MAXGAIN - [1:0] */ 631#define WM8903_DRC_MAXGAIN_WIDTH 2 /* DRC_MAXGAIN - [1:0] */ 632 633/* 634 * R42 (0x2A) - DRC 2 635 */ 636#define WM8903_DRC_R0_SLOPE_COMP_MASK 0x0038 /* DRC_R0_SLOPE_COMP - [5:3] */ 637#define WM8903_DRC_R0_SLOPE_COMP_SHIFT 3 /* DRC_R0_SLOPE_COMP - [5:3] */ 638#define WM8903_DRC_R0_SLOPE_COMP_WIDTH 3 /* DRC_R0_SLOPE_COMP - [5:3] */ 639#define WM8903_DRC_R1_SLOPE_COMP_MASK 0x0007 /* DRC_R1_SLOPE_COMP - [2:0] */ 640#define WM8903_DRC_R1_SLOPE_COMP_SHIFT 0 /* DRC_R1_SLOPE_COMP - [2:0] */ 641#define WM8903_DRC_R1_SLOPE_COMP_WIDTH 3 /* DRC_R1_SLOPE_COMP - [2:0] */ 642 643/* 644 * R43 (0x2B) - DRC 3 645 */ 646#define WM8903_DRC_THRESH_COMP_MASK 0x07E0 /* DRC_THRESH_COMP - [10:5] */ 647#define WM8903_DRC_THRESH_COMP_SHIFT 5 /* DRC_THRESH_COMP - [10:5] */ 648#define WM8903_DRC_THRESH_COMP_WIDTH 6 /* DRC_THRESH_COMP - [10:5] */ 649#define WM8903_DRC_AMP_COMP_MASK 0x001F /* DRC_AMP_COMP - [4:0] */ 650#define WM8903_DRC_AMP_COMP_SHIFT 0 /* DRC_AMP_COMP - [4:0] */ 651#define WM8903_DRC_AMP_COMP_WIDTH 5 /* DRC_AMP_COMP - [4:0] */ 652 653/* 654 * R44 (0x2C) - Analogue Left Input 0 655 */ 656#define WM8903_LINMUTE 0x0080 /* LINMUTE */ 657#define WM8903_LINMUTE_MASK 0x0080 /* LINMUTE */ 658#define WM8903_LINMUTE_SHIFT 7 /* LINMUTE */ 659#define WM8903_LINMUTE_WIDTH 1 /* LINMUTE */ 660#define WM8903_LIN_VOL_MASK 0x001F /* LIN_VOL - [4:0] */ 661#define WM8903_LIN_VOL_SHIFT 0 /* LIN_VOL - [4:0] */ 662#define WM8903_LIN_VOL_WIDTH 5 /* LIN_VOL - [4:0] */ 663 664/* 665 * R45 (0x2D) - Analogue Right Input 0 666 */ 667#define WM8903_RINMUTE 0x0080 /* RINMUTE */ 668#define WM8903_RINMUTE_MASK 0x0080 /* RINMUTE */ 669#define WM8903_RINMUTE_SHIFT 7 /* RINMUTE */ 670#define WM8903_RINMUTE_WIDTH 1 /* RINMUTE */ 671#define WM8903_RIN_VOL_MASK 0x001F /* RIN_VOL - [4:0] */ 672#define WM8903_RIN_VOL_SHIFT 0 /* RIN_VOL - [4:0] */ 673#define WM8903_RIN_VOL_WIDTH 5 /* RIN_VOL - [4:0] */ 674 675/* 676 * R46 (0x2E) - Analogue Left Input 1 677 */ 678#define WM8903_INL_CM_ENA 0x0040 /* INL_CM_ENA */ 679#define WM8903_INL_CM_ENA_MASK 0x0040 /* INL_CM_ENA */ 680#define WM8903_INL_CM_ENA_SHIFT 6 /* INL_CM_ENA */ 681#define WM8903_INL_CM_ENA_WIDTH 1 /* INL_CM_ENA */ 682#define WM8903_L_IP_SEL_N_MASK 0x0030 /* L_IP_SEL_N - [5:4] */ 683#define WM8903_L_IP_SEL_N_SHIFT 4 /* L_IP_SEL_N - [5:4] */ 684#define WM8903_L_IP_SEL_N_WIDTH 2 /* L_IP_SEL_N - [5:4] */ 685#define WM8903_L_IP_SEL_P_MASK 0x000C /* L_IP_SEL_P - [3:2] */ 686#define WM8903_L_IP_SEL_P_SHIFT 2 /* L_IP_SEL_P - [3:2] */ 687#define WM8903_L_IP_SEL_P_WIDTH 2 /* L_IP_SEL_P - [3:2] */ 688#define WM8903_L_MODE_MASK 0x0003 /* L_MODE - [1:0] */ 689#define WM8903_L_MODE_SHIFT 0 /* L_MODE - [1:0] */ 690#define WM8903_L_MODE_WIDTH 2 /* L_MODE - [1:0] */ 691 692/* 693 * R47 (0x2F) - Analogue Right Input 1 694 */ 695#define WM8903_INR_CM_ENA 0x0040 /* INR_CM_ENA */ 696#define WM8903_INR_CM_ENA_MASK 0x0040 /* INR_CM_ENA */ 697#define WM8903_INR_CM_ENA_SHIFT 6 /* INR_CM_ENA */ 698#define WM8903_INR_CM_ENA_WIDTH 1 /* INR_CM_ENA */ 699#define WM8903_R_IP_SEL_N_MASK 0x0030 /* R_IP_SEL_N - [5:4] */ 700#define WM8903_R_IP_SEL_N_SHIFT 4 /* R_IP_SEL_N - [5:4] */ 701#define WM8903_R_IP_SEL_N_WIDTH 2 /* R_IP_SEL_N - [5:4] */ 702#define WM8903_R_IP_SEL_P_MASK 0x000C /* R_IP_SEL_P - [3:2] */ 703#define WM8903_R_IP_SEL_P_SHIFT 2 /* R_IP_SEL_P - [3:2] */ 704#define WM8903_R_IP_SEL_P_WIDTH 2 /* R_IP_SEL_P - [3:2] */ 705#define WM8903_R_MODE_MASK 0x0003 /* R_MODE - [1:0] */ 706#define WM8903_R_MODE_SHIFT 0 /* R_MODE - [1:0] */ 707#define WM8903_R_MODE_WIDTH 2 /* R_MODE - [1:0] */ 708 709/* 710 * R50 (0x32) - Analogue Left Mix 0 711 */ 712#define WM8903_DACL_TO_MIXOUTL 0x0008 /* DACL_TO_MIXOUTL */ 713#define WM8903_DACL_TO_MIXOUTL_MASK 0x0008 /* DACL_TO_MIXOUTL */ 714#define WM8903_DACL_TO_MIXOUTL_SHIFT 3 /* DACL_TO_MIXOUTL */ 715#define WM8903_DACL_TO_MIXOUTL_WIDTH 1 /* DACL_TO_MIXOUTL */ 716#define WM8903_DACR_TO_MIXOUTL 0x0004 /* DACR_TO_MIXOUTL */ 717#define WM8903_DACR_TO_MIXOUTL_MASK 0x0004 /* DACR_TO_MIXOUTL */ 718#define WM8903_DACR_TO_MIXOUTL_SHIFT 2 /* DACR_TO_MIXOUTL */ 719#define WM8903_DACR_TO_MIXOUTL_WIDTH 1 /* DACR_TO_MIXOUTL */ 720#define WM8903_BYPASSL_TO_MIXOUTL 0x0002 /* BYPASSL_TO_MIXOUTL */ 721#define WM8903_BYPASSL_TO_MIXOUTL_MASK 0x0002 /* BYPASSL_TO_MIXOUTL */ 722#define WM8903_BYPASSL_TO_MIXOUTL_SHIFT 1 /* BYPASSL_TO_MIXOUTL */ 723#define WM8903_BYPASSL_TO_MIXOUTL_WIDTH 1 /* BYPASSL_TO_MIXOUTL */ 724#define WM8903_BYPASSR_TO_MIXOUTL 0x0001 /* BYPASSR_TO_MIXOUTL */ 725#define WM8903_BYPASSR_TO_MIXOUTL_MASK 0x0001 /* BYPASSR_TO_MIXOUTL */ 726#define WM8903_BYPASSR_TO_MIXOUTL_SHIFT 0 /* BYPASSR_TO_MIXOUTL */ 727#define WM8903_BYPASSR_TO_MIXOUTL_WIDTH 1 /* BYPASSR_TO_MIXOUTL */ 728 729/* 730 * R51 (0x33) - Analogue Right Mix 0 731 */ 732#define WM8903_DACL_TO_MIXOUTR 0x0008 /* DACL_TO_MIXOUTR */ 733#define WM8903_DACL_TO_MIXOUTR_MASK 0x0008 /* DACL_TO_MIXOUTR */ 734#define WM8903_DACL_TO_MIXOUTR_SHIFT 3 /* DACL_TO_MIXOUTR */ 735#define WM8903_DACL_TO_MIXOUTR_WIDTH 1 /* DACL_TO_MIXOUTR */ 736#define WM8903_DACR_TO_MIXOUTR 0x0004 /* DACR_TO_MIXOUTR */ 737#define WM8903_DACR_TO_MIXOUTR_MASK 0x0004 /* DACR_TO_MIXOUTR */ 738#define WM8903_DACR_TO_MIXOUTR_SHIFT 2 /* DACR_TO_MIXOUTR */ 739#define WM8903_DACR_TO_MIXOUTR_WIDTH 1 /* DACR_TO_MIXOUTR */ 740#define WM8903_BYPASSL_TO_MIXOUTR 0x0002 /* BYPASSL_TO_MIXOUTR */ 741#define WM8903_BYPASSL_TO_MIXOUTR_MASK 0x0002 /* BYPASSL_TO_MIXOUTR */ 742#define WM8903_BYPASSL_TO_MIXOUTR_SHIFT 1 /* BYPASSL_TO_MIXOUTR */ 743#define WM8903_BYPASSL_TO_MIXOUTR_WIDTH 1 /* BYPASSL_TO_MIXOUTR */ 744#define WM8903_BYPASSR_TO_MIXOUTR 0x0001 /* BYPASSR_TO_MIXOUTR */ 745#define WM8903_BYPASSR_TO_MIXOUTR_MASK 0x0001 /* BYPASSR_TO_MIXOUTR */ 746#define WM8903_BYPASSR_TO_MIXOUTR_SHIFT 0 /* BYPASSR_TO_MIXOUTR */ 747#define WM8903_BYPASSR_TO_MIXOUTR_WIDTH 1 /* BYPASSR_TO_MIXOUTR */ 748 749/* 750 * R52 (0x34) - Analogue Spk Mix Left 0 751 */ 752#define WM8903_DACL_TO_MIXSPKL 0x0008 /* DACL_TO_MIXSPKL */ 753#define WM8903_DACL_TO_MIXSPKL_MASK 0x0008 /* DACL_TO_MIXSPKL */ 754#define WM8903_DACL_TO_MIXSPKL_SHIFT 3 /* DACL_TO_MIXSPKL */ 755#define WM8903_DACL_TO_MIXSPKL_WIDTH 1 /* DACL_TO_MIXSPKL */ 756#define WM8903_DACR_TO_MIXSPKL 0x0004 /* DACR_TO_MIXSPKL */ 757#define WM8903_DACR_TO_MIXSPKL_MASK 0x0004 /* DACR_TO_MIXSPKL */ 758#define WM8903_DACR_TO_MIXSPKL_SHIFT 2 /* DACR_TO_MIXSPKL */ 759#define WM8903_DACR_TO_MIXSPKL_WIDTH 1 /* DACR_TO_MIXSPKL */ 760#define WM8903_BYPASSL_TO_MIXSPKL 0x0002 /* BYPASSL_TO_MIXSPKL */ 761#define WM8903_BYPASSL_TO_MIXSPKL_MASK 0x0002 /* BYPASSL_TO_MIXSPKL */ 762#define WM8903_BYPASSL_TO_MIXSPKL_SHIFT 1 /* BYPASSL_TO_MIXSPKL */ 763#define WM8903_BYPASSL_TO_MIXSPKL_WIDTH 1 /* BYPASSL_TO_MIXSPKL */ 764#define WM8903_BYPASSR_TO_MIXSPKL 0x0001 /* BYPASSR_TO_MIXSPKL */ 765#define WM8903_BYPASSR_TO_MIXSPKL_MASK 0x0001 /* BYPASSR_TO_MIXSPKL */ 766#define WM8903_BYPASSR_TO_MIXSPKL_SHIFT 0 /* BYPASSR_TO_MIXSPKL */ 767#define WM8903_BYPASSR_TO_MIXSPKL_WIDTH 1 /* BYPASSR_TO_MIXSPKL */ 768 769/* 770 * R53 (0x35) - Analogue Spk Mix Left 1 771 */ 772#define WM8903_DACL_MIXSPKL_VOL 0x0008 /* DACL_MIXSPKL_VOL */ 773#define WM8903_DACL_MIXSPKL_VOL_MASK 0x0008 /* DACL_MIXSPKL_VOL */ 774#define WM8903_DACL_MIXSPKL_VOL_SHIFT 3 /* DACL_MIXSPKL_VOL */ 775#define WM8903_DACL_MIXSPKL_VOL_WIDTH 1 /* DACL_MIXSPKL_VOL */ 776#define WM8903_DACR_MIXSPKL_VOL 0x0004 /* DACR_MIXSPKL_VOL */ 777#define WM8903_DACR_MIXSPKL_VOL_MASK 0x0004 /* DACR_MIXSPKL_VOL */ 778#define WM8903_DACR_MIXSPKL_VOL_SHIFT 2 /* DACR_MIXSPKL_VOL */ 779#define WM8903_DACR_MIXSPKL_VOL_WIDTH 1 /* DACR_MIXSPKL_VOL */ 780#define WM8903_BYPASSL_MIXSPKL_VOL 0x0002 /* BYPASSL_MIXSPKL_VOL */ 781#define WM8903_BYPASSL_MIXSPKL_VOL_MASK 0x0002 /* BYPASSL_MIXSPKL_VOL */ 782#define WM8903_BYPASSL_MIXSPKL_VOL_SHIFT 1 /* BYPASSL_MIXSPKL_VOL */ 783#define WM8903_BYPASSL_MIXSPKL_VOL_WIDTH 1 /* BYPASSL_MIXSPKL_VOL */ 784#define WM8903_BYPASSR_MIXSPKL_VOL 0x0001 /* BYPASSR_MIXSPKL_VOL */ 785#define WM8903_BYPASSR_MIXSPKL_VOL_MASK 0x0001 /* BYPASSR_MIXSPKL_VOL */ 786#define WM8903_BYPASSR_MIXSPKL_VOL_SHIFT 0 /* BYPASSR_MIXSPKL_VOL */ 787#define WM8903_BYPASSR_MIXSPKL_VOL_WIDTH 1 /* BYPASSR_MIXSPKL_VOL */ 788 789/* 790 * R54 (0x36) - Analogue Spk Mix Right 0 791 */ 792#define WM8903_DACL_TO_MIXSPKR 0x0008 /* DACL_TO_MIXSPKR */ 793#define WM8903_DACL_TO_MIXSPKR_MASK 0x0008 /* DACL_TO_MIXSPKR */ 794#define WM8903_DACL_TO_MIXSPKR_SHIFT 3 /* DACL_TO_MIXSPKR */ 795#define WM8903_DACL_TO_MIXSPKR_WIDTH 1 /* DACL_TO_MIXSPKR */ 796#define WM8903_DACR_TO_MIXSPKR 0x0004 /* DACR_TO_MIXSPKR */ 797#define WM8903_DACR_TO_MIXSPKR_MASK 0x0004 /* DACR_TO_MIXSPKR */ 798#define WM8903_DACR_TO_MIXSPKR_SHIFT 2 /* DACR_TO_MIXSPKR */ 799#define WM8903_DACR_TO_MIXSPKR_WIDTH 1 /* DACR_TO_MIXSPKR */ 800#define WM8903_BYPASSL_TO_MIXSPKR 0x0002 /* BYPASSL_TO_MIXSPKR */ 801#define WM8903_BYPASSL_TO_MIXSPKR_MASK 0x0002 /* BYPASSL_TO_MIXSPKR */ 802#define WM8903_BYPASSL_TO_MIXSPKR_SHIFT 1 /* BYPASSL_TO_MIXSPKR */ 803#define WM8903_BYPASSL_TO_MIXSPKR_WIDTH 1 /* BYPASSL_TO_MIXSPKR */ 804#define WM8903_BYPASSR_TO_MIXSPKR 0x0001 /* BYPASSR_TO_MIXSPKR */ 805#define WM8903_BYPASSR_TO_MIXSPKR_MASK 0x0001 /* BYPASSR_TO_MIXSPKR */ 806#define WM8903_BYPASSR_TO_MIXSPKR_SHIFT 0 /* BYPASSR_TO_MIXSPKR */ 807#define WM8903_BYPASSR_TO_MIXSPKR_WIDTH 1 /* BYPASSR_TO_MIXSPKR */ 808 809/* 810 * R55 (0x37) - Analogue Spk Mix Right 1 811 */ 812#define WM8903_DACL_MIXSPKR_VOL 0x0008 /* DACL_MIXSPKR_VOL */ 813#define WM8903_DACL_MIXSPKR_VOL_MASK 0x0008 /* DACL_MIXSPKR_VOL */ 814#define WM8903_DACL_MIXSPKR_VOL_SHIFT 3 /* DACL_MIXSPKR_VOL */ 815#define WM8903_DACL_MIXSPKR_VOL_WIDTH 1 /* DACL_MIXSPKR_VOL */ 816#define WM8903_DACR_MIXSPKR_VOL 0x0004 /* DACR_MIXSPKR_VOL */ 817#define WM8903_DACR_MIXSPKR_VOL_MASK 0x0004 /* DACR_MIXSPKR_VOL */ 818#define WM8903_DACR_MIXSPKR_VOL_SHIFT 2 /* DACR_MIXSPKR_VOL */ 819#define WM8903_DACR_MIXSPKR_VOL_WIDTH 1 /* DACR_MIXSPKR_VOL */ 820#define WM8903_BYPASSL_MIXSPKR_VOL 0x0002 /* BYPASSL_MIXSPKR_VOL */ 821#define WM8903_BYPASSL_MIXSPKR_VOL_MASK 0x0002 /* BYPASSL_MIXSPKR_VOL */ 822#define WM8903_BYPASSL_MIXSPKR_VOL_SHIFT 1 /* BYPASSL_MIXSPKR_VOL */ 823#define WM8903_BYPASSL_MIXSPKR_VOL_WIDTH 1 /* BYPASSL_MIXSPKR_VOL */ 824#define WM8903_BYPASSR_MIXSPKR_VOL 0x0001 /* BYPASSR_MIXSPKR_VOL */ 825#define WM8903_BYPASSR_MIXSPKR_VOL_MASK 0x0001 /* BYPASSR_MIXSPKR_VOL */ 826#define WM8903_BYPASSR_MIXSPKR_VOL_SHIFT 0 /* BYPASSR_MIXSPKR_VOL */ 827#define WM8903_BYPASSR_MIXSPKR_VOL_WIDTH 1 /* BYPASSR_MIXSPKR_VOL */ 828 829/* 830 * R57 (0x39) - Analogue OUT1 Left 831 */ 832#define WM8903_HPL_MUTE 0x0100 /* HPL_MUTE */ 833#define WM8903_HPL_MUTE_MASK 0x0100 /* HPL_MUTE */ 834#define WM8903_HPL_MUTE_SHIFT 8 /* HPL_MUTE */ 835#define WM8903_HPL_MUTE_WIDTH 1 /* HPL_MUTE */ 836#define WM8903_HPOUTVU 0x0080 /* HPOUTVU */ 837#define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */ 838#define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */ 839#define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */ 840#define WM8903_HPOUTLZC 0x0040 /* HPOUTLZC */ 841#define WM8903_HPOUTLZC_MASK 0x0040 /* HPOUTLZC */ 842#define WM8903_HPOUTLZC_SHIFT 6 /* HPOUTLZC */ 843#define WM8903_HPOUTLZC_WIDTH 1 /* HPOUTLZC */ 844#define WM8903_HPOUTL_VOL_MASK 0x003F /* HPOUTL_VOL - [5:0] */ 845#define WM8903_HPOUTL_VOL_SHIFT 0 /* HPOUTL_VOL - [5:0] */ 846#define WM8903_HPOUTL_VOL_WIDTH 6 /* HPOUTL_VOL - [5:0] */ 847 848/* 849 * R58 (0x3A) - Analogue OUT1 Right 850 */ 851#define WM8903_HPR_MUTE 0x0100 /* HPR_MUTE */ 852#define WM8903_HPR_MUTE_MASK 0x0100 /* HPR_MUTE */ 853#define WM8903_HPR_MUTE_SHIFT 8 /* HPR_MUTE */ 854#define WM8903_HPR_MUTE_WIDTH 1 /* HPR_MUTE */ 855#define WM8903_HPOUTVU 0x0080 /* HPOUTVU */ 856#define WM8903_HPOUTVU_MASK 0x0080 /* HPOUTVU */ 857#define WM8903_HPOUTVU_SHIFT 7 /* HPOUTVU */ 858#define WM8903_HPOUTVU_WIDTH 1 /* HPOUTVU */ 859#define WM8903_HPOUTRZC 0x0040 /* HPOUTRZC */ 860#define WM8903_HPOUTRZC_MASK 0x0040 /* HPOUTRZC */ 861#define WM8903_HPOUTRZC_SHIFT 6 /* HPOUTRZC */ 862#define WM8903_HPOUTRZC_WIDTH 1 /* HPOUTRZC */ 863#define WM8903_HPOUTR_VOL_MASK 0x003F /* HPOUTR_VOL - [5:0] */ 864#define WM8903_HPOUTR_VOL_SHIFT 0 /* HPOUTR_VOL - [5:0] */ 865#define WM8903_HPOUTR_VOL_WIDTH 6 /* HPOUTR_VOL - [5:0] */ 866 867/* 868 * R59 (0x3B) - Analogue OUT2 Left 869 */ 870#define WM8903_LINEOUTL_MUTE 0x0100 /* LINEOUTL_MUTE */ 871#define WM8903_LINEOUTL_MUTE_MASK 0x0100 /* LINEOUTL_MUTE */ 872#define WM8903_LINEOUTL_MUTE_SHIFT 8 /* LINEOUTL_MUTE */ 873#define WM8903_LINEOUTL_MUTE_WIDTH 1 /* LINEOUTL_MUTE */ 874#define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */ 875#define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */ 876#define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */ 877#define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */ 878#define WM8903_LINEOUTLZC 0x0040 /* LINEOUTLZC */ 879#define WM8903_LINEOUTLZC_MASK 0x0040 /* LINEOUTLZC */ 880#define WM8903_LINEOUTLZC_SHIFT 6 /* LINEOUTLZC */ 881#define WM8903_LINEOUTLZC_WIDTH 1 /* LINEOUTLZC */ 882#define WM8903_LINEOUTL_VOL_MASK 0x003F /* LINEOUTL_VOL - [5:0] */ 883#define WM8903_LINEOUTL_VOL_SHIFT 0 /* LINEOUTL_VOL - [5:0] */ 884#define WM8903_LINEOUTL_VOL_WIDTH 6 /* LINEOUTL_VOL - [5:0] */ 885 886/* 887 * R60 (0x3C) - Analogue OUT2 Right 888 */ 889#define WM8903_LINEOUTR_MUTE 0x0100 /* LINEOUTR_MUTE */ 890#define WM8903_LINEOUTR_MUTE_MASK 0x0100 /* LINEOUTR_MUTE */ 891#define WM8903_LINEOUTR_MUTE_SHIFT 8 /* LINEOUTR_MUTE */ 892#define WM8903_LINEOUTR_MUTE_WIDTH 1 /* LINEOUTR_MUTE */ 893#define WM8903_LINEOUTVU 0x0080 /* LINEOUTVU */ 894#define WM8903_LINEOUTVU_MASK 0x0080 /* LINEOUTVU */ 895#define WM8903_LINEOUTVU_SHIFT 7 /* LINEOUTVU */ 896#define WM8903_LINEOUTVU_WIDTH 1 /* LINEOUTVU */ 897#define WM8903_LINEOUTRZC 0x0040 /* LINEOUTRZC */ 898#define WM8903_LINEOUTRZC_MASK 0x0040 /* LINEOUTRZC */ 899#define WM8903_LINEOUTRZC_SHIFT 6 /* LINEOUTRZC */ 900#define WM8903_LINEOUTRZC_WIDTH 1 /* LINEOUTRZC */ 901#define WM8903_LINEOUTR_VOL_MASK 0x003F /* LINEOUTR_VOL - [5:0] */ 902#define WM8903_LINEOUTR_VOL_SHIFT 0 /* LINEOUTR_VOL - [5:0] */ 903#define WM8903_LINEOUTR_VOL_WIDTH 6 /* LINEOUTR_VOL - [5:0] */ 904 905/* 906 * R62 (0x3E) - Analogue OUT3 Left 907 */ 908#define WM8903_SPKL_MUTE 0x0100 /* SPKL_MUTE */ 909#define WM8903_SPKL_MUTE_MASK 0x0100 /* SPKL_MUTE */ 910#define WM8903_SPKL_MUTE_SHIFT 8 /* SPKL_MUTE */ 911#define WM8903_SPKL_MUTE_WIDTH 1 /* SPKL_MUTE */ 912#define WM8903_SPKVU 0x0080 /* SPKVU */ 913#define WM8903_SPKVU_MASK 0x0080 /* SPKVU */ 914#define WM8903_SPKVU_SHIFT 7 /* SPKVU */ 915#define WM8903_SPKVU_WIDTH 1 /* SPKVU */ 916#define WM8903_SPKLZC 0x0040 /* SPKLZC */ 917#define WM8903_SPKLZC_MASK 0x0040 /* SPKLZC */ 918#define WM8903_SPKLZC_SHIFT 6 /* SPKLZC */ 919#define WM8903_SPKLZC_WIDTH 1 /* SPKLZC */ 920#define WM8903_SPKL_VOL_MASK 0x003F /* SPKL_VOL - [5:0] */ 921#define WM8903_SPKL_VOL_SHIFT 0 /* SPKL_VOL - [5:0] */ 922#define WM8903_SPKL_VOL_WIDTH 6 /* SPKL_VOL - [5:0] */ 923 924/* 925 * R63 (0x3F) - Analogue OUT3 Right 926 */ 927#define WM8903_SPKR_MUTE 0x0100 /* SPKR_MUTE */ 928#define WM8903_SPKR_MUTE_MASK 0x0100 /* SPKR_MUTE */ 929#define WM8903_SPKR_MUTE_SHIFT 8 /* SPKR_MUTE */ 930#define WM8903_SPKR_MUTE_WIDTH 1 /* SPKR_MUTE */ 931#define WM8903_SPKVU 0x0080 /* SPKVU */ 932#define WM8903_SPKVU_MASK 0x0080 /* SPKVU */ 933#define WM8903_SPKVU_SHIFT 7 /* SPKVU */ 934#define WM8903_SPKVU_WIDTH 1 /* SPKVU */ 935#define WM8903_SPKRZC 0x0040 /* SPKRZC */ 936#define WM8903_SPKRZC_MASK 0x0040 /* SPKRZC */ 937#define WM8903_SPKRZC_SHIFT 6 /* SPKRZC */ 938#define WM8903_SPKRZC_WIDTH 1 /* SPKRZC */ 939#define WM8903_SPKR_VOL_MASK 0x003F /* SPKR_VOL - [5:0] */ 940#define WM8903_SPKR_VOL_SHIFT 0 /* SPKR_VOL - [5:0] */ 941#define WM8903_SPKR_VOL_WIDTH 6 /* SPKR_VOL - [5:0] */ 942 943/* 944 * R65 (0x41) - Analogue SPK Output Control 0 945 */ 946#define WM8903_SPK_DISCHARGE 0x0002 /* SPK_DISCHARGE */ 947#define WM8903_SPK_DISCHARGE_MASK 0x0002 /* SPK_DISCHARGE */ 948#define WM8903_SPK_DISCHARGE_SHIFT 1 /* SPK_DISCHARGE */ 949#define WM8903_SPK_DISCHARGE_WIDTH 1 /* SPK_DISCHARGE */ 950#define WM8903_VROI 0x0001 /* VROI */ 951#define WM8903_VROI_MASK 0x0001 /* VROI */ 952#define WM8903_VROI_SHIFT 0 /* VROI */ 953#define WM8903_VROI_WIDTH 1 /* VROI */ 954 955/* 956 * R67 (0x43) - DC Servo 0 957 */ 958#define WM8903_DCS_MASTER_ENA 0x0010 /* DCS_MASTER_ENA */ 959#define WM8903_DCS_MASTER_ENA_MASK 0x0010 /* DCS_MASTER_ENA */ 960#define WM8903_DCS_MASTER_ENA_SHIFT 4 /* DCS_MASTER_ENA */ 961#define WM8903_DCS_MASTER_ENA_WIDTH 1 /* DCS_MASTER_ENA */ 962#define WM8903_DCS_ENA_MASK 0x000F /* DCS_ENA - [3:0] */ 963#define WM8903_DCS_ENA_SHIFT 0 /* DCS_ENA - [3:0] */ 964#define WM8903_DCS_ENA_WIDTH 4 /* DCS_ENA - [3:0] */ 965 966/* 967 * R69 (0x45) - DC Servo 2 968 */ 969#define WM8903_DCS_MODE_MASK 0x0003 /* DCS_MODE - [1:0] */ 970#define WM8903_DCS_MODE_SHIFT 0 /* DCS_MODE - [1:0] */ 971#define WM8903_DCS_MODE_WIDTH 2 /* DCS_MODE - [1:0] */ 972 973/* 974 * R90 (0x5A) - Analogue HP 0 975 */ 976#define WM8903_HPL_RMV_SHORT 0x0080 /* HPL_RMV_SHORT */ 977#define WM8903_HPL_RMV_SHORT_MASK 0x0080 /* HPL_RMV_SHORT */ 978#define WM8903_HPL_RMV_SHORT_SHIFT 7 /* HPL_RMV_SHORT */ 979#define WM8903_HPL_RMV_SHORT_WIDTH 1 /* HPL_RMV_SHORT */ 980#define WM8903_HPL_ENA_OUTP 0x0040 /* HPL_ENA_OUTP */ 981#define WM8903_HPL_ENA_OUTP_MASK 0x0040 /* HPL_ENA_OUTP */ 982#define WM8903_HPL_ENA_OUTP_SHIFT 6 /* HPL_ENA_OUTP */ 983#define WM8903_HPL_ENA_OUTP_WIDTH 1 /* HPL_ENA_OUTP */ 984#define WM8903_HPL_ENA_DLY 0x0020 /* HPL_ENA_DLY */ 985#define WM8903_HPL_ENA_DLY_MASK 0x0020 /* HPL_ENA_DLY */ 986#define WM8903_HPL_ENA_DLY_SHIFT 5 /* HPL_ENA_DLY */ 987#define WM8903_HPL_ENA_DLY_WIDTH 1 /* HPL_ENA_DLY */ 988#define WM8903_HPL_ENA 0x0010 /* HPL_ENA */ 989#define WM8903_HPL_ENA_MASK 0x0010 /* HPL_ENA */ 990#define WM8903_HPL_ENA_SHIFT 4 /* HPL_ENA */ 991#define WM8903_HPL_ENA_WIDTH 1 /* HPL_ENA */ 992#define WM8903_HPR_RMV_SHORT 0x0008 /* HPR_RMV_SHORT */ 993#define WM8903_HPR_RMV_SHORT_MASK 0x0008 /* HPR_RMV_SHORT */ 994#define WM8903_HPR_RMV_SHORT_SHIFT 3 /* HPR_RMV_SHORT */ 995#define WM8903_HPR_RMV_SHORT_WIDTH 1 /* HPR_RMV_SHORT */ 996#define WM8903_HPR_ENA_OUTP 0x0004 /* HPR_ENA_OUTP */ 997#define WM8903_HPR_ENA_OUTP_MASK 0x0004 /* HPR_ENA_OUTP */ 998#define WM8903_HPR_ENA_OUTP_SHIFT 2 /* HPR_ENA_OUTP */ 999#define WM8903_HPR_ENA_OUTP_WIDTH 1 /* HPR_ENA_OUTP */ 1000#define WM8903_HPR_ENA_DLY 0x0002 /* HPR_ENA_DLY */
1001#define WM8903_HPR_ENA_DLY_MASK 0x0002 /* HPR_ENA_DLY */ 1002#define WM8903_HPR_ENA_DLY_SHIFT 1 /* HPR_ENA_DLY */ 1003#define WM8903_HPR_ENA_DLY_WIDTH 1 /* HPR_ENA_DLY */ 1004#define WM8903_HPR_ENA 0x0001 /* HPR_ENA */ 1005#define WM8903_HPR_ENA_MASK 0x0001 /* HPR_ENA */ 1006#define WM8903_HPR_ENA_SHIFT 0 /* HPR_ENA */ 1007#define WM8903_HPR_ENA_WIDTH 1 /* HPR_ENA */ 1008 1009/* 1010 * R94 (0x5E) - Analogue Lineout 0 1011 */ 1012#define WM8903_LINEOUTL_RMV_SHORT 0x0080 /* LINEOUTL_RMV_SHORT */ 1013#define WM8903_LINEOUTL_RMV_SHORT_MASK 0x0080 /* LINEOUTL_RMV_SHORT */ 1014#define WM8903_LINEOUTL_RMV_SHORT_SHIFT 7 /* LINEOUTL_RMV_SHORT */ 1015#define WM8903_LINEOUTL_RMV_SHORT_WIDTH 1 /* LINEOUTL_RMV_SHORT */ 1016#define WM8903_LINEOUTL_ENA_OUTP 0x0040 /* LINEOUTL_ENA_OUTP */ 1017#define WM8903_LINEOUTL_ENA_OUTP_MASK 0x0040 /* LINEOUTL_ENA_OUTP */ 1018#define WM8903_LINEOUTL_ENA_OUTP_SHIFT 6 /* LINEOUTL_ENA_OUTP */ 1019#define WM8903_LINEOUTL_ENA_OUTP_WIDTH 1 /* LINEOUTL_ENA_OUTP */ 1020#define WM8903_LINEOUTL_ENA_DLY 0x0020 /* LINEOUTL_ENA_DLY */ 1021#define WM8903_LINEOUTL_ENA_DLY_MASK 0x0020 /* LINEOUTL_ENA_DLY */ 1022#define WM8903_LINEOUTL_ENA_DLY_SHIFT 5 /* LINEOUTL_ENA_DLY */ 1023#define WM8903_LINEOUTL_ENA_DLY_WIDTH 1 /* LINEOUTL_ENA_DLY */ 1024#define WM8903_LINEOUTL_ENA 0x0010 /* LINEOUTL_ENA */ 1025#define WM8903_LINEOUTL_ENA_MASK 0x0010 /* LINEOUTL_ENA */ 1026#define WM8903_LINEOUTL_ENA_SHIFT 4 /* LINEOUTL_ENA */ 1027#define WM8903_LINEOUTL_ENA_WIDTH 1 /* LINEOUTL_ENA */ 1028#define WM8903_LINEOUTR_RMV_SHORT 0x0008 /* LINEOUTR_RMV_SHORT */ 1029#define WM8903_LINEOUTR_RMV_SHORT_MASK 0x0008 /* LINEOUTR_RMV_SHORT */ 1030#define WM8903_LINEOUTR_RMV_SHORT_SHIFT 3 /* LINEOUTR_RMV_SHORT */ 1031#define WM8903_LINEOUTR_RMV_SHORT_WIDTH 1 /* LINEOUTR_RMV_SHORT */ 1032#define WM8903_LINEOUTR_ENA_OUTP 0x0004 /* LINEOUTR_ENA_OUTP */ 1033#define WM8903_LINEOUTR_ENA_OUTP_MASK 0x0004 /* LINEOUTR_ENA_OUTP */ 1034#define WM8903_LINEOUTR_ENA_OUTP_SHIFT 2 /* LINEOUTR_ENA_OUTP */ 1035#define WM8903_LINEOUTR_ENA_OUTP_WIDTH 1 /* LINEOUTR_ENA_OUTP */ 1036#define WM8903_LINEOUTR_ENA_DLY 0x0002 /* LINEOUTR_ENA_DLY */ 1037#define WM8903_LINEOUTR_ENA_DLY_MASK 0x0002 /* LINEOUTR_ENA_DLY */ 1038#define WM8903_LINEOUTR_ENA_DLY_SHIFT 1 /* LINEOUTR_ENA_DLY */ 1039#define WM8903_LINEOUTR_ENA_DLY_WIDTH 1 /* LINEOUTR_ENA_DLY */ 1040#define WM8903_LINEOUTR_ENA 0x0001 /* LINEOUTR_ENA */ 1041#define WM8903_LINEOUTR_ENA_MASK 0x0001 /* LINEOUTR_ENA */ 1042#define WM8903_LINEOUTR_ENA_SHIFT 0 /* LINEOUTR_ENA */ 1043#define WM8903_LINEOUTR_ENA_WIDTH 1 /* LINEOUTR_ENA */ 1044 1045/* 1046 * R98 (0x62) - Charge Pump 0 1047 */ 1048#define WM8903_CP_ENA 0x0001 /* CP_ENA */ 1049#define WM8903_CP_ENA_MASK 0x0001 /* CP_ENA */ 1050#define WM8903_CP_ENA_SHIFT 0 /* CP_ENA */ 1051#define WM8903_CP_ENA_WIDTH 1 /* CP_ENA */ 1052 1053/* 1054 * R104 (0x68) - Class W 0 1055 */ 1056#define WM8903_CP_DYN_FREQ 0x0002 /* CP_DYN_FREQ */ 1057#define WM8903_CP_DYN_FREQ_MASK 0x0002 /* CP_DYN_FREQ */ 1058#define WM8903_CP_DYN_FREQ_SHIFT 1 /* CP_DYN_FREQ */ 1059#define WM8903_CP_DYN_FREQ_WIDTH 1 /* CP_DYN_FREQ */ 1060#define WM8903_CP_DYN_V 0x0001 /* CP_DYN_V */ 1061#define WM8903_CP_DYN_V_MASK 0x0001 /* CP_DYN_V */ 1062#define WM8903_CP_DYN_V_SHIFT 0 /* CP_DYN_V */ 1063#define WM8903_CP_DYN_V_WIDTH 1 /* CP_DYN_V */ 1064 1065/* 1066 * R108 (0x6C) - Write Sequencer 0 1067 */ 1068#define WM8903_WSEQ_ENA 0x0100 /* WSEQ_ENA */ 1069#define WM8903_WSEQ_ENA_MASK 0x0100 /* WSEQ_ENA */ 1070#define WM8903_WSEQ_ENA_SHIFT 8 /* WSEQ_ENA */ 1071#define WM8903_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */ 1072#define WM8903_WSEQ_WRITE_INDEX_MASK 0x001F /* WSEQ_WRITE_INDEX - [4:0] */ 1073#define WM8903_WSEQ_WRITE_INDEX_SHIFT 0 /* WSEQ_WRITE_INDEX - [4:0] */ 1074#define WM8903_WSEQ_WRITE_INDEX_WIDTH 5 /* WSEQ_WRITE_INDEX - [4:0] */ 1075 1076/* 1077 * R109 (0x6D) - Write Sequencer 1 1078 */ 1079#define WM8903_WSEQ_DATA_WIDTH_MASK 0x7000 /* WSEQ_DATA_WIDTH - [14:12] */ 1080#define WM8903_WSEQ_DATA_WIDTH_SHIFT 12 /* WSEQ_DATA_WIDTH - [14:12] */ 1081#define WM8903_WSEQ_DATA_WIDTH_WIDTH 3 /* WSEQ_DATA_WIDTH - [14:12] */ 1082#define WM8903_WSEQ_DATA_START_MASK 0x0F00 /* WSEQ_DATA_START - [11:8] */ 1083#define WM8903_WSEQ_DATA_START_SHIFT 8 /* WSEQ_DATA_START - [11:8] */ 1084#define WM8903_WSEQ_DATA_START_WIDTH 4 /* WSEQ_DATA_START - [11:8] */ 1085#define WM8903_WSEQ_ADDR_MASK 0x00FF /* WSEQ_ADDR - [7:0] */ 1086#define WM8903_WSEQ_ADDR_SHIFT 0 /* WSEQ_ADDR - [7:0] */ 1087#define WM8903_WSEQ_ADDR_WIDTH 8 /* WSEQ_ADDR - [7:0] */ 1088 1089/* 1090 * R110 (0x6E) - Write Sequencer 2 1091 */ 1092#define WM8903_WSEQ_EOS 0x4000 /* WSEQ_EOS */ 1093#define WM8903_WSEQ_EOS_MASK 0x4000 /* WSEQ_EOS */ 1094#define WM8903_WSEQ_EOS_SHIFT 14 /* WSEQ_EOS */ 1095#define WM8903_WSEQ_EOS_WIDTH 1 /* WSEQ_EOS */ 1096#define WM8903_WSEQ_DELAY_MASK 0x0F00 /* WSEQ_DELAY - [11:8] */ 1097#define WM8903_WSEQ_DELAY_SHIFT 8 /* WSEQ_DELAY - [11:8] */ 1098#define WM8903_WSEQ_DELAY_WIDTH 4 /* WSEQ_DELAY - [11:8] */ 1099#define WM8903_WSEQ_DATA_MASK 0x00FF /* WSEQ_DATA - [7:0] */ 1100#define WM8903_WSEQ_DATA_SHIFT 0 /* WSEQ_DATA - [7:0] */ 1101#define WM8903_WSEQ_DATA_WIDTH 8 /* WSEQ_DATA - [7:0] */ 1102 1103/* 1104 * R111 (0x6F) - Write Sequencer 3 1105 */ 1106#define WM8903_WSEQ_ABORT 0x0200 /* WSEQ_ABORT */ 1107#define WM8903_WSEQ_ABORT_MASK 0x0200 /* WSEQ_ABORT */ 1108#define WM8903_WSEQ_ABORT_SHIFT 9 /* WSEQ_ABORT */ 1109#define WM8903_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */ 1110#define WM8903_WSEQ_START 0x0100 /* WSEQ_START */ 1111#define WM8903_WSEQ_START_MASK 0x0100 /* WSEQ_START */ 1112#define WM8903_WSEQ_START_SHIFT 8 /* WSEQ_START */ 1113#define WM8903_WSEQ_START_WIDTH 1 /* WSEQ_START */ 1114#define WM8903_WSEQ_START_INDEX_MASK 0x003F /* WSEQ_START_INDEX - [5:0] */ 1115#define WM8903_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [5:0] */ 1116#define WM8903_WSEQ_START_INDEX_WIDTH 6 /* WSEQ_START_INDEX - [5:0] */ 1117 1118/* 1119 * R112 (0x70) - Write Sequencer 4 1120 */ 1121#define WM8903_WSEQ_CURRENT_INDEX_MASK 0x03F0 /* WSEQ_CURRENT_INDEX - [9:4] */ 1122#define WM8903_WSEQ_CURRENT_INDEX_SHIFT 4 /* WSEQ_CURRENT_INDEX - [9:4] */ 1123#define WM8903_WSEQ_CURRENT_INDEX_WIDTH 6 /* WSEQ_CURRENT_INDEX - [9:4] */ 1124#define WM8903_WSEQ_BUSY 0x0001 /* WSEQ_BUSY */ 1125#define WM8903_WSEQ_BUSY_MASK 0x0001 /* WSEQ_BUSY */ 1126#define WM8903_WSEQ_BUSY_SHIFT 0 /* WSEQ_BUSY */ 1127#define WM8903_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */ 1128 1129/* 1130 * R114 (0x72) - Control Interface 1131 */ 1132#define WM8903_MASK_WRITE_ENA 0x0001 /* MASK_WRITE_ENA */ 1133#define WM8903_MASK_WRITE_ENA_MASK 0x0001 /* MASK_WRITE_ENA */ 1134#define WM8903_MASK_WRITE_ENA_SHIFT 0 /* MASK_WRITE_ENA */ 1135#define WM8903_MASK_WRITE_ENA_WIDTH 1 /* MASK_WRITE_ENA */ 1136 1137/* 1138 * R116 (0x74) - GPIO Control 1 1139 */ 1140#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ 1141#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ 1142#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ 1143#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ 1144#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ 1145#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ 1146#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ 1147#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ 1148#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ 1149#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ 1150#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ 1151#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ 1152#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ 1153#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ 1154#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ 1155#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ 1156#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ 1157#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ 1158#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ 1159#define WM8903_GP1_PD 0x0008 /* GP1_PD */ 1160#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ 1161#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ 1162#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ 1163#define WM8903_GP1_PU 0x0004 /* GP1_PU */ 1164#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ 1165#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ 1166#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ 1167#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ 1168#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ 1169#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ 1170#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ 1171#define WM8903_GP1_DB 0x0001 /* GP1_DB */ 1172#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ 1173#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ 1174#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ 1175 1176/* 1177 * R117 (0x75) - GPIO Control 2 1178 */ 1179#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ 1180#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ 1181#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ 1182#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ 1183#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ 1184#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ 1185#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ 1186#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ 1187#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ 1188#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ 1189#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ 1190#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ 1191#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ 1192#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ 1193#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ 1194#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ 1195#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ 1196#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ 1197#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ 1198#define WM8903_GP2_PD 0x0008 /* GP2_PD */ 1199#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ 1200#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ 1201#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ 1202#define WM8903_GP2_PU 0x0004 /* GP2_PU */ 1203#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ 1204#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ 1205#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ 1206#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ 1207#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ 1208#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ 1209#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ 1210#define WM8903_GP2_DB 0x0001 /* GP2_DB */ 1211#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ 1212#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ 1213#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ 1214 1215/* 1216 * R118 (0x76) - GPIO Control 3 1217 */ 1218#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ 1219#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ 1220#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ 1221#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ 1222#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ 1223#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ 1224#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ 1225#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ 1226#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ 1227#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ 1228#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ 1229#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ 1230#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ 1231#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ 1232#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ 1233#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ 1234#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ 1235#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ 1236#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ 1237#define WM8903_GP3_PD 0x0008 /* GP3_PD */ 1238#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ 1239#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ 1240#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ 1241#define WM8903_GP3_PU 0x0004 /* GP3_PU */ 1242#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ 1243#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ 1244#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ 1245#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ 1246#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ 1247#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ 1248#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ 1249#define WM8903_GP3_DB 0x0001 /* GP3_DB */ 1250#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ 1251#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ 1252#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ 1253 1254/* 1255 * R119 (0x77) - GPIO Control 4 1256 */ 1257#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ 1258#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ 1259#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ 1260#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ 1261#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ 1262#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ 1263#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ 1264#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ 1265#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ 1266#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ 1267#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ 1268#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ 1269#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ 1270#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ 1271#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ 1272#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ 1273#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ 1274#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ 1275#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ 1276#define WM8903_GP4_PD 0x0008 /* GP4_PD */ 1277#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ 1278#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ 1279#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ 1280#define WM8903_GP4_PU 0x0004 /* GP4_PU */ 1281#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ 1282#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ 1283#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ 1284#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ 1285#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ 1286#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ 1287#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ 1288#define WM8903_GP4_DB 0x0001 /* GP4_DB */ 1289#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ 1290#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ 1291#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ 1292 1293/* 1294 * R120 (0x78) - GPIO Control 5 1295 */ 1296#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ 1297#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ 1298#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ 1299#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ 1300#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ 1301#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ 1302#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ 1303#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ 1304#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ 1305#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ 1306#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ 1307#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ 1308#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ 1309#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ 1310#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ 1311#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ 1312#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ 1313#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ 1314#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ 1315#define WM8903_GP5_PD 0x0008 /* GP5_PD */ 1316#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ 1317#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ 1318#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ 1319#define WM8903_GP5_PU 0x0004 /* GP5_PU */ 1320#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ 1321#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ 1322#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ 1323#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ 1324#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ 1325#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ 1326#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ 1327#define WM8903_GP5_DB 0x0001 /* GP5_DB */ 1328#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ 1329#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ 1330#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ 1331 1332/* 1333 * R121 (0x79) - Interrupt Status 1 1334 */ 1335#define WM8903_MICSHRT_EINT 0x8000 /* MICSHRT_EINT */ 1336#define WM8903_MICSHRT_EINT_MASK 0x8000 /* MICSHRT_EINT */ 1337#define WM8903_MICSHRT_EINT_SHIFT 15 /* MICSHRT_EINT */ 1338#define WM8903_MICSHRT_EINT_WIDTH 1 /* MICSHRT_EINT */ 1339#define WM8903_MICDET_EINT 0x4000 /* MICDET_EINT */ 1340#define WM8903_MICDET_EINT_MASK 0x4000 /* MICDET_EINT */ 1341#define WM8903_MICDET_EINT_SHIFT 14 /* MICDET_EINT */ 1342#define WM8903_MICDET_EINT_WIDTH 1 /* MICDET_EINT */ 1343#define WM8903_WSEQ_BUSY_EINT 0x2000 /* WSEQ_BUSY_EINT */ 1344#define WM8903_WSEQ_BUSY_EINT_MASK 0x2000 /* WSEQ_BUSY_EINT */ 1345#define WM8903_WSEQ_BUSY_EINT_SHIFT 13 /* WSEQ_BUSY_EINT */ 1346#define WM8903_WSEQ_BUSY_EINT_WIDTH 1 /* WSEQ_BUSY_EINT */ 1347#define WM8903_GP5_EINT 0x0010 /* GP5_EINT */ 1348#define WM8903_GP5_EINT_MASK 0x0010 /* GP5_EINT */ 1349#define WM8903_GP5_EINT_SHIFT 4 /* GP5_EINT */ 1350#define WM8903_GP5_EINT_WIDTH 1 /* GP5_EINT */ 1351#define WM8903_GP4_EINT 0x0008 /* GP4_EINT */ 1352#define WM8903_GP4_EINT_MASK 0x0008 /* GP4_EINT */ 1353#define WM8903_GP4_EINT_SHIFT 3 /* GP4_EINT */ 1354#define WM8903_GP4_EINT_WIDTH 1 /* GP4_EINT */ 1355#define WM8903_GP3_EINT 0x0004 /* GP3_EINT */ 1356#define WM8903_GP3_EINT_MASK 0x0004 /* GP3_EINT */ 1357#define WM8903_GP3_EINT_SHIFT 2 /* GP3_EINT */ 1358#define WM8903_GP3_EINT_WIDTH 1 /* GP3_EINT */ 1359#define WM8903_GP2_EINT 0x0002 /* GP2_EINT */ 1360#define WM8903_GP2_EINT_MASK 0x0002 /* GP2_EINT */ 1361#define WM8903_GP2_EINT_SHIFT 1 /* GP2_EINT */ 1362#define WM8903_GP2_EINT_WIDTH 1 /* GP2_EINT */ 1363#define WM8903_GP1_EINT 0x0001 /* GP1_EINT */ 1364#define WM8903_GP1_EINT_MASK 0x0001 /* GP1_EINT */ 1365#define WM8903_GP1_EINT_SHIFT 0 /* GP1_EINT */ 1366#define WM8903_GP1_EINT_WIDTH 1 /* GP1_EINT */ 1367 1368/* 1369 * R122 (0x7A) - Interrupt Status 1 Mask 1370 */ 1371#define WM8903_IM_MICSHRT_EINT 0x8000 /* IM_MICSHRT_EINT */ 1372#define WM8903_IM_MICSHRT_EINT_MASK 0x8000 /* IM_MICSHRT_EINT */ 1373#define WM8903_IM_MICSHRT_EINT_SHIFT 15 /* IM_MICSHRT_EINT */ 1374#define WM8903_IM_MICSHRT_EINT_WIDTH 1 /* IM_MICSHRT_EINT */ 1375#define WM8903_IM_MICDET_EINT 0x4000 /* IM_MICDET_EINT */ 1376#define WM8903_IM_MICDET_EINT_MASK 0x4000 /* IM_MICDET_EINT */ 1377#define WM8903_IM_MICDET_EINT_SHIFT 14 /* IM_MICDET_EINT */ 1378#define WM8903_IM_MICDET_EINT_WIDTH 1 /* IM_MICDET_EINT */ 1379#define WM8903_IM_WSEQ_BUSY_EINT 0x2000 /* IM_WSEQ_BUSY_EINT */ 1380#define WM8903_IM_WSEQ_BUSY_EINT_MASK 0x2000 /* IM_WSEQ_BUSY_EINT */ 1381#define WM8903_IM_WSEQ_BUSY_EINT_SHIFT 13 /* IM_WSEQ_BUSY_EINT */ 1382#define WM8903_IM_WSEQ_BUSY_EINT_WIDTH 1 /* IM_WSEQ_BUSY_EINT */ 1383#define WM8903_IM_GP5_EINT 0x0010 /* IM_GP5_EINT */ 1384#define WM8903_IM_GP5_EINT_MASK 0x0010 /* IM_GP5_EINT */ 1385#define WM8903_IM_GP5_EINT_SHIFT 4 /* IM_GP5_EINT */ 1386#define WM8903_IM_GP5_EINT_WIDTH 1 /* IM_GP5_EINT */ 1387#define WM8903_IM_GP4_EINT 0x0008 /* IM_GP4_EINT */ 1388#define WM8903_IM_GP4_EINT_MASK 0x0008 /* IM_GP4_EINT */ 1389#define WM8903_IM_GP4_EINT_SHIFT 3 /* IM_GP4_EINT */ 1390#define WM8903_IM_GP4_EINT_WIDTH 1 /* IM_GP4_EINT */ 1391#define WM8903_IM_GP3_EINT 0x0004 /* IM_GP3_EINT */ 1392#define WM8903_IM_GP3_EINT_MASK 0x0004 /* IM_GP3_EINT */ 1393#define WM8903_IM_GP3_EINT_SHIFT 2 /* IM_GP3_EINT */ 1394#define WM8903_IM_GP3_EINT_WIDTH 1 /* IM_GP3_EINT */ 1395#define WM8903_IM_GP2_EINT 0x0002 /* IM_GP2_EINT */ 1396#define WM8903_IM_GP2_EINT_MASK 0x0002 /* IM_GP2_EINT */ 1397#define WM8903_IM_GP2_EINT_SHIFT 1 /* IM_GP2_EINT */ 1398#define WM8903_IM_GP2_EINT_WIDTH 1 /* IM_GP2_EINT */ 1399#define WM8903_IM_GP1_EINT 0x0001 /* IM_GP1_EINT */ 1400#define WM8903_IM_GP1_EINT_MASK 0x0001 /* IM_GP1_EINT */ 1401#define WM8903_IM_GP1_EINT_SHIFT 0 /* IM_GP1_EINT */ 1402#define WM8903_IM_GP1_EINT_WIDTH 1 /* IM_GP1_EINT */ 1403 1404/* 1405 * R123 (0x7B) - Interrupt Polarity 1 1406 */ 1407#define WM8903_MICSHRT_INV 0x8000 /* MICSHRT_INV */ 1408#define WM8903_MICSHRT_INV_MASK 0x8000 /* MICSHRT_INV */ 1409#define WM8903_MICSHRT_INV_SHIFT 15 /* MICSHRT_INV */ 1410#define WM8903_MICSHRT_INV_WIDTH 1 /* MICSHRT_INV */ 1411#define WM8903_MICDET_INV 0x4000 /* MICDET_INV */ 1412#define WM8903_MICDET_INV_MASK 0x4000 /* MICDET_INV */ 1413#define WM8903_MICDET_INV_SHIFT 14 /* MICDET_INV */ 1414#define WM8903_MICDET_INV_WIDTH 1 /* MICDET_INV */ 1415 1416/* 1417 * R126 (0x7E) - Interrupt Control 1418 */ 1419#define WM8903_IRQ_POL 0x0001 /* IRQ_POL */ 1420#define WM8903_IRQ_POL_MASK 0x0001 /* IRQ_POL */ 1421#define WM8903_IRQ_POL_SHIFT 0 /* IRQ_POL */ 1422#define WM8903_IRQ_POL_WIDTH 1 /* IRQ_POL */ 1423 1424/* 1425 * R129 (0x81) - Control Interface Test 1 1426 */ 1427#define WM8903_USER_KEY 0x0002 /* USER_KEY */ 1428#define WM8903_USER_KEY_MASK 0x0002 /* USER_KEY */ 1429#define WM8903_USER_KEY_SHIFT 1 /* USER_KEY */ 1430#define WM8903_USER_KEY_WIDTH 1 /* USER_KEY */ 1431#define WM8903_TEST_KEY 0x0001 /* TEST_KEY */ 1432#define WM8903_TEST_KEY_MASK 0x0001 /* TEST_KEY */ 1433#define WM8903_TEST_KEY_SHIFT 0 /* TEST_KEY */ 1434#define WM8903_TEST_KEY_WIDTH 1 /* TEST_KEY */ 1435 1436/* 1437 * R149 (0x95) - Charge Pump Test 1 1438 */ 1439#define WM8903_CP_SW_KELVIN_MODE_MASK 0x0006 /* CP_SW_KELVIN_MODE - [2:1] */ 1440#define WM8903_CP_SW_KELVIN_MODE_SHIFT 1 /* CP_SW_KELVIN_MODE - [2:1] */ 1441#define WM8903_CP_SW_KELVIN_MODE_WIDTH 2 /* CP_SW_KELVIN_MODE - [2:1] */ 1442 1443/* 1444 * R164 (0xA4) - Clock Rate Test 4 1445 */ 1446#define WM8903_ADC_DIG_MIC 0x0200 /* ADC_DIG_MIC */ 1447#define WM8903_ADC_DIG_MIC_MASK 0x0200 /* ADC_DIG_MIC */ 1448#define WM8903_ADC_DIG_MIC_SHIFT 9 /* ADC_DIG_MIC */ 1449#define WM8903_ADC_DIG_MIC_WIDTH 1 /* ADC_DIG_MIC */ 1450 1451/* 1452 * R172 (0xAC) - Analogue Output Bias 0 1453 */ 1454#define WM8903_PGA_BIAS_MASK 0x0070 /* PGA_BIAS - [6:4] */ 1455#define WM8903_PGA_BIAS_SHIFT 4 /* PGA_BIAS - [6:4] */ 1456#define WM8903_PGA_BIAS_WIDTH 3 /* PGA_BIAS - [6:4] */ 1457 1458#endif 1459