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16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
20#include <linux/interrupt.h>
21#include <linux/delay.h>
22
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27
28#include <asm/io.h>
29
30#include "fsl_dma.h"
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35
36#define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
37 SNDRV_PCM_FMTBIT_U8 | \
38 SNDRV_PCM_FMTBIT_S16_LE | \
39 SNDRV_PCM_FMTBIT_S16_BE | \
40 SNDRV_PCM_FMTBIT_U16_LE | \
41 SNDRV_PCM_FMTBIT_U16_BE | \
42 SNDRV_PCM_FMTBIT_S24_LE | \
43 SNDRV_PCM_FMTBIT_S24_BE | \
44 SNDRV_PCM_FMTBIT_U24_LE | \
45 SNDRV_PCM_FMTBIT_U24_BE | \
46 SNDRV_PCM_FMTBIT_S32_LE | \
47 SNDRV_PCM_FMTBIT_S32_BE | \
48 SNDRV_PCM_FMTBIT_U32_LE | \
49 SNDRV_PCM_FMTBIT_U32_BE)
50
51#define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
52 SNDRV_PCM_RATE_CONTINUOUS)
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67static struct {
68 dma_addr_t ssi_stx_phys;
69 dma_addr_t ssi_srx_phys;
70 struct ccsr_dma_channel __iomem *dma_channel[2];
71 unsigned int irq[2];
72 unsigned int assigned[2];
73} dma_global_data;
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77
78
79#define NUM_DMA_LINKS 2
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104struct fsl_dma_private {
105 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
106 unsigned int controller_id;
107 unsigned int channel_id;
108 struct ccsr_dma_channel __iomem *dma_channel;
109 unsigned int irq;
110 struct snd_pcm_substream *substream;
111 dma_addr_t ssi_sxx_phys;
112 dma_addr_t ld_buf_phys;
113 unsigned int current_link;
114 dma_addr_t dma_buf_phys;
115 dma_addr_t dma_buf_next;
116 dma_addr_t dma_buf_end;
117 size_t period_size;
118 unsigned int num_periods;
119};
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140static const struct snd_pcm_hardware fsl_dma_hardware = {
141
142 .info = SNDRV_PCM_INFO_INTERLEAVED |
143 SNDRV_PCM_INFO_MMAP |
144 SNDRV_PCM_INFO_MMAP_VALID |
145 SNDRV_PCM_INFO_JOINT_DUPLEX |
146 SNDRV_PCM_INFO_PAUSE,
147 .formats = FSLDMA_PCM_FORMATS,
148 .rates = FSLDMA_PCM_RATES,
149 .rate_min = 5512,
150 .rate_max = 192000,
151 .period_bytes_min = 512,
152 .period_bytes_max = (u32) -1,
153 .periods_min = NUM_DMA_LINKS,
154 .periods_max = (unsigned int) -1,
155 .buffer_bytes_max = 128 * 1024,
156};
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163
164static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
165{
166 unsigned long flags;
167
168 snd_pcm_stream_lock_irqsave(substream, flags);
169
170 if (snd_pcm_running(substream))
171 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
172
173 snd_pcm_stream_unlock_irqrestore(substream, flags);
174}
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181
182static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
183{
184 struct fsl_dma_link_descriptor *link =
185 &dma_private->link[dma_private->current_link];
186
187
188 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
189 link->source_addr =
190 cpu_to_be32(dma_private->dma_buf_next);
191 else
192 link->dest_addr =
193 cpu_to_be32(dma_private->dma_buf_next);
194
195
196 dma_private->dma_buf_next += dma_private->period_size;
197
198 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
199 dma_private->dma_buf_next = dma_private->dma_buf_phys;
200
201 if (++dma_private->current_link >= NUM_DMA_LINKS)
202 dma_private->current_link = 0;
203}
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210
211static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
212{
213 struct fsl_dma_private *dma_private = dev_id;
214 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
215 irqreturn_t ret = IRQ_NONE;
216 u32 sr, sr2 = 0;
217
218
219
220
221 sr = in_be32(&dma_channel->sr);
222
223 if (sr & CCSR_DMA_SR_TE) {
224 dev_err(dma_private->substream->pcm->card->dev,
225 "DMA transmit error (controller=%u channel=%u irq=%u\n",
226 dma_private->controller_id,
227 dma_private->channel_id, irq);
228 fsl_dma_abort_stream(dma_private->substream);
229 sr2 |= CCSR_DMA_SR_TE;
230 ret = IRQ_HANDLED;
231 }
232
233 if (sr & CCSR_DMA_SR_CH)
234 ret = IRQ_HANDLED;
235
236 if (sr & CCSR_DMA_SR_PE) {
237 dev_err(dma_private->substream->pcm->card->dev,
238 "DMA%u programming error (channel=%u irq=%u)\n",
239 dma_private->controller_id,
240 dma_private->channel_id, irq);
241 fsl_dma_abort_stream(dma_private->substream);
242 sr2 |= CCSR_DMA_SR_PE;
243 ret = IRQ_HANDLED;
244 }
245
246 if (sr & CCSR_DMA_SR_EOLNI) {
247 sr2 |= CCSR_DMA_SR_EOLNI;
248 ret = IRQ_HANDLED;
249 }
250
251 if (sr & CCSR_DMA_SR_CB)
252 ret = IRQ_HANDLED;
253
254 if (sr & CCSR_DMA_SR_EOSI) {
255 struct snd_pcm_substream *substream = dma_private->substream;
256
257
258 snd_pcm_period_elapsed(substream);
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265 if (dma_private->num_periods != NUM_DMA_LINKS)
266 fsl_dma_update_pointers(dma_private);
267
268 sr2 |= CCSR_DMA_SR_EOSI;
269 ret = IRQ_HANDLED;
270 }
271
272 if (sr & CCSR_DMA_SR_EOLSI) {
273 sr2 |= CCSR_DMA_SR_EOLSI;
274 ret = IRQ_HANDLED;
275 }
276
277
278 if (sr2)
279 out_be32(&dma_channel->sr, sr2);
280
281 return ret;
282}
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290
291static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
292 struct snd_pcm *pcm)
293{
294 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32);
295 int ret;
296
297 if (!card->dev->dma_mask)
298 card->dev->dma_mask = &fsl_dma_dmamask;
299
300 if (!card->dev->coherent_dma_mask)
301 card->dev->coherent_dma_mask = fsl_dma_dmamask;
302
303 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
304 fsl_dma_hardware.buffer_bytes_max,
305 &pcm->streams[0].substream->dma_buffer);
306 if (ret) {
307 dev_err(card->dev,
308 "Can't allocate playback DMA buffer (size=%u)\n",
309 fsl_dma_hardware.buffer_bytes_max);
310 return -ENOMEM;
311 }
312
313 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
314 fsl_dma_hardware.buffer_bytes_max,
315 &pcm->streams[1].substream->dma_buffer);
316 if (ret) {
317 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
318 dev_err(card->dev,
319 "Can't allocate capture DMA buffer (size=%u)\n",
320 fsl_dma_hardware.buffer_bytes_max);
321 return -ENOMEM;
322 }
323
324 return 0;
325}
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389static int fsl_dma_open(struct snd_pcm_substream *substream)
390{
391 struct snd_pcm_runtime *runtime = substream->runtime;
392 struct fsl_dma_private *dma_private;
393 struct ccsr_dma_channel __iomem *dma_channel;
394 dma_addr_t ld_buf_phys;
395 u64 temp_link;
396 u32 mr;
397 unsigned int channel;
398 int ret = 0;
399 unsigned int i;
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406 ret = snd_pcm_hw_constraint_integer(runtime,
407 SNDRV_PCM_HW_PARAM_PERIODS);
408 if (ret < 0) {
409 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
410 return ret;
411 }
412
413 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
414
415 if (dma_global_data.assigned[channel]) {
416 dev_err(substream->pcm->card->dev,
417 "DMA channel already assigned\n");
418 return -EBUSY;
419 }
420
421 dma_private = dma_alloc_coherent(substream->pcm->card->dev,
422 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL);
423 if (!dma_private) {
424 dev_err(substream->pcm->card->dev,
425 "can't allocate DMA private data\n");
426 return -ENOMEM;
427 }
428 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
429 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys;
430 else
431 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys;
432
433 dma_private->dma_channel = dma_global_data.dma_channel[channel];
434 dma_private->irq = dma_global_data.irq[channel];
435 dma_private->substream = substream;
436 dma_private->ld_buf_phys = ld_buf_phys;
437 dma_private->dma_buf_phys = substream->dma_buffer.addr;
438
439
440 dma_private->controller_id = 0;
441 dma_private->channel_id = channel;
442
443 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private);
444 if (ret) {
445 dev_err(substream->pcm->card->dev,
446 "can't register ISR for IRQ %u (ret=%i)\n",
447 dma_private->irq, ret);
448 dma_free_coherent(substream->pcm->card->dev,
449 sizeof(struct fsl_dma_private),
450 dma_private, dma_private->ld_buf_phys);
451 return ret;
452 }
453
454 dma_global_data.assigned[channel] = 1;
455
456 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
457 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
458 runtime->private_data = dma_private;
459
460
461
462 dma_channel = dma_private->dma_channel;
463
464 temp_link = dma_private->ld_buf_phys +
465 sizeof(struct fsl_dma_link_descriptor);
466
467 for (i = 0; i < NUM_DMA_LINKS; i++) {
468 dma_private->link[i].next = cpu_to_be64(temp_link);
469
470 temp_link += sizeof(struct fsl_dma_link_descriptor);
471 }
472
473 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
474
475
476 out_be32(&dma_channel->clndar,
477 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
478 out_be32(&dma_channel->eclndar,
479 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
480
481
482 out_be32(&dma_channel->bcr, 0);
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488 mr = in_be32(&dma_channel->mr) &
489 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
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506 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
507 CCSR_DMA_MR_EMS_EN;
508
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510
511 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
512 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
513
514 out_be32(&dma_channel->mr, mr);
515
516 return 0;
517}
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543static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
544 struct snd_pcm_hw_params *hw_params)
545{
546 struct snd_pcm_runtime *runtime = substream->runtime;
547 struct fsl_dma_private *dma_private = runtime->private_data;
548
549
550 unsigned int sample_size =
551 snd_pcm_format_physical_width(params_format(hw_params));
552
553
554 unsigned int frame_size = 2 * (sample_size / 8);
555
556
557 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
558
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560 size_t buffer_size = params_buffer_bytes(hw_params);
561
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563 size_t period_size = params_period_bytes(hw_params);
564
565
566 dma_addr_t temp_addr = substream->dma_buffer.addr;
567
568
569 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
570
571 u32 mr;
572
573 unsigned int i;
574
575
576 dma_private->period_size = period_size;
577 dma_private->num_periods = params_periods(hw_params);
578 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
579 dma_private->dma_buf_next = dma_private->dma_buf_phys +
580 (NUM_DMA_LINKS * period_size);
581
582 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
583
584 dma_private->dma_buf_next = dma_private->dma_buf_phys;
585
586 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
587 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
588
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592
593
594 switch (sample_size) {
595 case 8:
596 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
597 ssi_sxx_phys += 3;
598 break;
599 case 16:
600 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
601 ssi_sxx_phys += 2;
602 break;
603 case 32:
604 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
605 break;
606 default:
607
608 dev_err(substream->pcm->card->dev,
609 "unsupported sample size %u\n", sample_size);
610 return -EINVAL;
611 }
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621 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
622 mr |= CCSR_DMA_MR_BWC(2 * frame_size);
623 else
624 mr |= CCSR_DMA_MR_BWC(frame_size);
625
626 out_be32(&dma_channel->mr, mr);
627
628 for (i = 0; i < NUM_DMA_LINKS; i++) {
629 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
630
631 link->count = cpu_to_be32(period_size);
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655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
656 link->source_addr = cpu_to_be32(temp_addr);
657 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
658
659 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
660 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
661 } else {
662 link->source_addr = cpu_to_be32(ssi_sxx_phys);
663 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
664
665 link->dest_addr = cpu_to_be32(temp_addr);
666 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
667 }
668
669 temp_addr += period_size;
670 }
671
672 return 0;
673}
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687static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
688{
689 struct snd_pcm_runtime *runtime = substream->runtime;
690 struct fsl_dma_private *dma_private = runtime->private_data;
691 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
692 dma_addr_t position;
693 snd_pcm_uframes_t frames;
694
695 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
696 position = in_be32(&dma_channel->sar);
697 else
698 position = in_be32(&dma_channel->dar);
699
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706
707 if (!position)
708 return 0;
709
710 if ((position < dma_private->dma_buf_phys) ||
711 (position > dma_private->dma_buf_end)) {
712 dev_err(substream->pcm->card->dev,
713 "dma pointer is out of range, halting stream\n");
714 return SNDRV_PCM_POS_XRUN;
715 }
716
717 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
718
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721
722
723 if (frames == runtime->buffer_size)
724 frames = 0;
725
726 return frames;
727}
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736
737static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
738{
739 struct snd_pcm_runtime *runtime = substream->runtime;
740 struct fsl_dma_private *dma_private = runtime->private_data;
741
742 if (dma_private) {
743 struct ccsr_dma_channel __iomem *dma_channel;
744
745 dma_channel = dma_private->dma_channel;
746
747
748 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
749 out_be32(&dma_channel->mr, 0);
750
751
752 out_be32(&dma_channel->sr, -1);
753 out_be32(&dma_channel->clndar, 0);
754 out_be32(&dma_channel->eclndar, 0);
755 out_be32(&dma_channel->satr, 0);
756 out_be32(&dma_channel->sar, 0);
757 out_be32(&dma_channel->datr, 0);
758 out_be32(&dma_channel->dar, 0);
759 out_be32(&dma_channel->bcr, 0);
760 out_be32(&dma_channel->nlndar, 0);
761 out_be32(&dma_channel->enlndar, 0);
762 }
763
764 return 0;
765}
766
767
768
769
770static int fsl_dma_close(struct snd_pcm_substream *substream)
771{
772 struct snd_pcm_runtime *runtime = substream->runtime;
773 struct fsl_dma_private *dma_private = runtime->private_data;
774 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
775
776 if (dma_private) {
777 if (dma_private->irq)
778 free_irq(dma_private->irq, dma_private);
779
780 if (dma_private->ld_buf_phys) {
781 dma_unmap_single(substream->pcm->card->dev,
782 dma_private->ld_buf_phys,
783 sizeof(dma_private->link), DMA_TO_DEVICE);
784 }
785
786
787 dma_free_coherent(substream->pcm->card->dev,
788 sizeof(struct fsl_dma_private),
789 dma_private, dma_private->ld_buf_phys);
790 substream->runtime->private_data = NULL;
791 }
792
793 dma_global_data.assigned[dir] = 0;
794
795 return 0;
796}
797
798
799
800
801static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
802{
803 struct snd_pcm_substream *substream;
804 unsigned int i;
805
806 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
807 substream = pcm->streams[i].substream;
808 if (substream) {
809 snd_dma_free_pages(&substream->dma_buffer);
810 substream->dma_buffer.area = NULL;
811 substream->dma_buffer.addr = 0;
812 }
813 }
814}
815
816static struct snd_pcm_ops fsl_dma_ops = {
817 .open = fsl_dma_open,
818 .close = fsl_dma_close,
819 .ioctl = snd_pcm_lib_ioctl,
820 .hw_params = fsl_dma_hw_params,
821 .hw_free = fsl_dma_hw_free,
822 .pointer = fsl_dma_pointer,
823};
824
825struct snd_soc_platform fsl_soc_platform = {
826 .name = "fsl-dma",
827 .pcm_ops = &fsl_dma_ops,
828 .pcm_new = fsl_dma_new,
829 .pcm_free = fsl_dma_free_dma_buffers,
830};
831EXPORT_SYMBOL_GPL(fsl_soc_platform);
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843
844int fsl_dma_configure(struct fsl_dma_info *dma_info)
845{
846 static int initialized;
847
848
849 if (initialized)
850 return 0;
851
852 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys;
853 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys;
854 dma_global_data.dma_channel[0] = dma_info->dma_channel[0];
855 dma_global_data.dma_channel[1] = dma_info->dma_channel[1];
856 dma_global_data.irq[0] = dma_info->dma_irq[0];
857 dma_global_data.irq[1] = dma_info->dma_irq[1];
858 dma_global_data.assigned[0] = 0;
859 dma_global_data.assigned[1] = 0;
860
861 initialized = 1;
862 return 1;
863}
864EXPORT_SYMBOL_GPL(fsl_dma_configure);
865
866static int __init fsl_soc_platform_init(void)
867{
868 return snd_soc_register_platform(&fsl_soc_platform);
869}
870module_init(fsl_soc_platform_init);
871
872static void __exit fsl_soc_platform_exit(void)
873{
874 snd_soc_unregister_platform(&fsl_soc_platform);
875}
876module_exit(fsl_soc_platform_exit);
877
878MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
879MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module");
880MODULE_LICENSE("GPL");
881