LXR linux/arch/arm/common/timer-sp.c

   1/*
   2 *  linux/arch/arm/common/timer-sp.c
   3 *
   4 *  Copyright (C) 1999 - 2003 ARM Limited
   5 *  Copyright (C) 2000 Deep Blue Solutions Ltd
   6 *
   7 * This program is free software; you can redistribute it and/or modify
   8 * it under the terms of the GNU General Public License as published by
   9 * the Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20 */
  21#include <linux/clocksource.h>
  22#include <linux/clockchips.h>
  23#include <linux/interrupt.h>
  24#include <linux/irq.h>
  25#include <linux/io.h>
  26
  27#include <asm/hardware/arm_timer.h>
  28
  29/*
  30 * These timers are currently always setup to be clocked at 1MHz.
  31 */
  32#define TIMER_FREQ_KHZ  (1000)
  33#define TIMER_RELOAD    (TIMER_FREQ_KHZ * 1000 / HZ)
  34
  35static void __iomem *clksrc_base;
  36
  37static cycle_t sp804_read(struct clocksource *cs)
  38{
  39        return ~readl(clksrc_base + TIMER_VALUE);
  40}
  41
  42static struct clocksource clocksource_sp804 = {
  43        .name           = "timer3",
  44        .rating         = 200,
  45        .read           = sp804_read,
  46        .mask           = CLOCKSOURCE_MASK(32),
  47        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  48};
  49
  50void __init sp804_clocksource_init(void __iomem *base)
  51{
  52        struct clocksource *cs = &clocksource_sp804;
  53
  54        clksrc_base = base;
  55
  56        /* setup timer 0 as free-running clocksource */
  57        writel(0, clksrc_base + TIMER_CTRL);
  58        writel(0xffffffff, clksrc_base + TIMER_LOAD);
  59        writel(0xffffffff, clksrc_base + TIMER_VALUE);
  60        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
  61                clksrc_base + TIMER_CTRL);
  62
  63        clocksource_register_khz(cs, TIMER_FREQ_KHZ);
  64}
  65
  66
  67static void __iomem *clkevt_base;
  68
  69/*
  70 * IRQ handler for the timer
  71 */
  72static irqreturn_t sp804_timer_interrupt(int irq, void *dev_id)
  73{
  74        struct clock_event_device *evt = dev_id;
  75
  76        /* clear the interrupt */
  77        writel(1, clkevt_base + TIMER_INTCLR);
  78
  79        evt->event_handler(evt);
  80
  81        return IRQ_HANDLED;
  82}
  83
  84static void sp804_set_mode(enum clock_event_mode mode,
  85        struct clock_event_device *evt)
  86{
  87        unsigned long ctrl = TIMER_CTRL_32BIT | TIMER_CTRL_IE;
  88
  89        writel(ctrl, clkevt_base + TIMER_CTRL);
  90
  91        switch (mode) {
  92        case CLOCK_EVT_MODE_PERIODIC:
  93                writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
  94                ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
  95                break;
  96
  97        case CLOCK_EVT_MODE_ONESHOT:
  98                /* period set, and timer enabled in 'next_event' hook */
  99                ctrl |= TIMER_CTRL_ONESHOT;
 100                break;
 101
 102        case CLOCK_EVT_MODE_UNUSED:
 103        case CLOCK_EVT_MODE_SHUTDOWN:
 104        default:
 105                break;
 106        }
 107
 108        writel(ctrl, clkevt_base + TIMER_CTRL);
 109}
 110
 111static int sp804_set_next_event(unsigned long next,
 112        struct clock_event_device *evt)
 113{
 114        unsigned long ctrl = readl(clkevt_base + TIMER_CTRL);
 115
 116        writel(next, clkevt_base + TIMER_LOAD);
 117        writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL);
 118
 119        return 0;
 120}
 121
 122static struct clock_event_device sp804_clockevent = {
 123        .name           = "timer0",
 124        .shift          = 32,
 125        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 126        .set_mode       = sp804_set_mode,
 127        .set_next_event = sp804_set_next_event,
 128        .rating         = 300,
 129        .cpumask        = cpu_all_mask,
 130};
 131
 132static struct irqaction sp804_timer_irq = {
 133        .name           = "timer",
 134        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 135        .handler        = sp804_timer_interrupt,
 136        .dev_id         = &sp804_clockevent,
 137};
 138
 139void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
 140{
 141        struct clock_event_device *evt = &sp804_clockevent;
 142
 143        clkevt_base = base;
 144
 145        evt->irq = timer_irq;
 146        evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
 147        evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
 148        evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
 149
 150        setup_irq(timer_irq, &sp804_timer_irq);
 151        clockevents_register_device(evt);
 152}
 153