1/* 2 * arch/arm/include/asm/hardware/entry-macro-gic.S 3 * 4 * Low-level IRQ helper macros for GIC 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#include <asm/hardware/gic.h> 12 13#ifndef HAVE_GET_IRQNR_PREAMBLE 14 .macro get_irqnr_preamble, base, tmp 15 ldr \base, =gic_cpu_base_addr 16 ldr \base, [\base] 17 .endm 18#endif 19 20/* 21 * The interrupt numbering scheme is defined in the 22 * interrupt controller spec. To wit: 23 * 24 * Interrupts 0-15 are IPI 25 * 16-28 are reserved 26 * 29-31 are local. We allow 30 to be used for the watchdog. 27 * 32-1020 are global 28 * 1021-1022 are reserved 29 * 1023 is "spurious" (no interrupt) 30 * 31 * For now, we ignore all local interrupts so only return an interrupt if it's 32 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. 33 * 34 * A simple read from the controller will tell us the number of the highest 35 * priority enabled interrupt. We then just need to check whether it is in the 36 * valid range for an IRQ (30-1020 inclusive). 37 */ 38 39 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 40 41 ldr \irqstat, [\base, #GIC_CPU_INTACK] 42 /* bits 12-10 = src CPU, 9-0 = int # */ 43 44 ldr \tmp, =1021 45 bic \irqnr, \irqstat, #0x1c00 46 cmp \irqnr, #29 47 cmpcc \irqnr, \irqnr 48 cmpne \irqnr, \tmp 49 cmpcs \irqnr, \irqnr 50 .endm 51 52/* We assume that irqstat (the raw value of the IRQ acknowledge 53 * register) is preserved from the macro above. 54 * If there is an IPI, we immediately signal end of interrupt on the 55 * controller, since this requires the original irqstat value which 56 * we won't easily be able to recreate later. 57 */ 58 59 .macro test_for_ipi, irqnr, irqstat, base, tmp 60 bic \irqnr, \irqstat, #0x1c00 61 cmp \irqnr, #16 62 strcc \irqstat, [\base, #GIC_CPU_EOI] 63 cmpcs \irqnr, \irqnr 64 .endm 65 66/* As above, this assumes that irqstat and base are preserved.. */ 67 68 .macro test_for_ltirq, irqnr, irqstat, base, tmp 69 bic \irqnr, \irqstat, #0x1c00 70 mov \tmp, #0 71 cmp \irqnr, #29 72 moveq \tmp, #1 73 streq \irqstat, [\base, #GIC_CPU_EOI] 74 cmp \tmp, #0 75 .endm 76