linux/arch/arm/include/asm/hardware/pl330.h
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   1/* linux/include/asm/hardware/pl330.h
   2 *
   3 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
   4 *      Jaswinder Singh <jassi.brar@samsung.com>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21#ifndef __PL330_CORE_H
  22#define __PL330_CORE_H
  23
  24#define PL330_MAX_CHAN          8
  25#define PL330_MAX_IRQS          32
  26#define PL330_MAX_PERI          32
  27
  28enum pl330_srccachectrl {
  29        SCCTRL0 = 0, /* Noncacheable and nonbufferable */
  30        SCCTRL1, /* Bufferable only */
  31        SCCTRL2, /* Cacheable, but do not allocate */
  32        SCCTRL3, /* Cacheable and bufferable, but do not allocate */
  33        SINVALID1,
  34        SINVALID2,
  35        SCCTRL6, /* Cacheable write-through, allocate on reads only */
  36        SCCTRL7, /* Cacheable write-back, allocate on reads only */
  37};
  38
  39enum pl330_dstcachectrl {
  40        DCCTRL0 = 0, /* Noncacheable and nonbufferable */
  41        DCCTRL1, /* Bufferable only */
  42        DCCTRL2, /* Cacheable, but do not allocate */
  43        DCCTRL3, /* Cacheable and bufferable, but do not allocate */
  44        DINVALID1 = 8,
  45        DINVALID2,
  46        DCCTRL6, /* Cacheable write-through, allocate on writes only */
  47        DCCTRL7, /* Cacheable write-back, allocate on writes only */
  48};
  49
  50/* Populated by the PL330 core driver for DMA API driver's info */
  51struct pl330_config {
  52        u32     periph_id;
  53        u32     pcell_id;
  54#define DMAC_MODE_NS    (1 << 0)
  55        unsigned int    mode;
  56        unsigned int    data_bus_width:10; /* In number of bits */
  57        unsigned int    data_buf_dep:10;
  58        unsigned int    num_chan:4;
  59        unsigned int    num_peri:6;
  60        u32             peri_ns;
  61        unsigned int    num_events:6;
  62        u32             irq_ns;
  63};
  64
  65/* Handle to the DMAC provided to the PL330 core */
  66struct pl330_info {
  67        /* Owning device */
  68        struct device *dev;
  69        /* Size of MicroCode buffers for each channel. */
  70        unsigned mcbufsz;
  71        /* ioremap'ed address of PL330 registers. */
  72        void __iomem    *base;
  73        /* Client can freely use it. */
  74        void    *client_data;
  75        /* PL330 core data, Client must not touch it. */
  76        void    *pl330_data;
  77        /* Populated by the PL330 core driver during pl330_add */
  78        struct pl330_config     pcfg;
  79        /*
  80         * If the DMAC has some reset mechanism, then the
  81         * client may want to provide pointer to the method.
  82         */
  83        void (*dmac_reset)(struct pl330_info *pi);
  84};
  85
  86enum pl330_byteswap {
  87        SWAP_NO = 0,
  88        SWAP_2,
  89        SWAP_4,
  90        SWAP_8,
  91        SWAP_16,
  92};
  93
  94/**
  95 * Request Configuration.
  96 * The PL330 core does not modify this and uses the last
  97 * working configuration if the request doesn't provide any.
  98 *
  99 * The Client may want to provide this info only for the
 100 * first request and a request with new settings.
 101 */
 102struct pl330_reqcfg {
 103        /* Address Incrementing */
 104        unsigned dst_inc:1;
 105        unsigned src_inc:1;
 106
 107        /*
 108         * For now, the SRC & DST protection levels
 109         * and burst size/length are assumed same.
 110         */
 111        bool nonsecure;
 112        bool privileged;
 113        bool insnaccess;
 114        unsigned brst_len:5;
 115        unsigned brst_size:3; /* in power of 2 */
 116
 117        enum pl330_dstcachectrl dcctl;
 118        enum pl330_srccachectrl scctl;
 119        enum pl330_byteswap swap;
 120};
 121
 122/*
 123 * One cycle of DMAC operation.
 124 * There may be more than one xfer in a request.
 125 */
 126struct pl330_xfer {
 127        u32 src_addr;
 128        u32 dst_addr;
 129        /* Size to xfer */
 130        u32 bytes;
 131        /*
 132         * Pointer to next xfer in the list.
 133         * The last xfer in the req must point to NULL.
 134         */
 135        struct pl330_xfer *next;
 136};
 137
 138/* The xfer callbacks are made with one of these arguments. */
 139enum pl330_op_err {
 140        /* The all xfers in the request were success. */
 141        PL330_ERR_NONE,
 142        /* If req aborted due to global error. */
 143        PL330_ERR_ABORT,
 144        /* If req failed due to problem with Channel. */
 145        PL330_ERR_FAIL,
 146};
 147
 148enum pl330_reqtype {
 149        MEMTOMEM,
 150        MEMTODEV,
 151        DEVTOMEM,
 152        DEVTODEV,
 153};
 154
 155/* A request defining Scatter-Gather List ending with NULL xfer. */
 156struct pl330_req {
 157        enum pl330_reqtype rqtype;
 158        /* Index of peripheral for the xfer. */
 159        unsigned peri:5;
 160        /* Unique token for this xfer, set by the client. */
 161        void *token;
 162        /* Callback to be called after xfer. */
 163        void (*xfer_cb)(void *token, enum pl330_op_err err);
 164        /* If NULL, req will be done at last set parameters. */
 165        struct pl330_reqcfg *cfg;
 166        /* Pointer to first xfer in the request. */
 167        struct pl330_xfer *x;
 168};
 169
 170/*
 171 * To know the status of the channel and DMAC, the client
 172 * provides a pointer to this structure. The PL330 core
 173 * fills it with current information.
 174 */
 175struct pl330_chanstatus {
 176        /*
 177         * If the DMAC engine halted due to some error,
 178         * the client should remove-add DMAC.
 179         */
 180        bool dmac_halted;
 181        /*
 182         * If channel is halted due to some error,
 183         * the client should ABORT/FLUSH and START the channel.
 184         */
 185        bool faulting;
 186        /* Location of last load */
 187        u32 src_addr;
 188        /* Location of last store */
 189        u32 dst_addr;
 190        /*
 191         * Pointer to the currently active req, NULL if channel is
 192         * inactive, even though the requests may be present.
 193         */
 194        struct pl330_req *top_req;
 195        /* Pointer to req waiting second in the queue if any. */
 196        struct pl330_req *wait_req;
 197};
 198
 199enum pl330_chan_op {
 200        /* Start the channel */
 201        PL330_OP_START,
 202        /* Abort the active xfer */
 203        PL330_OP_ABORT,
 204        /* Stop xfer and flush queue */
 205        PL330_OP_FLUSH,
 206};
 207
 208extern int pl330_add(struct pl330_info *);
 209extern void pl330_del(struct pl330_info *pi);
 210extern int pl330_update(const struct pl330_info *pi);
 211extern void pl330_release_channel(void *ch_id);
 212extern void *pl330_request_channel(const struct pl330_info *pi);
 213extern int pl330_chan_status(void *ch_id, struct pl330_chanstatus *pstatus);
 214extern int pl330_chan_ctrl(void *ch_id, enum pl330_chan_op op);
 215extern int pl330_submit_req(void *ch_id, struct pl330_req *r);
 216
 217#endif  /* __PL330_CORE_H */
 218
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