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13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/fs.h>
17#include <linux/debugfs.h>
18#include <linux/seq_file.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/spinlock.h>
23#include <linux/delay.h>
24#include <linux/clk.h>
25#include <linux/io.h>
26
27#include <mach/hardware.h>
28#include <mach/at91_pmc.h>
29#include <mach/cpu.h>
30
31#include "clock.h"
32#include "generic.h"
33
34
35
36
37
38
39
40
41#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
42#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
43#define clk_is_peripheral(x) ((x)->type & CLK_TYPE_PERIPHERAL)
44#define clk_is_sys(x) ((x)->type & CLK_TYPE_SYSTEM)
45
46
47
48
49
50#define cpu_has_utmi() ( cpu_is_at91cap9() \
51 || cpu_is_at91sam9rl() \
52 || cpu_is_at91sam9g45())
53
54#define cpu_has_800M_plla() ( cpu_is_at91sam9g20() \
55 || cpu_is_at91sam9g45())
56
57#define cpu_has_300M_plla() (cpu_is_at91sam9g10())
58
59#define cpu_has_pllb() (!(cpu_is_at91sam9rl() \
60 || cpu_is_at91sam9g45()))
61
62#define cpu_has_upll() (cpu_is_at91sam9g45())
63
64
65#define cpu_has_uhp() (!cpu_is_at91sam9rl())
66
67
68#define cpu_has_udpfs() (!(cpu_is_at91sam9rl() \
69 || cpu_is_at91sam9g45()))
70
71static LIST_HEAD(clocks);
72static DEFINE_SPINLOCK(clk_lock);
73
74static u32 at91_pllb_usb_init;
75
76
77
78
79
80
81
82static struct clk clk32k = {
83 .name = "clk32k",
84 .rate_hz = AT91_SLOW_CLOCK,
85 .users = 1,
86 .id = 0,
87 .type = CLK_TYPE_PRIMARY,
88};
89static struct clk main_clk = {
90 .name = "main",
91 .pmc_mask = AT91_PMC_MOSCS,
92 .id = 1,
93 .type = CLK_TYPE_PRIMARY,
94};
95static struct clk plla = {
96 .name = "plla",
97 .parent = &main_clk,
98 .pmc_mask = AT91_PMC_LOCKA,
99 .id = 2,
100 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
101};
102
103static void pllb_mode(struct clk *clk, int is_on)
104{
105 u32 value;
106
107 if (is_on) {
108 is_on = AT91_PMC_LOCKB;
109 value = at91_pllb_usb_init;
110 } else
111 value = 0;
112
113
114 at91_sys_write(AT91_CKGR_PLLBR, value);
115
116 do {
117 cpu_relax();
118 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
119}
120
121static struct clk pllb = {
122 .name = "pllb",
123 .parent = &main_clk,
124 .pmc_mask = AT91_PMC_LOCKB,
125 .mode = pllb_mode,
126 .id = 3,
127 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
128};
129
130static void pmc_sys_mode(struct clk *clk, int is_on)
131{
132 if (is_on)
133 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
134 else
135 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
136}
137
138static void pmc_uckr_mode(struct clk *clk, int is_on)
139{
140 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
141
142 if (cpu_is_at91sam9g45()) {
143 if (is_on)
144 uckr |= AT91_PMC_BIASEN;
145 else
146 uckr &= ~AT91_PMC_BIASEN;
147 }
148
149 if (is_on) {
150 is_on = AT91_PMC_LOCKU;
151 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
152 } else
153 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
154
155 do {
156 cpu_relax();
157 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
158}
159
160
161static struct clk udpck = {
162 .name = "udpck",
163 .parent = &pllb,
164 .mode = pmc_sys_mode,
165};
166static struct clk utmi_clk = {
167 .name = "utmi_clk",
168 .parent = &main_clk,
169 .pmc_mask = AT91_PMC_UPLLEN,
170 .mode = pmc_uckr_mode,
171 .type = CLK_TYPE_PLL,
172};
173static struct clk uhpck = {
174 .name = "uhpck",
175
176 .mode = pmc_sys_mode,
177};
178
179
180
181
182
183
184
185static struct clk mck = {
186 .name = "mck",
187 .pmc_mask = AT91_PMC_MCKRDY,
188};
189
190static void pmc_periph_mode(struct clk *clk, int is_on)
191{
192 if (is_on)
193 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
194 else
195 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
196}
197
198static struct clk __init *at91_css_to_clk(unsigned long css)
199{
200 switch (css) {
201 case AT91_PMC_CSS_SLOW:
202 return &clk32k;
203 case AT91_PMC_CSS_MAIN:
204 return &main_clk;
205 case AT91_PMC_CSS_PLLA:
206 return &plla;
207 case AT91_PMC_CSS_PLLB:
208 if (cpu_has_upll())
209
210 return &utmi_clk;
211 else if (cpu_has_pllb())
212 return &pllb;
213 }
214
215 return NULL;
216}
217
218
219
220
221
222
223void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
224{
225 struct clk *clk = clk_get(NULL, id);
226
227 if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
228 return;
229
230 clk->function = func;
231 clk->dev = dev;
232}
233
234
235struct clk *clk_get(struct device *dev, const char *id)
236{
237 struct clk *clk;
238
239 list_for_each_entry(clk, &clocks, node) {
240 if (strcmp(id, clk->name) == 0)
241 return clk;
242 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
243 return clk;
244 }
245
246 return ERR_PTR(-ENOENT);
247}
248EXPORT_SYMBOL(clk_get);
249
250void clk_put(struct clk *clk)
251{
252}
253EXPORT_SYMBOL(clk_put);
254
255static void __clk_enable(struct clk *clk)
256{
257 if (clk->parent)
258 __clk_enable(clk->parent);
259 if (clk->users++ == 0 && clk->mode)
260 clk->mode(clk, 1);
261}
262
263int clk_enable(struct clk *clk)
264{
265 unsigned long flags;
266
267 spin_lock_irqsave(&clk_lock, flags);
268 __clk_enable(clk);
269 spin_unlock_irqrestore(&clk_lock, flags);
270 return 0;
271}
272EXPORT_SYMBOL(clk_enable);
273
274static void __clk_disable(struct clk *clk)
275{
276 BUG_ON(clk->users == 0);
277 if (--clk->users == 0 && clk->mode)
278 clk->mode(clk, 0);
279 if (clk->parent)
280 __clk_disable(clk->parent);
281}
282
283void clk_disable(struct clk *clk)
284{
285 unsigned long flags;
286
287 spin_lock_irqsave(&clk_lock, flags);
288 __clk_disable(clk);
289 spin_unlock_irqrestore(&clk_lock, flags);
290}
291EXPORT_SYMBOL(clk_disable);
292
293unsigned long clk_get_rate(struct clk *clk)
294{
295 unsigned long flags;
296 unsigned long rate;
297
298 spin_lock_irqsave(&clk_lock, flags);
299 for (;;) {
300 rate = clk->rate_hz;
301 if (rate || !clk->parent)
302 break;
303 clk = clk->parent;
304 }
305 spin_unlock_irqrestore(&clk_lock, flags);
306 return rate;
307}
308EXPORT_SYMBOL(clk_get_rate);
309
310
311
312#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
313
314
315
316
317
318
319
320
321long clk_round_rate(struct clk *clk, unsigned long rate)
322{
323 unsigned long flags;
324 unsigned prescale;
325 unsigned long actual;
326 unsigned long prev = ULONG_MAX;
327
328 if (!clk_is_programmable(clk))
329 return -EINVAL;
330 spin_lock_irqsave(&clk_lock, flags);
331
332 actual = clk->parent->rate_hz;
333 for (prescale = 0; prescale < 7; prescale++) {
334 if (actual > rate)
335 prev = actual;
336
337 if (actual && actual <= rate) {
338 if ((prev - rate) < (rate - actual)) {
339 actual = prev;
340 prescale--;
341 }
342 break;
343 }
344 actual >>= 1;
345 }
346
347 spin_unlock_irqrestore(&clk_lock, flags);
348 return (prescale < 7) ? actual : -ENOENT;
349}
350EXPORT_SYMBOL(clk_round_rate);
351
352int clk_set_rate(struct clk *clk, unsigned long rate)
353{
354 unsigned long flags;
355 unsigned prescale;
356 unsigned long actual;
357
358 if (!clk_is_programmable(clk))
359 return -EINVAL;
360 if (clk->users)
361 return -EBUSY;
362 spin_lock_irqsave(&clk_lock, flags);
363
364 actual = clk->parent->rate_hz;
365 for (prescale = 0; prescale < 7; prescale++) {
366 if (actual && actual <= rate) {
367 u32 pckr;
368
369 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
370 pckr &= AT91_PMC_CSS;
371 pckr |= prescale << 2;
372 at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
373 clk->rate_hz = actual;
374 break;
375 }
376 actual >>= 1;
377 }
378
379 spin_unlock_irqrestore(&clk_lock, flags);
380 return (prescale < 7) ? actual : -ENOENT;
381}
382EXPORT_SYMBOL(clk_set_rate);
383
384struct clk *clk_get_parent(struct clk *clk)
385{
386 return clk->parent;
387}
388EXPORT_SYMBOL(clk_get_parent);
389
390int clk_set_parent(struct clk *clk, struct clk *parent)
391{
392 unsigned long flags;
393
394 if (clk->users)
395 return -EBUSY;
396 if (!clk_is_primary(parent) || !clk_is_programmable(clk))
397 return -EINVAL;
398
399 if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
400 return -EINVAL;
401
402 spin_lock_irqsave(&clk_lock, flags);
403
404 clk->rate_hz = parent->rate_hz;
405 clk->parent = parent;
406 at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
407
408 spin_unlock_irqrestore(&clk_lock, flags);
409 return 0;
410}
411EXPORT_SYMBOL(clk_set_parent);
412
413
414static void __init init_programmable_clock(struct clk *clk)
415{
416 struct clk *parent;
417 u32 pckr;
418
419 pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
420 parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
421 clk->parent = parent;
422 clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
423}
424
425#endif
426
427
428
429#ifdef CONFIG_DEBUG_FS
430
431static int at91_clk_show(struct seq_file *s, void *unused)
432{
433 u32 scsr, pcsr, uckr = 0, sr;
434 struct clk *clk;
435
436 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
437 seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
438 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
439 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
440 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
441 if (cpu_has_pllb())
442 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
443 if (cpu_has_utmi())
444 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
445 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
446 if (cpu_has_upll())
447 seq_printf(s, "USB = %8x\n", at91_sys_read(AT91_PMC_USB));
448 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
449
450 seq_printf(s, "\n");
451
452 list_for_each_entry(clk, &clocks, node) {
453 char *state;
454
455 if (clk->mode == pmc_sys_mode)
456 state = (scsr & clk->pmc_mask) ? "on" : "off";
457 else if (clk->mode == pmc_periph_mode)
458 state = (pcsr & clk->pmc_mask) ? "on" : "off";
459 else if (clk->mode == pmc_uckr_mode)
460 state = (uckr & clk->pmc_mask) ? "on" : "off";
461 else if (clk->pmc_mask)
462 state = (sr & clk->pmc_mask) ? "on" : "off";
463 else if (clk == &clk32k || clk == &main_clk)
464 state = "on";
465 else
466 state = "";
467
468 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
469 clk->name, clk->users, state, clk_get_rate(clk),
470 clk->parent ? clk->parent->name : "");
471 }
472 return 0;
473}
474
475static int at91_clk_open(struct inode *inode, struct file *file)
476{
477 return single_open(file, at91_clk_show, NULL);
478}
479
480static const struct file_operations at91_clk_operations = {
481 .open = at91_clk_open,
482 .read = seq_read,
483 .llseek = seq_lseek,
484 .release = single_release,
485};
486
487static int __init at91_clk_debugfs_init(void)
488{
489
490 (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
491
492 return 0;
493}
494postcore_initcall(at91_clk_debugfs_init);
495
496#endif
497
498
499
500
501int __init clk_register(struct clk *clk)
502{
503 if (clk_is_peripheral(clk)) {
504 if (!clk->parent)
505 clk->parent = &mck;
506 clk->mode = pmc_periph_mode;
507 list_add_tail(&clk->node, &clocks);
508 }
509 else if (clk_is_sys(clk)) {
510 clk->parent = &mck;
511 clk->mode = pmc_sys_mode;
512
513 list_add_tail(&clk->node, &clocks);
514 }
515#ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
516 else if (clk_is_programmable(clk)) {
517 clk->mode = pmc_sys_mode;
518 init_programmable_clock(clk);
519 list_add_tail(&clk->node, &clocks);
520 }
521#endif
522
523 return 0;
524}
525
526
527
528
529static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
530{
531 unsigned mul, div;
532
533 div = reg & 0xff;
534 mul = (reg >> 16) & 0x7ff;
535 if (div && mul) {
536 freq /= div;
537 freq *= mul + 1;
538 } else
539 freq = 0;
540
541 return freq;
542}
543
544static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
545{
546 if (pll == &pllb && (reg & AT91_PMC_USB96M))
547 return freq / 2;
548 else
549 return freq;
550}
551
552static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
553{
554 unsigned i, div = 0, mul = 0, diff = 1 << 30;
555 unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
556
557
558 if (out_freq > 240000000)
559 goto fail;
560
561 for (i = 1; i < 256; i++) {
562 int diff1;
563 unsigned input, mul1;
564
565
566
567
568
569
570 input = main_freq / i;
571 if (cpu_is_at91sam9g20() && input < 2000000)
572 continue;
573 if (input < 100000)
574 continue;
575 if (input > 32000000)
576 continue;
577
578 mul1 = out_freq / input;
579 if (cpu_is_at91sam9g20() && mul > 63)
580 continue;
581 if (mul1 > 2048)
582 continue;
583 if (mul1 < 2)
584 goto fail;
585
586 diff1 = out_freq - input * mul1;
587 if (diff1 < 0)
588 diff1 = -diff1;
589 if (diff > diff1) {
590 diff = diff1;
591 div = i;
592 mul = mul1;
593 if (diff == 0)
594 break;
595 }
596 }
597 if (i == 256 && diff > (out_freq >> 5))
598 goto fail;
599 return ret | ((mul - 1) << 16) | div;
600fail:
601 return 0;
602}
603
604static struct clk *const standard_pmc_clocks[] __initdata = {
605
606 &clk32k,
607 &main_clk,
608 &plla,
609
610
611 &mck
612};
613
614
615static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
616{
617
618
619
620
621
622
623 uhpck.parent = &pllb;
624
625 at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
626 pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
627 if (cpu_is_at91rm9200()) {
628 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
629 udpck.pmc_mask = AT91RM9200_PMC_UDP;
630 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
631 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
632 cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
633 cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
634 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
635 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
636 } else if (cpu_is_at91cap9()) {
637 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
638 }
639 at91_sys_write(AT91_CKGR_PLLBR, 0);
640
641 udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
642 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
643}
644
645
646static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
647{
648
649
650
651 unsigned int usbr = AT91_PMC_USBS_UPLL;
652
653
654 usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
655
656 at91_sys_write(AT91_PMC_USB, usbr);
657
658
659 uhpck.parent = &utmi_clk;
660 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
661 uhpck.rate_hz = utmi_clk.rate_hz;
662 uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
663}
664
665int __init at91_clock_init(unsigned long main_clock)
666{
667 unsigned tmp, freq, mckr;
668 int i;
669 int pll_overclock = false;
670
671
672
673
674
675
676
677 if (!main_clock) {
678 do {
679 tmp = at91_sys_read(AT91_CKGR_MCFR);
680 } while (!(tmp & AT91_PMC_MAINRDY));
681 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
682 }
683 main_clk.rate_hz = main_clock;
684
685
686 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
687 if (cpu_has_300M_plla()) {
688 if (plla.rate_hz > 300000000)
689 pll_overclock = true;
690 } else if (cpu_has_800M_plla()) {
691 if (plla.rate_hz > 800000000)
692 pll_overclock = true;
693 } else {
694 if (plla.rate_hz > 209000000)
695 pll_overclock = true;
696 }
697 if (pll_overclock)
698 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
699
700 if (cpu_is_at91sam9g45()) {
701 mckr = at91_sys_read(AT91_PMC_MCKR);
702 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));
703 }
704
705 if (!cpu_has_pllb() && cpu_has_upll()) {
706
707
708 utmi_clk.type |= CLK_TYPE_PRIMARY;
709 utmi_clk.id = 3;
710 }
711
712
713
714
715
716 if (cpu_has_utmi()) {
717
718
719
720
721 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
722 }
723
724
725
726
727 if (cpu_has_pllb())
728 at91_pllb_usbfs_clock_init(main_clock);
729 if (cpu_has_upll())
730
731 at91_upll_usbfs_clock_init(main_clock);
732
733
734
735
736
737 mckr = at91_sys_read(AT91_PMC_MCKR);
738 mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
739 freq = mck.parent->rate_hz;
740 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));
741 if (cpu_is_at91rm9200()) {
742 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));
743 } else if (cpu_is_at91sam9g20()) {
744 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
745 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;
746 if (mckr & AT91_PMC_PDIV)
747 freq /= 2;
748 } else if (cpu_is_at91sam9g45()) {
749 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
750 freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));
751 } else {
752 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));
753 }
754
755
756 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
757 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
758
759 if (cpu_has_pllb())
760 list_add_tail(&pllb.node, &clocks);
761
762 if (cpu_has_uhp())
763 list_add_tail(&uhpck.node, &clocks);
764
765 if (cpu_has_udpfs())
766 list_add_tail(&udpck.node, &clocks);
767
768 if (cpu_has_utmi())
769 list_add_tail(&utmi_clk.node, &clocks);
770
771
772 clk_enable(&mck);
773
774 printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
775 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
776 (unsigned) main_clock / 1000000,
777 ((unsigned) main_clock % 1000000) / 1000);
778
779 return 0;
780}
781
782
783
784
785static int __init at91_clock_reset(void)
786{
787 unsigned long pcdr = 0;
788 unsigned long scdr = 0;
789 struct clk *clk;
790
791 list_for_each_entry(clk, &clocks, node) {
792 if (clk->users > 0)
793 continue;
794
795 if (clk->mode == pmc_periph_mode)
796 pcdr |= clk->pmc_mask;
797
798 if (clk->mode == pmc_sys_mode)
799 scdr |= clk->pmc_mask;
800
801 pr_debug("Clocks: disable unused %s\n", clk->name);
802 }
803
804 at91_sys_write(AT91_PMC_PCDR, pcdr);
805 at91_sys_write(AT91_PMC_SCDR, scdr);
806
807 return 0;
808}
809late_initcall(at91_clock_reset);
810