LXR linux/arch/arm/mach-davinci/irq.c

   1/*
   2 * Interrupt handler for DaVinci boards.
   3 *
   4 * Copyright (C) 2006 Texas Instruments.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as published by
   8 * the Free Software Foundation; either version 2 of the License, or
   9 * (at your option) any later version.
  10 *
  11 * This program is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 *
  20 */
  21#include <linux/kernel.h>
  22#include <linux/init.h>
  23#include <linux/interrupt.h>
  24#include <linux/irq.h>
  25#include <linux/io.h>
  26
  27#include <mach/hardware.h>
  28#include <mach/cputype.h>
  29#include <mach/common.h>
  30#include <asm/mach/irq.h>
  31
  32#define IRQ_BIT(irq)            ((irq) & 0x1f)
  33
  34#define FIQ_REG0_OFFSET         0x0000
  35#define FIQ_REG1_OFFSET         0x0004
  36#define IRQ_REG0_OFFSET         0x0008
  37#define IRQ_REG1_OFFSET         0x000C
  38#define IRQ_ENT_REG0_OFFSET     0x0018
  39#define IRQ_ENT_REG1_OFFSET     0x001C
  40#define IRQ_INCTL_REG_OFFSET    0x0020
  41#define IRQ_EABASE_REG_OFFSET   0x0024
  42#define IRQ_INTPRI0_REG_OFFSET  0x0030
  43#define IRQ_INTPRI7_REG_OFFSET  0x004C
  44
  45static inline unsigned int davinci_irq_readl(int offset)
  46{
  47        return __raw_readl(davinci_intc_base + offset);
  48}
  49
  50static inline void davinci_irq_writel(unsigned long value, int offset)
  51{
  52        __raw_writel(value, davinci_intc_base + offset);
  53}
  54
  55/* Disable interrupt */
  56static void davinci_mask_irq(struct irq_data *d)
  57{
  58        unsigned int mask;
  59        u32 l;
  60
  61        mask = 1 << IRQ_BIT(d->irq);
  62
  63        if (d->irq > 31) {
  64                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
  65                l &= ~mask;
  66                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
  67        } else {
  68                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
  69                l &= ~mask;
  70                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
  71        }
  72}
  73
  74/* Enable interrupt */
  75static void davinci_unmask_irq(struct irq_data *d)
  76{
  77        unsigned int mask;
  78        u32 l;
  79
  80        mask = 1 << IRQ_BIT(d->irq);
  81
  82        if (d->irq > 31) {
  83                l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
  84                l |= mask;
  85                davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
  86        } else {
  87                l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
  88                l |= mask;
  89                davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
  90        }
  91}
  92
  93/* EOI interrupt */
  94static void davinci_ack_irq(struct irq_data *d)
  95{
  96        unsigned int mask;
  97
  98        mask = 1 << IRQ_BIT(d->irq);
  99
 100        if (d->irq > 31)
 101                davinci_irq_writel(mask, IRQ_REG1_OFFSET);
 102        else
 103                davinci_irq_writel(mask, IRQ_REG0_OFFSET);
 104}
 105
 106static struct irq_chip davinci_irq_chip_0 = {
 107        .name           = "AINTC",
 108        .irq_ack        = davinci_ack_irq,
 109        .irq_mask       = davinci_mask_irq,
 110        .irq_unmask     = davinci_unmask_irq,
 111};
 112
 113/* ARM Interrupt Controller Initialization */
 114void __init davinci_irq_init(void)
 115{
 116        unsigned i;
 117        const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
 118
 119        davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
 120        davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_4K);
 121        if (WARN_ON(!davinci_intc_base))
 122                return;
 123
 124        /* Clear all interrupt requests */
 125        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
 126        davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
 127        davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
 128        davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 129
 130        /* Disable all interrupts */
 131        davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
 132        davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
 133
 134        /* Interrupts disabled immediately, IRQ entry reflects all */
 135        davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
 136
 137        /* we don't use the hardware vector table, just its entry addresses */
 138        davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
 139
 140        /* Clear all interrupt requests */
 141        davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
 142        davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
 143        davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
 144        davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
 145
 146        for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
 147                unsigned        j;
 148                u32             pri;
 149
 150                for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
 151                        pri |= (*davinci_def_priorities & 0x07) << j;
 152                davinci_irq_writel(pri, i);
 153        }
 154
 155        /* set up genirq dispatch for ARM INTC */
 156        for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
 157                set_irq_chip(i, &davinci_irq_chip_0);
 158                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 159                if (i != IRQ_TINT1_TINT34)
 160                        set_irq_handler(i, handle_edge_irq);
 161                else
 162                        set_irq_handler(i, handle_level_irq);
 163        }
 164}
 165