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17#include <linux/ioport.h>
18#include <linux/interrupt.h>
19#include <linux/list.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/spinlock.h>
23
24#include <asm/mach/irq.h>
25
26#include <mach/hardware.h>
27#include <asm/hardware/dec21285.h>
28#include <asm/irq.h>
29#include <asm/mach-types.h>
30
31#include "common.h"
32
33static void isa_mask_pic_lo_irq(struct irq_data *d)
34{
35 unsigned int mask = 1 << (d->irq & 7);
36
37 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
38}
39
40static void isa_ack_pic_lo_irq(struct irq_data *d)
41{
42 unsigned int mask = 1 << (d->irq & 7);
43
44 outb(inb(PIC_MASK_LO) | mask, PIC_MASK_LO);
45 outb(0x20, PIC_LO);
46}
47
48static void isa_unmask_pic_lo_irq(struct irq_data *d)
49{
50 unsigned int mask = 1 << (d->irq & 7);
51
52 outb(inb(PIC_MASK_LO) & ~mask, PIC_MASK_LO);
53}
54
55static struct irq_chip isa_lo_chip = {
56 .irq_ack = isa_ack_pic_lo_irq,
57 .irq_mask = isa_mask_pic_lo_irq,
58 .irq_unmask = isa_unmask_pic_lo_irq,
59};
60
61static void isa_mask_pic_hi_irq(struct irq_data *d)
62{
63 unsigned int mask = 1 << (d->irq & 7);
64
65 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
66}
67
68static void isa_ack_pic_hi_irq(struct irq_data *d)
69{
70 unsigned int mask = 1 << (d->irq & 7);
71
72 outb(inb(PIC_MASK_HI) | mask, PIC_MASK_HI);
73 outb(0x62, PIC_LO);
74 outb(0x20, PIC_HI);
75}
76
77static void isa_unmask_pic_hi_irq(struct irq_data *d)
78{
79 unsigned int mask = 1 << (d->irq & 7);
80
81 outb(inb(PIC_MASK_HI) & ~mask, PIC_MASK_HI);
82}
83
84static struct irq_chip isa_hi_chip = {
85 .irq_ack = isa_ack_pic_hi_irq,
86 .irq_mask = isa_mask_pic_hi_irq,
87 .irq_unmask = isa_unmask_pic_hi_irq,
88};
89
90static void
91isa_irq_handler(unsigned int irq, struct irq_desc *desc)
92{
93 unsigned int isa_irq = *(unsigned char *)PCIIACK_BASE;
94
95 if (isa_irq < _ISA_IRQ(0) || isa_irq >= _ISA_IRQ(16)) {
96 do_bad_IRQ(isa_irq, desc);
97 return;
98 }
99
100 generic_handle_irq(isa_irq);
101}
102
103static struct irqaction irq_cascade = {
104 .handler = no_action,
105 .name = "cascade",
106};
107
108static struct resource pic1_resource = {
109 .name = "pic1",
110 .start = 0x20,
111 .end = 0x3f,
112};
113
114static struct resource pic2_resource = {
115 .name = "pic2",
116 .start = 0xa0,
117 .end = 0xbf,
118};
119
120void __init isa_init_irq(unsigned int host_irq)
121{
122 unsigned int irq;
123
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126
127
128
129 outb(0x11, PIC_LO);
130 outb(_ISA_IRQ(0), PIC_MASK_LO);
131 outb(0x04, PIC_MASK_LO);
132 outb(0x01, PIC_MASK_LO);
133 outb(0xf5, PIC_MASK_LO);
134
135 outb(0x11, PIC_HI);
136 outb(_ISA_IRQ(8), PIC_MASK_HI);
137 outb(0x02, PIC_MASK_HI);
138 outb(0x01, PIC_MASK_HI);
139 outb(0xfa, PIC_MASK_HI);
140
141 outb(0x0b, PIC_LO);
142 outb(0x0b, PIC_HI);
143
144 if (inb(PIC_MASK_LO) == 0xf5 && inb(PIC_MASK_HI) == 0xfa) {
145 outb(0xff, PIC_MASK_LO);
146 outb(0xff, PIC_MASK_HI);
147 } else {
148 printk(KERN_INFO "IRQ: ISA PIC not found\n");
149 host_irq = (unsigned int)-1;
150 }
151
152 if (host_irq != (unsigned int)-1) {
153 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
154 set_irq_chip(irq, &isa_lo_chip);
155 set_irq_handler(irq, handle_level_irq);
156 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
157 }
158
159 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
160 set_irq_chip(irq, &isa_hi_chip);
161 set_irq_handler(irq, handle_level_irq);
162 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
163 }
164
165 request_resource(&ioport_resource, &pic1_resource);
166 request_resource(&ioport_resource, &pic2_resource);
167 setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
168
169 set_irq_chained_handler(host_irq, isa_irq_handler);
170
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176
177 if (machine_is_netwinder())
178 set_irq_flags(_ISA_IRQ(11), IRQF_VALID |
179 IRQF_PROBE | IRQF_NOAUTOEN);
180 }
181}
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