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20#include <linux/pci.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/jiffies.h>
24#include <asm/irq.h>
25#include <mach/hardware.h>
26#include <asm/sizes.h>
27#include <asm/signal.h>
28#include <asm/mach/pci.h>
29#include <mach/pci.h>
30
31#define IOP13XX_PCI_DEBUG 0
32#define PRINTK(x...) ((void)(IOP13XX_PCI_DEBUG && printk(x)))
33
34u32 iop13xx_atux_pmmr_offset;
35u32 iop13xx_atue_pmmr_offset;
36static struct pci_bus *pci_bus_atux = 0;
37static struct pci_bus *pci_bus_atue = 0;
38u32 iop13xx_atue_mem_base;
39u32 iop13xx_atux_mem_base;
40size_t iop13xx_atue_mem_size;
41size_t iop13xx_atux_mem_size;
42unsigned long iop13xx_pcibios_min_io = 0;
43unsigned long iop13xx_pcibios_min_mem = 0;
44
45EXPORT_SYMBOL(iop13xx_atue_mem_base);
46EXPORT_SYMBOL(iop13xx_atux_mem_base);
47EXPORT_SYMBOL(iop13xx_atue_mem_size);
48EXPORT_SYMBOL(iop13xx_atux_mem_size);
49
50int init_atu = 0;
51static unsigned long atux_trhfa_timeout = 0;
52
53
54
55
56void iop13xx_map_pci_memory(void)
57{
58 int atu;
59 struct pci_bus *bus;
60 struct pci_dev *dev;
61 resource_size_t end = 0;
62
63 for (atu = 0; atu < 2; atu++) {
64 bus = atu ? pci_bus_atue : pci_bus_atux;
65 if (bus) {
66 list_for_each_entry(dev, &bus->devices, bus_list) {
67 int i;
68 int max = 7;
69
70 if (dev->subordinate)
71 max = DEVICE_COUNT_RESOURCE;
72
73 for (i = 0; i < max; i++) {
74 struct resource *res = &dev->resource[i];
75 if (res->flags & IORESOURCE_MEM)
76 end = max(res->end, end);
77 }
78 }
79
80 switch(atu) {
81 case 0:
82 iop13xx_atux_mem_size =
83 (end - IOP13XX_PCIX_LOWER_MEM_RA) + 1;
84
85
86 if (iop13xx_atux_mem_size & (SZ_16M - 1)) {
87 iop13xx_atux_mem_size &= ~(SZ_16M - 1);
88 iop13xx_atux_mem_size += SZ_16M;
89 }
90
91 if (end) {
92 iop13xx_atux_mem_base =
93 (u32) __arm_ioremap_pfn(
94 __phys_to_pfn(IOP13XX_PCIX_LOWER_MEM_PA)
95 , 0, iop13xx_atux_mem_size, MT_DEVICE);
96 if (!iop13xx_atux_mem_base) {
97 printk("%s: atux allocation "
98 "failed\n", __func__);
99 BUG();
100 }
101 } else
102 iop13xx_atux_mem_size = 0;
103 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
104 __func__, atu, iop13xx_atux_mem_size,
105 iop13xx_atux_mem_base);
106 break;
107 case 1:
108 iop13xx_atue_mem_size =
109 (end - IOP13XX_PCIE_LOWER_MEM_RA) + 1;
110
111
112 if (iop13xx_atue_mem_size & (SZ_16M - 1)) {
113 iop13xx_atue_mem_size &= ~(SZ_16M - 1);
114 iop13xx_atue_mem_size += SZ_16M;
115 }
116
117 if (end) {
118 iop13xx_atue_mem_base =
119 (u32) __arm_ioremap_pfn(
120 __phys_to_pfn(IOP13XX_PCIE_LOWER_MEM_PA)
121 , 0, iop13xx_atue_mem_size, MT_DEVICE);
122 if (!iop13xx_atue_mem_base) {
123 printk("%s: atue allocation "
124 "failed\n", __func__);
125 BUG();
126 }
127 } else
128 iop13xx_atue_mem_size = 0;
129 PRINTK("%s: atu: %d bus_size: %d mem_base: %x\n",
130 __func__, atu, iop13xx_atue_mem_size,
131 iop13xx_atue_mem_base);
132 break;
133 }
134
135 printk("%s: Initialized (%uM @ resource/virtual: %08lx/%08x)\n",
136 atu ? "ATUE" : "ATUX",
137 (atu ? iop13xx_atue_mem_size : iop13xx_atux_mem_size) /
138 SZ_1M,
139 atu ? IOP13XX_PCIE_LOWER_MEM_RA :
140 IOP13XX_PCIX_LOWER_MEM_RA,
141 atu ? iop13xx_atue_mem_base :
142 iop13xx_atux_mem_base);
143 end = 0;
144 }
145
146 }
147}
148
149static int iop13xx_atu_function(int atu)
150{
151 int func = 0;
152
153
154
155
156 switch(atu) {
157 case IOP13XX_INIT_ATU_ATUX:
158 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
159 func = 5;
160 else
161 func = 0;
162 break;
163 case IOP13XX_INIT_ATU_ATUE:
164 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
165 func = 0;
166 else
167 func = 5;
168 break;
169 default:
170 BUG();
171 }
172
173 return func;
174}
175
176
177
178
179
180
181
182
183
184static u32 iop13xx_atux_cfg_address(struct pci_bus *bus, int devfn, int where)
185{
186 struct pci_sys_data *sys = bus->sysdata;
187 u32 addr;
188
189 if (sys->busnr == bus->number)
190 addr = 1 << (PCI_SLOT(devfn) + 16) | (PCI_SLOT(devfn) << 11);
191 else
192 addr = bus->number << 16 | PCI_SLOT(devfn) << 11 | 1;
193
194 addr |= PCI_FUNC(devfn) << 8 | ((where & 0xff) & ~3);
195 addr |= ((where & 0xf00) >> 8) << 24;
196
197 return addr;
198}
199
200
201
202
203
204
205
206
207static u32 iop13xx_atue_cfg_address(struct pci_bus *bus, int devfn, int where)
208{
209 struct pci_sys_data *sys = bus->sysdata;
210 u32 addr;
211
212 PRINTK("iop13xx_atue_cfg_address: bus: %d dev: %d func: %d",
213 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
214 addr = ((u32) bus->number) << IOP13XX_ATUE_OCCAR_BUS_NUM |
215 ((u32) PCI_SLOT(devfn)) << IOP13XX_ATUE_OCCAR_DEV_NUM |
216 ((u32) PCI_FUNC(devfn)) << IOP13XX_ATUE_OCCAR_FUNC_NUM |
217 (where & ~0x3);
218
219 if (sys->busnr != bus->number)
220 addr |= 1;
221
222 return addr;
223}
224
225
226
227
228
229
230
231static int iop13xx_atux_pci_status(int clear)
232{
233 unsigned int status;
234 int err = 0;
235
236
237
238
239 status = __raw_readw(IOP13XX_ATUX_ATUSR);
240 if (status & IOP_PCI_STATUS_ERROR)
241 {
242 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
243 if(clear)
244 __raw_writew(status & IOP_PCI_STATUS_ERROR,
245 IOP13XX_ATUX_ATUSR);
246 err = 1;
247 }
248 status = __raw_readl(IOP13XX_ATUX_ATUISR);
249 if (status & IOP13XX_ATUX_ATUISR_ERROR)
250 {
251 PRINTK("\t\t\tPCI error interrupt: ATUISR %#08x", status);
252 if(clear)
253 __raw_writel(status & IOP13XX_ATUX_ATUISR_ERROR,
254 IOP13XX_ATUX_ATUISR);
255 err = 1;
256 }
257 return err;
258}
259
260
261
262
263
264static u32 iop13xx_atux_read(unsigned long addr)
265{
266 u32 val;
267
268 __asm__ __volatile__(
269 "str %1, [%2]\n\t"
270 "ldr %0, [%3]\n\t"
271 "mov %0, %0\n\t"
272 : "=r" (val)
273 : "r" (addr), "r" (IOP13XX_ATUX_OCCAR), "r" (IOP13XX_ATUX_OCCDR));
274
275 return val;
276}
277
278
279
280
281static int
282iop13xx_atux_read_config(struct pci_bus *bus, unsigned int devfn, int where,
283 int size, u32 *value)
284{
285 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
286 u32 val = iop13xx_atux_read(addr) >> ((where & 3) * 8);
287
288 if (iop13xx_atux_pci_status(1) || is_atux_occdr_error()) {
289 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
290 IOP13XX_XBG_BECSR);
291 val = 0xffffffff;
292 }
293
294 *value = val;
295
296 return PCIBIOS_SUCCESSFUL;
297}
298
299static int
300iop13xx_atux_write_config(struct pci_bus *bus, unsigned int devfn, int where,
301 int size, u32 value)
302{
303 unsigned long addr = iop13xx_atux_cfg_address(bus, devfn, where);
304 u32 val;
305
306 if (size != 4) {
307 val = iop13xx_atux_read(addr);
308 if (!iop13xx_atux_pci_status(1) == 0)
309 return PCIBIOS_SUCCESSFUL;
310
311 where = (where & 3) * 8;
312
313 if (size == 1)
314 val &= ~(0xff << where);
315 else
316 val &= ~(0xffff << where);
317
318 __raw_writel(val | value << where, IOP13XX_ATUX_OCCDR);
319 } else {
320 __raw_writel(addr, IOP13XX_ATUX_OCCAR);
321 __raw_writel(value, IOP13XX_ATUX_OCCDR);
322 }
323
324 return PCIBIOS_SUCCESSFUL;
325}
326
327static struct pci_ops iop13xx_atux_ops = {
328 .read = iop13xx_atux_read_config,
329 .write = iop13xx_atux_write_config,
330};
331
332
333
334
335
336
337
338static int iop13xx_atue_pci_status(int clear)
339{
340 unsigned int status;
341 int err = 0;
342
343
344
345
346
347
348 status = __raw_readw(IOP13XX_ATUE_ATUSR);
349 if (status & IOP_PCI_STATUS_ERROR) {
350 PRINTK("\t\t\tPCI error: ATUSR %#08x", status);
351 if(clear)
352 __raw_writew(status & IOP_PCI_STATUS_ERROR,
353 IOP13XX_ATUE_ATUSR);
354 err++;
355 }
356
357
358 status = __raw_readl(IOP13XX_ATUE_ATUISR);
359 if (status & IOP13XX_ATUE_ATUISR_ERROR) {
360 PRINTK("\t\t\tPCI error: ATUISR %#08x", status);
361 if (clear)
362 __raw_writew(status & IOP13XX_ATUE_ATUISR_ERROR,
363 IOP13XX_ATUE_ATUISR);
364 err++;
365
366
367 if (status & IOP13XX_ATUE_STAT_PCI_IFACE_ERR) {
368
369 status = __raw_readl(IOP13XX_ATUE_PIE_STS) &
370 ~(__raw_readl(IOP13XX_ATUE_PIE_MSK));
371
372 if (status) {
373 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
374 __raw_readl(IOP13XX_ATUE_PIE_STS));
375 err++;
376 } else {
377 PRINTK("\t\t\tPCI-E error: ATUE_PIE_STS %#08x",
378 __raw_readl(IOP13XX_ATUE_PIE_STS));
379 PRINTK("\t\t\tPCI-E error: ATUE_PIE_MSK %#08x",
380 __raw_readl(IOP13XX_ATUE_PIE_MSK));
381 BUG();
382 }
383
384 if(clear)
385 __raw_writel(status, IOP13XX_ATUE_PIE_STS);
386 }
387 }
388
389 return err;
390}
391
392static int
393iop13xx_pcie_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
394{
395 WARN_ON(idsel != 0);
396
397 switch (pin) {
398 case 1: return ATUE_INTA;
399 case 2: return ATUE_INTB;
400 case 3: return ATUE_INTC;
401 case 4: return ATUE_INTD;
402 default: return -1;
403 }
404}
405
406static u32 iop13xx_atue_read(unsigned long addr)
407{
408 u32 val;
409
410 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
411 val = __raw_readl(IOP13XX_ATUE_OCCDR);
412
413 rmb();
414
415 return val;
416}
417
418
419
420
421static int
422iop13xx_atue_read_config(struct pci_bus *bus, unsigned int devfn, int where,
423 int size, u32 *value)
424{
425 u32 val;
426 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
427
428
429 if (!PCI_SLOT(devfn) || (addr & 1)) {
430 val = iop13xx_atue_read(addr) >> ((where & 3) * 8);
431 if( iop13xx_atue_pci_status(1) || is_atue_occdr_error() ) {
432 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3,
433 IOP13XX_XBG_BECSR);
434 val = 0xffffffff;
435 }
436
437 PRINTK("addr=%#0lx, val=%#010x", addr, val);
438 } else
439 val = 0xffffffff;
440
441 *value = val;
442
443 return PCIBIOS_SUCCESSFUL;
444}
445
446static int
447iop13xx_atue_write_config(struct pci_bus *bus, unsigned int devfn, int where,
448 int size, u32 value)
449{
450 unsigned long addr = iop13xx_atue_cfg_address(bus, devfn, where);
451 u32 val;
452
453 if (size != 4) {
454 val = iop13xx_atue_read(addr);
455 if (!iop13xx_atue_pci_status(1) == 0)
456 return PCIBIOS_SUCCESSFUL;
457
458 where = (where & 3) * 8;
459
460 if (size == 1)
461 val &= ~(0xff << where);
462 else
463 val &= ~(0xffff << where);
464
465 __raw_writel(val | value << where, IOP13XX_ATUE_OCCDR);
466 } else {
467 __raw_writel(addr, IOP13XX_ATUE_OCCAR);
468 __raw_writel(value, IOP13XX_ATUE_OCCDR);
469 }
470
471 return PCIBIOS_SUCCESSFUL;
472}
473
474static struct pci_ops iop13xx_atue_ops = {
475 .read = iop13xx_atue_read_config,
476 .write = iop13xx_atue_write_config,
477};
478
479
480
481
482
483
484
485int
486iop13xx_pci_abort(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
487{
488 PRINTK("Data abort: address = 0x%08lx "
489 "fsr = 0x%03x PC = 0x%08lx LR = 0x%08lx",
490 addr, fsr, regs->ARM_pc, regs->ARM_lr);
491
492 PRINTK("IOP13XX_XBG_BECSR: %#10x", __raw_readl(IOP13XX_XBG_BECSR));
493 PRINTK("IOP13XX_XBG_BERAR: %#10x", __raw_readl(IOP13XX_XBG_BERAR));
494 PRINTK("IOP13XX_XBG_BERUAR: %#10x", __raw_readl(IOP13XX_XBG_BERUAR));
495
496
497
498
499 if (fsr & (1 << 10))
500 regs->ARM_pc += 4;
501
502 if (is_atue_occdr_error() || is_atux_occdr_error())
503 return 0;
504 else
505 return 1;
506}
507
508
509
510struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *sys)
511{
512 int which_atu;
513 struct pci_bus *bus = NULL;
514
515 switch (init_atu) {
516 case IOP13XX_INIT_ATU_ATUX:
517 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
518 break;
519 case IOP13XX_INIT_ATU_ATUE:
520 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
521 break;
522 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
523 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
524 break;
525 default:
526 which_atu = 0;
527 }
528
529 if (!which_atu) {
530 BUG();
531 return NULL;
532 }
533
534 switch (which_atu) {
535 case IOP13XX_INIT_ATU_ATUX:
536 if (time_after_eq(jiffies + msecs_to_jiffies(1000),
537 atux_trhfa_timeout))
538 while(time_before(jiffies, atux_trhfa_timeout))
539 udelay(100);
540
541 bus = pci_bus_atux = pci_scan_bus(sys->busnr,
542 &iop13xx_atux_ops,
543 sys);
544 break;
545 case IOP13XX_INIT_ATU_ATUE:
546 bus = pci_bus_atue = pci_scan_bus(sys->busnr,
547 &iop13xx_atue_ops,
548 sys);
549 break;
550 }
551
552 return bus;
553}
554
555
556
557
558
559void __init iop13xx_atue_setup(void)
560{
561 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUE);
562 u32 reg_val;
563
564#ifdef CONFIG_PCI_MSI
565
566 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
567 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUE_IALR0);
568 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUE_IATVR0);
569 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUE_IABAR0);
570#endif
571
572
573
574 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
575 IOP13XX_ATUE_IALR1);
576 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
577
578
579 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
580 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUE_IABAR1);
581
582
583
584
585 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
586 __raw_writel(PHYS_OFFSET, IOP13XX_ATUE_IATVR1);
587
588
589
590 __raw_writel(0x0, IOP13XX_ATUE_OUMWTVR1);
591
592 __raw_writel(IOP13XX_ATUE_OUMBAR_ENABLE |
593 (IOP13XX_PCIE_MEM_PHYS_OFFSET >> 32),
594 IOP13XX_ATUE_OUMBAR1);
595
596
597
598
599 __raw_writel(((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000),
600 IOP13XX_ATUE_OIOBAR);
601 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
602
603
604 iop13xx_atue_pci_status(1);
605
606
607
608 reg_val = __raw_readl(IOP13XX_ATUE_OIOBAR);
609 reg_val &= ~0x7;
610 reg_val |= func;
611 __raw_writel(reg_val, IOP13XX_ATUE_OIOBAR);
612
613
614
615 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
616 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
617 IOP13XX_ATU_OUMBAR_FUNC_NUM);
618 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
619 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
620
621 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
622 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
623 IOP13XX_ATU_OUMBAR_FUNC_NUM);
624 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
625 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
626
627 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
628 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
629 IOP13XX_ATU_OUMBAR_FUNC_NUM);
630 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
631 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
632
633 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
634 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
635 IOP13XX_ATU_OUMBAR_FUNC_NUM);
636 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
637 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
638
639
640
641 reg_val = __raw_readw(IOP13XX_ATUE_ATUCMD);
642 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
643 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
644 __raw_writew(reg_val, IOP13XX_ATUE_ATUCMD);
645
646 reg_val = __raw_readl(IOP13XX_ATUE_ATUCR);
647 reg_val |= IOP13XX_ATUE_ATUCR_OUT_EN |
648 IOP13XX_ATUE_ATUCR_IVM;
649 __raw_writel(reg_val, IOP13XX_ATUE_ATUCR);
650}
651
652void __init iop13xx_atue_disable(void)
653{
654 u32 reg_val;
655
656 __raw_writew(0x0, IOP13XX_ATUE_ATUCMD);
657 __raw_writel(IOP13XX_ATUE_ATUCR_IVM, IOP13XX_ATUE_ATUCR);
658
659
660 while (__raw_readl(IOP13XX_ATUE_PCSR) & (IOP13XX_ATUE_PCSR_OUT_Q_BUSY |
661 IOP13XX_ATUE_PCSR_IN_Q_BUSY |
662 IOP13XX_ATUE_PCSR_LLRB_BUSY))
663 cpu_relax();
664
665
666 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR0);
667 __raw_writel(0x0, IOP13XX_ATUE_IABAR0);
668 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR0);
669 __raw_writel(0x0, IOP13XX_ATUE_IATVR0);
670 __raw_writel(0x0, IOP13XX_ATUE_IALR0);
671 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR0);
672 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
673 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR0);
674
675
676 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR1);
677 __raw_writel(0x0, IOP13XX_ATUE_IABAR1);
678 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR1);
679 __raw_writel(0x0, IOP13XX_ATUE_IATVR1);
680 __raw_writel(0x0, IOP13XX_ATUE_IALR1);
681 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR1);
682 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
683 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR1);
684
685
686 __raw_writel(0x0, IOP13XX_ATUE_IAUBAR2);
687 __raw_writel(0x0, IOP13XX_ATUE_IABAR2);
688 __raw_writel(0x0, IOP13XX_ATUE_IAUTVR2);
689 __raw_writel(0x0, IOP13XX_ATUE_IATVR2);
690 __raw_writel(0x0, IOP13XX_ATUE_IALR2);
691 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR2);
692 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
693 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR2);
694
695
696 reg_val = __raw_readl(IOP13XX_ATUE_OUMBAR3);
697 reg_val &= ~IOP13XX_ATUE_OUMBAR_ENABLE;
698 __raw_writel(reg_val, IOP13XX_ATUE_OUMBAR3);
699
700
701
702
703 __raw_writel((IOP13XX_PCIE_LOWER_IO_PA >> 0x4) & 0xfffff000,
704 IOP13XX_ATUE_OIOBAR);
705 __raw_writel(IOP13XX_PCIE_LOWER_IO_BA, IOP13XX_ATUE_OIOWTVR);
706}
707
708
709
710
711
712void __init iop13xx_atux_setup(void)
713{
714 u32 reg_val;
715 int func = iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX);
716
717
718
719
720
721
722 reg_val = __raw_readl(IOP13XX_ATUX_PCSR);
723 if (reg_val & IOP13XX_ATUX_PCSR_P_RSTOUT) {
724 int msec = (reg_val >> IOP13XX_ATUX_PCSR_FREQ_OFFSET) & 0x7;
725 msec = 1000 / (8-msec);
726 __raw_writel(reg_val & ~IOP13XX_ATUX_PCSR_P_RSTOUT,
727 IOP13XX_ATUX_PCSR);
728 atux_trhfa_timeout = jiffies + msecs_to_jiffies(msec);
729 }
730 else
731 atux_trhfa_timeout = jiffies;
732
733#ifdef CONFIG_PCI_MSI
734
735 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_MU_MUBAR);
736 __raw_writel(~(IOP13XX_MU_WINDOW_SIZE - 1), IOP13XX_ATUX_IALR0);
737 __raw_writel(IOP13XX_MU_BASE_PHYS, IOP13XX_ATUX_IATVR0);
738 __raw_writel(IOP13XX_MU_BASE_PCI, IOP13XX_ATUX_IABAR0);
739#endif
740
741
742
743 __raw_writel(~(IOP13XX_MAX_RAM_SIZE - PHYS_OFFSET - 1) & ~0x1,
744 IOP13XX_ATUX_IALR1);
745 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
746
747
748 __raw_writel(PHYS_OFFSET | PCI_BASE_ADDRESS_MEM_TYPE_64 |
749 PCI_BASE_ADDRESS_MEM_PREFETCH, IOP13XX_ATUX_IABAR1);
750
751
752
753
754 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
755 __raw_writel(PHYS_OFFSET, IOP13XX_ATUX_IATVR1);
756
757
758
759 __raw_writel(0x0, IOP13XX_ATUX_OUMWTVR1);
760
761 __raw_writel(IOP13XX_ATUX_OUMBAR_ENABLE |
762 IOP13XX_PCIX_MEM_PHYS_OFFSET >> 32,
763 IOP13XX_ATUX_OUMBAR1);
764
765
766
767
768 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
769 IOP13XX_ATUX_OIOBAR);
770 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
771
772
773 iop13xx_atux_pci_status(1);
774
775
776
777 reg_val = __raw_readl(IOP13XX_ATUX_OIOBAR);
778 reg_val &= ~0x7;
779 reg_val |= func;
780 __raw_writel(reg_val, IOP13XX_ATUX_OIOBAR);
781
782
783
784 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
785 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
786 IOP13XX_ATU_OUMBAR_FUNC_NUM);
787 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
788 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
789
790 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
791 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
792 IOP13XX_ATU_OUMBAR_FUNC_NUM);
793 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
794 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
795
796 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
797 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
798 IOP13XX_ATU_OUMBAR_FUNC_NUM);
799 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
800 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
801
802 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
803 reg_val &= ~(IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK <<
804 IOP13XX_ATU_OUMBAR_FUNC_NUM);
805 reg_val |= func << IOP13XX_ATU_OUMBAR_FUNC_NUM;
806 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
807
808
809
810 reg_val = __raw_readw(IOP13XX_ATUX_ATUCMD);
811 reg_val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
812 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
813 __raw_writew(reg_val, IOP13XX_ATUX_ATUCMD);
814
815 reg_val = __raw_readl(IOP13XX_ATUX_ATUCR);
816 reg_val |= IOP13XX_ATUX_ATUCR_OUT_EN;
817 __raw_writel(reg_val, IOP13XX_ATUX_ATUCR);
818}
819
820void __init iop13xx_atux_disable(void)
821{
822 u32 reg_val;
823
824 __raw_writew(0x0, IOP13XX_ATUX_ATUCMD);
825 __raw_writel(0x0, IOP13XX_ATUX_ATUCR);
826
827
828 while (__raw_readl(IOP13XX_ATUX_PCSR) & (IOP13XX_ATUX_PCSR_OUT_Q_BUSY |
829 IOP13XX_ATUX_PCSR_IN_Q_BUSY))
830 cpu_relax();
831
832
833 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR0);
834 __raw_writel(0x0, IOP13XX_ATUX_IABAR0);
835 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR0);
836 __raw_writel(0x0, IOP13XX_ATUX_IATVR0);
837 __raw_writel(0x0, IOP13XX_ATUX_IALR0);
838 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR0);
839 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
840 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR0);
841
842
843 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR1);
844 __raw_writel(0x0, IOP13XX_ATUX_IABAR1);
845 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR1);
846 __raw_writel(0x0, IOP13XX_ATUX_IATVR1);
847 __raw_writel(0x0, IOP13XX_ATUX_IALR1);
848 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR1);
849 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
850 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR1);
851
852
853 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR2);
854 __raw_writel(0x0, IOP13XX_ATUX_IABAR2);
855 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR2);
856 __raw_writel(0x0, IOP13XX_ATUX_IATVR2);
857 __raw_writel(0x0, IOP13XX_ATUX_IALR2);
858 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR2);
859 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
860 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR2);
861
862
863 __raw_writel(0x0, IOP13XX_ATUX_IAUBAR3);
864 __raw_writel(0x0, IOP13XX_ATUX_IABAR3);
865 __raw_writel(0x0, IOP13XX_ATUX_IAUTVR3);
866 __raw_writel(0x0, IOP13XX_ATUX_IATVR3);
867 __raw_writel(0x0, IOP13XX_ATUX_IALR3);
868 reg_val = __raw_readl(IOP13XX_ATUX_OUMBAR3);
869 reg_val &= ~IOP13XX_ATUX_OUMBAR_ENABLE;
870 __raw_writel(reg_val, IOP13XX_ATUX_OUMBAR3);
871
872
873
874
875 __raw_writel((IOP13XX_PCIX_LOWER_IO_PA >> 0x4) & 0xfffff000,
876 IOP13XX_ATUX_OIOBAR);
877 __raw_writel(IOP13XX_PCIX_LOWER_IO_BA, IOP13XX_ATUX_OIOWTVR);
878}
879
880void __init iop13xx_set_atu_mmr_bases(void)
881{
882
883 switch(__raw_readl(IOP13XX_ESSR0) &
884 (IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX)) {
885
886 case 0:
887 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
888 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
889 break;
890
891
892
893 case IOP13XX_CONTROLLER_ONLY:
894 iop13xx_atux_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
895 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
896 break;
897
898
899
900 case IOP13XX_INTERFACE_SEL_PCIX:
901 iop13xx_atux_pmmr_offset = IOP13XX_ATU1_PMMR_OFFSET;
902 iop13xx_atue_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
903 break;
904
905 case IOP13XX_CONTROLLER_ONLY | IOP13XX_INTERFACE_SEL_PCIX:
906 iop13xx_atux_pmmr_offset = IOP13XX_ATU2_PMMR_OFFSET;
907 iop13xx_atue_pmmr_offset = IOP13XX_ATU0_PMMR_OFFSET;
908 break;
909 default:
910 BUG();
911 }
912}
913
914void __init iop13xx_atu_select(struct hw_pci *plat_pci)
915{
916 int i;
917
918
919
920
921
922 if (init_atu == IOP13XX_INIT_ATU_DEFAULT) {
923
924 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX) {
925
926
927
928 init_atu |= IOP13XX_INIT_ATU_ATUE;
929 switch (__raw_readw(IOP13XX_ATUE_DID) & 0xf0) {
930 case 0x70:
931 case 0x80:
932 case 0xc0:
933 init_atu |= IOP13XX_INIT_ATU_ATUX;
934 break;
935 }
936 } else {
937
938
939
940 init_atu |= IOP13XX_INIT_ATU_ATUX;
941 switch (__raw_readw(IOP13XX_ATUX_DID) & 0xf0) {
942 case 0x70:
943 case 0x80:
944 case 0xc0:
945 init_atu |= IOP13XX_INIT_ATU_ATUE;
946 break;
947 }
948 }
949
950
951 if (init_atu & IOP13XX_INIT_ATU_ATUX)
952 if (!(__raw_readl(IOP13XX_ATUX_PCSR) &
953 IOP13XX_ATUX_PCSR_CENTRAL_RES))
954 init_atu &= ~IOP13XX_INIT_ATU_ATUX;
955
956 if (init_atu & IOP13XX_INIT_ATU_ATUE)
957 if (__raw_readl(IOP13XX_ATUE_PCSR) &
958 IOP13XX_ATUE_PCSR_END_POINT)
959 init_atu &= ~IOP13XX_INIT_ATU_ATUE;
960 }
961
962 for (i = 0; i < 2; i++) {
963 if((init_atu & (1 << i)) == (1 << i))
964 plat_pci->nr_controllers++;
965 }
966}
967
968void __init iop13xx_pci_init(void)
969{
970
971 __raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
972
973
974 iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
975
976
977
978
979
980 if (init_atu & IOP13XX_INIT_ATU_ATUE) {
981 iop13xx_atue_disable();
982 iop13xx_atue_setup();
983 }
984
985 if (init_atu & IOP13XX_INIT_ATU_ATUX) {
986 iop13xx_atux_disable();
987 iop13xx_atux_setup();
988 }
989
990 hook_fault_code(16+6, iop13xx_pci_abort, SIGBUS, 0,
991 "imprecise external abort");
992}
993
994
995
996
997int iop13xx_pci_setup(int nr, struct pci_sys_data *sys)
998{
999 struct resource *res;
1000 int which_atu;
1001 u32 pcixsr, pcsr;
1002
1003 if (nr > 1)
1004 return 0;
1005
1006 res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
1007 if (!res)
1008 panic("PCI: unable to alloc resources");
1009
1010
1011
1012
1013
1014
1015
1016 switch(init_atu) {
1017 case IOP13XX_INIT_ATU_ATUX:
1018 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUX;
1019 break;
1020 case IOP13XX_INIT_ATU_ATUE:
1021 which_atu = nr ? 0 : IOP13XX_INIT_ATU_ATUE;
1022 break;
1023 case (IOP13XX_INIT_ATU_ATUX | IOP13XX_INIT_ATU_ATUE):
1024 which_atu = nr ? IOP13XX_INIT_ATU_ATUE : IOP13XX_INIT_ATU_ATUX;
1025 break;
1026 default:
1027 which_atu = 0;
1028 }
1029
1030 if (!which_atu) {
1031 kfree(res);
1032 return 0;
1033 }
1034
1035 switch(which_atu) {
1036 case IOP13XX_INIT_ATU_ATUX:
1037 pcixsr = __raw_readl(IOP13XX_ATUX_PCIXSR);
1038 pcixsr &= ~0xffff;
1039 pcixsr |= sys->busnr << IOP13XX_ATUX_PCIXSR_BUS_NUM |
1040 0 << IOP13XX_ATUX_PCIXSR_DEV_NUM |
1041 iop13xx_atu_function(IOP13XX_INIT_ATU_ATUX)
1042 << IOP13XX_ATUX_PCIXSR_FUNC_NUM;
1043 __raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
1044
1045 res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
1046 res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
1047 res[0].name = "IQ81340 ATUX PCI I/O Space";
1048 res[0].flags = IORESOURCE_IO;
1049
1050 res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
1051 res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
1052 res[1].name = "IQ81340 ATUX PCI Memory Space";
1053 res[1].flags = IORESOURCE_MEM;
1054 sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
1055 sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
1056 break;
1057 case IOP13XX_INIT_ATU_ATUE:
1058
1059 pcsr = __raw_readl(IOP13XX_ATUE_PCSR);
1060 pcsr &= ~(0xfff8 << 16);
1061 pcsr |= sys->busnr << IOP13XX_ATUE_PCSR_BUS_NUM |
1062 0 << IOP13XX_ATUE_PCSR_DEV_NUM;
1063
1064 __raw_writel(pcsr, IOP13XX_ATUE_PCSR);
1065
1066 res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
1067 res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
1068 res[0].name = "IQ81340 ATUE PCI I/O Space";
1069 res[0].flags = IORESOURCE_IO;
1070
1071 res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
1072 res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
1073 res[1].name = "IQ81340 ATUE PCI Memory Space";
1074 res[1].flags = IORESOURCE_MEM;
1075 sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
1076 sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
1077 sys->map_irq = iop13xx_pcie_map_irq;
1078 break;
1079 default:
1080 kfree(res);
1081 return 0;
1082 }
1083
1084 request_resource(&ioport_resource, &res[0]);
1085 request_resource(&iomem_resource, &res[1]);
1086
1087 sys->resource[0] = &res[0];
1088 sys->resource[1] = &res[1];
1089 sys->resource[2] = NULL;
1090
1091 return 1;
1092}
1093
1094u16 iop13xx_dev_id(void)
1095{
1096 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
1097 return __raw_readw(IOP13XX_ATUE_DID);
1098 else
1099 return __raw_readw(IOP13XX_ATUX_DID);
1100}
1101
1102static int __init iop13xx_init_atu_setup(char *str)
1103{
1104 init_atu = IOP13XX_INIT_ATU_NONE;
1105 if (str) {
1106 while (*str != '\0') {
1107 switch (*str) {
1108 case 'x':
1109 case 'X':
1110 init_atu |= IOP13XX_INIT_ATU_ATUX;
1111 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1112 break;
1113 case 'e':
1114 case 'E':
1115 init_atu |= IOP13XX_INIT_ATU_ATUE;
1116 init_atu &= ~IOP13XX_INIT_ATU_NONE;
1117 break;
1118 case ',':
1119 case '=':
1120 break;
1121 default:
1122 PRINTK("\"iop13xx_init_atu\" malformed at "
1123 "character: \'%c\'", *str);
1124 *(str + 1) = '\0';
1125 init_atu = IOP13XX_INIT_ATU_DEFAULT;
1126 }
1127 str++;
1128 }
1129 }
1130 return 1;
1131}
1132
1133__setup("iop13xx_init_atu", iop13xx_init_atu_setup);
1134