1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 2 * 3 * This program is free software; you can redistribute it and/or modify 4 * it under the terms of the GNU General Public License version 2 and 5 * only version 2 as published by the Free Software Foundation. 6 * 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 * 12 * You should have received a copy of the GNU General Public License 13 * along with this program; if not, write to the Free Software 14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 15 * 02110-1301, USA. 16 */ 17 18#ifndef MSM_IOMMU_H 19#define MSM_IOMMU_H 20 21#include <linux/interrupt.h> 22 23/* Sharability attributes of MSM IOMMU mappings */ 24#define MSM_IOMMU_ATTR_NON_SH 0x0 25#define MSM_IOMMU_ATTR_SH 0x4 26 27/* Cacheability attributes of MSM IOMMU mappings */ 28#define MSM_IOMMU_ATTR_NONCACHED 0x0 29#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1 30#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2 31#define MSM_IOMMU_ATTR_CACHED_WT 0x3 32 33/* Mask for the cache policy attribute */ 34#define MSM_IOMMU_CP_MASK 0x03 35 36/* Maximum number of Machine IDs that we are allowing to be mapped to the same 37 * context bank. The number of MIDs mapped to the same CB does not affect 38 * performance, but there is a practical limit on how many distinct MIDs may 39 * be present. These mappings are typically determined at design time and are 40 * not expected to change at run time. 41 */ 42#define MAX_NUM_MIDS 32 43 44/** 45 * struct msm_iommu_dev - a single IOMMU hardware instance 46 * name Human-readable name given to this IOMMU HW instance 47 * clk_rate Rate to set for this IOMMU's clock, if applicable to this 48 * particular IOMMU. 0 means don't set a rate. 49 * -1 means it is an AXI clock with no valid rate 50 * 51 */ 52struct msm_iommu_dev { 53 const char *name; 54 int clk_rate; 55}; 56 57/** 58 * struct msm_iommu_ctx_dev - an IOMMU context bank instance 59 * name Human-readable name given to this context bank 60 * num Index of this context bank within the hardware 61 * mids List of Machine IDs that are to be mapped into this context 62 * bank, terminated by -1. The MID is a set of signals on the 63 * AXI bus that identifies the function associated with a specific 64 * memory request. (See ARM spec). 65 */ 66struct msm_iommu_ctx_dev { 67 const char *name; 68 int num; 69 int mids[MAX_NUM_MIDS]; 70}; 71 72 73/** 74 * struct msm_iommu_drvdata - A single IOMMU hardware instance 75 * @base: IOMMU config port base address (VA) 76 * @irq: Interrupt number 77 * 78 * A msm_iommu_drvdata holds the global driver data about a single piece 79 * of an IOMMU hardware instance. 80 */ 81struct msm_iommu_drvdata { 82 void __iomem *base; 83 int irq; 84}; 85 86/** 87 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance 88 * @num: Hardware context number of this context 89 * @pdev: Platform device associated wit this HW instance 90 * @attached_elm: List element for domains to track which devices are 91 * attached to them 92 * 93 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank 94 * within each IOMMU hardware instance 95 */ 96struct msm_iommu_ctx_drvdata { 97 int num; 98 struct platform_device *pdev; 99 struct list_head attached_elm; 100}; 101 102/* 103 * Look up an IOMMU context device by its context name. NULL if none found. 104 * Useful for testing and drivers that do not yet fully have IOMMU stuff in 105 * their platform devices. 106 */ 107struct device *msm_iommu_get_ctx(const char *ctx_name); 108 109/* 110 * Interrupt handler for the IOMMU context fault interrupt. Hooking the 111 * interrupt is not supported in the API yet, but this will print an error 112 * message and dump useful IOMMU registers. 113 */ 114irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id); 115 116#endif 117