1/* Copyright (c) 2009, Code Aurora Forum. All rights reserved. 2 * 3 * Redistribution and use in source and binary forms, with or without 4 * modification, are permitted provided that the following conditions are 5 * met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above 9 * copyright notice, this list of conditions and the following 10 * disclaimer in the documentation and/or other materials provided 11 * with the distribution. 12 * * Neither the name of Code Aurora Forum, Inc. nor the names of its 13 * contributors may be used to endorse or promote products derived 14 * from this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED 17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 */ 29 30#ifndef __ASM_ARCH_MSM_IRQS_7X30_H 31#define __ASM_ARCH_MSM_IRQS_7X30_H 32 33/* MSM ACPU Interrupt Numbers */ 34 35#define INT_DEBUG_TIMER_EXP 0 36#define INT_GPT0_TIMER_EXP 1 37#define INT_GPT1_TIMER_EXP 2 38#define INT_WDT0_ACCSCSSBARK 3 39#define INT_WDT1_ACCSCSSBARK 4 40#define INT_AVS_SVIC 5 41#define INT_AVS_SVIC_SW_DONE 6 42#define INT_SC_DBG_RX_FULL 7 43#define INT_SC_DBG_TX_EMPTY 8 44#define INT_ARM11_PM 9 45#define INT_AVS_REQ_DOWN 10 46#define INT_AVS_REQ_UP 11 47#define INT_SC_ACG 12 48/* SCSS_VICFIQSTS0[13:15] are RESERVED */ 49#define INT_L2_SVICCPUIRPTREQ 16 50#define INT_L2_SVICDMANSIRPTREQ 17 51#define INT_L2_SVICDMASIRPTREQ 18 52#define INT_L2_SVICSLVIRPTREQ 19 53#define INT_AD5A_MPROC_APPS_0 20 54#define INT_AD5A_MPROC_APPS_1 21 55#define INT_A9_M2A_0 22 56#define INT_A9_M2A_1 23 57#define INT_A9_M2A_2 24 58#define INT_A9_M2A_3 25 59#define INT_A9_M2A_4 26 60#define INT_A9_M2A_5 27 61#define INT_A9_M2A_6 28 62#define INT_A9_M2A_7 29 63#define INT_A9_M2A_8 30 64#define INT_A9_M2A_9 31 65 66#define INT_AXI_EBI1_SC (32 + 0) 67#define INT_IMEM_ERR (32 + 1) 68#define INT_AXI_EBI0_SC (32 + 2) 69#define INT_PBUS_SC_IRQC (32 + 3) 70#define INT_PERPH_BUS_BPM (32 + 4) 71#define INT_CC_TEMP_SENSE (32 + 5) 72#define INT_UXMC_EBI0 (32 + 6) 73#define INT_UXMC_EBI1 (32 + 7) 74#define INT_EBI2_OP_DONE (32 + 8) 75#define INT_EBI2_WR_ER_DONE (32 + 9) 76#define INT_TCSR_SPSS_CE (32 + 10) 77#define INT_EMDH (32 + 11) 78#define INT_PMDH (32 + 12) 79#define INT_MDC (32 + 13) 80#define INT_MIDI_TO_SUPSS (32 + 14) 81#define INT_LPA_2 (32 + 15) 82#define INT_GPIO_GROUP1_SECURE (32 + 16) 83#define INT_GPIO_GROUP2_SECURE (32 + 17) 84#define INT_GPIO_GROUP1 (32 + 18) 85#define INT_GPIO_GROUP2 (32 + 19) 86#define INT_MPRPH_SOFTRESET (32 + 20) 87#define INT_PWB_I2C (32 + 21) 88#define INT_PWB_I2C_2 (32 + 22) 89#define INT_TSSC_SAMPLE (32 + 23) 90#define INT_TSSC_PENUP (32 + 24) 91#define INT_TCHSCRN_SSBI (32 + 25) 92#define INT_FM_RDS (32 + 26) 93#define INT_KEYSENSE (32 + 27) 94#define INT_USB_OTG_HS (32 + 28) 95#define INT_USB_OTG_HS2 (32 + 29) 96#define INT_USB_OTG_HS3 (32 + 30) 97#define INT_CSI (32 + 31) 98 99#define INT_SPI_OUTPUT (64 + 0) 100#define INT_SPI_INPUT (64 + 1) 101#define INT_SPI_ERROR (64 + 2) 102#define INT_UART1 (64 + 3) 103#define INT_UART1_RX (64 + 4) 104#define INT_UART2 (64 + 5) 105#define INT_UART2_RX (64 + 6) 106#define INT_UART3 (64 + 7) 107#define INT_UART3_RX (64 + 8) 108#define INT_UART1DM_IRQ (64 + 9) 109#define INT_UART1DM_RX (64 + 10) 110#define INT_UART2DM_IRQ (64 + 11) 111#define INT_UART2DM_RX (64 + 12) 112#define INT_TSIF (64 + 13) 113#define INT_ADM_SC1 (64 + 14) 114#define INT_ADM_SC2 (64 + 15) 115#define INT_MDP (64 + 16) 116#define INT_VPE (64 + 17) 117#define INT_GRP_2D (64 + 18) 118#define INT_GRP_3D (64 + 19) 119#define INT_ROTATOR (64 + 20) 120#define INT_MFC720 (64 + 21) 121#define INT_JPEG (64 + 22) 122#define INT_VFE (64 + 23) 123#define INT_TV_ENC (64 + 24) 124#define INT_PMIC_SSBI (64 + 25) 125#define INT_MPM_1 (64 + 26) 126#define INT_TCSR_SPSS_SAMPLE (64 + 27) 127#define INT_TCSR_SPSS_PENUP (64 + 28) 128#define INT_MPM_2 (64 + 29) 129#define INT_SDC1_0 (64 + 30) 130#define INT_SDC1_1 (64 + 31) 131 132#define INT_SDC3_0 (96 + 0) 133#define INT_SDC3_1 (96 + 1) 134#define INT_SDC2_0 (96 + 2) 135#define INT_SDC2_1 (96 + 3) 136#define INT_SDC4_0 (96 + 4) 137#define INT_SDC4_1 (96 + 5) 138#define INT_PWB_QUP_IN (96 + 6) 139#define INT_PWB_QUP_OUT (96 + 7) 140#define INT_PWB_QUP_ERR (96 + 8) 141#define INT_SCSS_WDT0_BITE (96 + 9) 142/* SCSS_VICFIQSTS3[10:31] are RESERVED */ 143 144/* Retrofit universal macro names */ 145#define INT_ADM_AARM INT_ADM_SC2 146#define INT_USB_HS INT_USB_OTG_HS 147#define INT_USB_OTG INT_USB_OTG_HS 148#define INT_TCHSCRN1 INT_TSSC_SAMPLE 149#define INT_TCHSCRN2 INT_TSSC_PENUP 150#define INT_GP_TIMER_EXP INT_GPT0_TIMER_EXP 151#define INT_ADSP_A11 INT_AD5A_MPROC_APPS_0 152#define INT_ADSP_A9_A11 INT_AD5A_MPROC_APPS_1 153#define INT_MDDI_EXT INT_EMDH 154#define INT_MDDI_PRI INT_PMDH 155#define INT_MDDI_CLIENT INT_MDC 156#define INT_NAND_WR_ER_DONE INT_EBI2_WR_ER_DONE 157#define INT_NAND_OP_DONE INT_EBI2_OP_DONE 158 159#define NR_MSM_IRQS 128 160#define NR_GPIO_IRQS 182 161#define PMIC8058_IRQ_BASE (NR_MSM_IRQS + NR_GPIO_IRQS) 162#define NR_PMIC8058_GPIO_IRQS 40 163#define NR_PMIC8058_MPP_IRQS 12 164#define NR_PMIC8058_MISC_IRQS 8 165#define NR_PMIC8058_IRQS (NR_PMIC8058_GPIO_IRQS +\ 166 NR_PMIC8058_MPP_IRQS +\ 167 NR_PMIC8058_MISC_IRQS) 168#define NR_BOARD_IRQS NR_PMIC8058_IRQS 169 170#endif /* __ASM_ARCH_MSM_IRQS_7X30_H */ 171