1/* 2 * Copyright (C) 2007 Google, Inc. 3 * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved. 4 * Author: Brian Swetland <swetland@google.com> 5 * 6 * This software is licensed under the terms of the GNU General Public 7 * License version 2, as published by the Free Software Foundation, and 8 * may be copied, distributed, and modified under those terms. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * 16 * The MSM peripherals are spread all over across 768MB of physical 17 * space, which makes just having a simple IO_ADDRESS macro to slide 18 * them into the right virtual location rough. Instead, we will 19 * provide a master phys->virt mapping for peripherals here. 20 * 21 */ 22 23#ifndef __ASM_ARCH_MSM_IOMAP_8X50_H 24#define __ASM_ARCH_MSM_IOMAP_8X50_H 25 26/* Physical base address and size of peripherals. 27 * Ordered by the virtual base addresses they will be mapped at. 28 * 29 * MSM_VIC_BASE must be an value that can be loaded via a "mov" 30 * instruction, otherwise entry-macro.S will not compile. 31 * 32 * If you add or remove entries here, you'll want to edit the 33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your 34 * changes. 35 * 36 */ 37 38#define MSM_VIC_BASE IOMEM(0xE0000000) 39#define MSM_VIC_PHYS 0xAC000000 40#define MSM_VIC_SIZE SZ_4K 41 42#define MSM_CSR_BASE IOMEM(0xE0001000) 43#define MSM_CSR_PHYS 0xAC100000 44#define MSM_CSR_SIZE SZ_4K 45 46#define MSM_TMR_PHYS MSM_CSR_PHYS 47#define MSM_TMR_BASE MSM_CSR_BASE 48#define MSM_TMR_SIZE SZ_4K 49 50#define MSM_GPT_BASE MSM_TMR_BASE 51#define MSM_DGT_BASE (MSM_TMR_BASE + 0x10) 52 53#define MSM_DMOV_BASE IOMEM(0xE0002000) 54#define MSM_DMOV_PHYS 0xA9700000 55#define MSM_DMOV_SIZE SZ_4K 56 57#define MSM_GPIO1_BASE IOMEM(0xE0003000) 58#define MSM_GPIO1_PHYS 0xA9000000 59#define MSM_GPIO1_SIZE SZ_4K 60 61#define MSM_GPIO2_BASE IOMEM(0xE0004000) 62#define MSM_GPIO2_PHYS 0xA9100000 63#define MSM_GPIO2_SIZE SZ_4K 64 65#define MSM_CLK_CTL_BASE IOMEM(0xE0005000) 66#define MSM_CLK_CTL_PHYS 0xA8600000 67#define MSM_CLK_CTL_SIZE SZ_4K 68 69#define MSM_SIRC_BASE IOMEM(0xE1006000) 70#define MSM_SIRC_PHYS 0xAC200000 71#define MSM_SIRC_SIZE SZ_4K 72 73#define MSM_SCPLL_BASE IOMEM(0xE1007000) 74#define MSM_SCPLL_PHYS 0xA8800000 75#define MSM_SCPLL_SIZE SZ_4K 76 77#ifdef CONFIG_MSM_SOC_REV_A 78#define MSM_SMI_BASE 0xE0000000 79#else 80#define MSM_SMI_BASE 0x00000000 81#endif 82 83#define MSM_SHARED_RAM_BASE IOMEM(0xE0100000) 84#define MSM_SHARED_RAM_PHYS (MSM_SMI_BASE + 0x00100000) 85#define MSM_SHARED_RAM_SIZE SZ_1M 86 87#define MSM_UART1_PHYS 0xA9A00000 88#define MSM_UART1_SIZE SZ_4K 89 90#define MSM_UART2_PHYS 0xA9B00000 91#define MSM_UART2_SIZE SZ_4K 92 93#define MSM_UART3_PHYS 0xA9C00000 94#define MSM_UART3_SIZE SZ_4K 95 96#ifdef CONFIG_MSM_DEBUG_UART 97#define MSM_DEBUG_UART_BASE 0xE1000000 98#if CONFIG_MSM_DEBUG_UART == 1 99#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS 100#elif CONFIG_MSM_DEBUG_UART == 2 101#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS 102#elif CONFIG_MSM_DEBUG_UART == 3 103#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS 104#endif 105#define MSM_DEBUG_UART_SIZE SZ_4K 106#endif 107 108#define MSM_MDC_BASE IOMEM(0xE0200000) 109#define MSM_MDC_PHYS 0xAA500000 110#define MSM_MDC_SIZE SZ_1M 111 112#define MSM_AD5_BASE IOMEM(0xE0300000) 113#define MSM_AD5_PHYS 0xAC000000 114#define MSM_AD5_SIZE (SZ_1M*13) 115 116 117#define MSM_I2C_SIZE SZ_4K 118#define MSM_I2C_PHYS 0xA9900000 119 120#define MSM_HSUSB_PHYS 0xA0800000 121#define MSM_HSUSB_SIZE SZ_1K 122 123#define MSM_NAND_PHYS 0xA0A00000 124 125 126#define MSM_TSIF_PHYS (0xa0100000) 127#define MSM_TSIF_SIZE (0x200) 128 129#define MSM_TSSC_PHYS 0xAA300000 130 131#define MSM_UART1DM_PHYS 0xA0200000 132#define MSM_UART2DM_PHYS 0xA0900000 133 134 135#define MSM_SDC1_PHYS 0xA0400000 136#define MSM_SDC1_SIZE SZ_4K 137 138#define MSM_SDC2_PHYS 0xA0500000 139#define MSM_SDC2_SIZE SZ_4K 140 141#define MSM_SDC3_PHYS 0xA0600000 142#define MSM_SDC3_SIZE SZ_4K 143 144#define MSM_SDC4_PHYS 0xA0700000 145#define MSM_SDC4_SIZE SZ_4K 146 147#endif 148