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16#ifndef _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
17#define _ARCH_ARM_MACH_MSM_MSM_SMD_PRIVATE_H_
18
19#include <linux/platform_device.h>
20#include <linux/spinlock.h>
21#include <linux/list.h>
22#include <linux/io.h>
23
24#include <mach/msm_iomap.h>
25
26struct smem_heap_info {
27 unsigned initialized;
28 unsigned free_offset;
29 unsigned heap_remaining;
30 unsigned reserved;
31};
32
33struct smem_heap_entry {
34 unsigned allocated;
35 unsigned offset;
36 unsigned size;
37 unsigned reserved;
38};
39
40struct smem_proc_comm {
41 unsigned command;
42 unsigned status;
43 unsigned data1;
44 unsigned data2;
45};
46
47#define PC_APPS 0
48#define PC_MODEM 1
49
50#define VERSION_SMD 0
51#define VERSION_QDSP6 4
52#define VERSION_APPS_SBL 6
53#define VERSION_MODEM_SBL 7
54#define VERSION_APPS 8
55#define VERSION_MODEM 9
56
57struct smem_shared {
58 struct smem_proc_comm proc_comm[4];
59 unsigned version[32];
60 struct smem_heap_info heap_info;
61 struct smem_heap_entry heap_toc[512];
62};
63
64#define SMSM_V1_SIZE (sizeof(unsigned) * 8)
65#define SMSM_V2_SIZE (sizeof(unsigned) * 4)
66
67#ifdef CONFIG_MSM_SMD_PKG3
68struct smsm_interrupt_info {
69 uint32_t interrupt_mask;
70 uint32_t pending_interrupts;
71 uint32_t wakeup_reason;
72};
73#else
74#define DEM_MAX_PORT_NAME_LEN (20)
75struct msm_dem_slave_data {
76 uint32_t sleep_time;
77 uint32_t interrupt_mask;
78 uint32_t resources_used;
79 uint32_t reserved1;
80
81 uint32_t wakeup_reason;
82 uint32_t pending_interrupts;
83 uint32_t rpc_prog;
84 uint32_t rpc_proc;
85 char smd_port_name[DEM_MAX_PORT_NAME_LEN];
86 uint32_t reserved2;
87};
88#endif
89
90#define SZ_DIAG_ERR_MSG 0xC8
91#define ID_DIAG_ERR_MSG SMEM_DIAG_ERR_MESSAGE
92#define ID_SMD_CHANNELS SMEM_SMD_BASE_ID
93#define ID_SHARED_STATE SMEM_SMSM_SHARED_STATE
94#define ID_CH_ALLOC_TBL SMEM_CHANNEL_ALLOC_TBL
95
96#define SMSM_INIT 0x00000001
97#define SMSM_SMDINIT 0x00000008
98#define SMSM_RPCINIT 0x00000020
99#define SMSM_RESET 0x00000040
100#define SMSM_RSA 0x00000080
101#define SMSM_RUN 0x00000100
102#define SMSM_PWRC 0x00000200
103#define SMSM_TIMEWAIT 0x00000400
104#define SMSM_TIMEINIT 0x00000800
105#define SMSM_PWRC_EARLY_EXIT 0x00001000
106#define SMSM_WFPI 0x00002000
107#define SMSM_SLEEP 0x00004000
108#define SMSM_SLEEPEXIT 0x00008000
109#define SMSM_APPS_REBOOT 0x00020000
110#define SMSM_SYSTEM_POWER_DOWN 0x00040000
111#define SMSM_SYSTEM_REBOOT 0x00080000
112#define SMSM_SYSTEM_DOWNLOAD 0x00100000
113#define SMSM_PWRC_SUSPEND 0x00200000
114#define SMSM_APPS_SHUTDOWN 0x00400000
115#define SMSM_SMD_LOOPBACK 0x00800000
116#define SMSM_RUN_QUIET 0x01000000
117#define SMSM_MODEM_WAIT 0x02000000
118#define SMSM_MODEM_BREAK 0x04000000
119#define SMSM_MODEM_CONTINUE 0x08000000
120#define SMSM_UNKNOWN 0x80000000
121
122#define SMSM_WKUP_REASON_RPC 0x00000001
123#define SMSM_WKUP_REASON_INT 0x00000002
124#define SMSM_WKUP_REASON_GPIO 0x00000004
125#define SMSM_WKUP_REASON_TIMER 0x00000008
126#define SMSM_WKUP_REASON_ALARM 0x00000010
127#define SMSM_WKUP_REASON_RESET 0x00000020
128
129#ifdef CONFIG_ARCH_MSM7X00A
130enum smsm_state_item {
131 SMSM_STATE_APPS = 1,
132 SMSM_STATE_MODEM = 3,
133 SMSM_STATE_COUNT,
134};
135#else
136enum smsm_state_item {
137 SMSM_STATE_APPS,
138 SMSM_STATE_MODEM,
139 SMSM_STATE_HEXAGON,
140 SMSM_STATE_APPS_DEM,
141 SMSM_STATE_MODEM_DEM,
142 SMSM_STATE_QDSP6_DEM,
143 SMSM_STATE_POWER_MASTER_DEM,
144 SMSM_STATE_TIME_MASTER_DEM,
145 SMSM_STATE_COUNT,
146};
147#endif
148
149void *smem_alloc(unsigned id, unsigned size);
150int smsm_change_state(enum smsm_state_item item, uint32_t clear_mask, uint32_t set_mask);
151uint32_t smsm_get_state(enum smsm_state_item item);
152int smsm_set_sleep_duration(uint32_t delay);
153void smsm_print_sleep_info(void);
154
155#define SMEM_NUM_SMD_CHANNELS 64
156
157typedef enum {
158
159 SMEM_PROC_COMM = 0,
160 SMEM_HEAP_INFO,
161 SMEM_ALLOCATION_TABLE,
162 SMEM_VERSION_INFO,
163 SMEM_HW_RESET_DETECT,
164 SMEM_AARM_WARM_BOOT,
165 SMEM_DIAG_ERR_MESSAGE,
166 SMEM_SPINLOCK_ARRAY,
167 SMEM_MEMORY_BARRIER_LOCATION,
168
169
170 SMEM_AARM_PARTITION_TABLE,
171 SMEM_AARM_BAD_BLOCK_TABLE,
172 SMEM_RESERVE_BAD_BLOCKS,
173 SMEM_WM_UUID,
174 SMEM_CHANNEL_ALLOC_TBL,
175 SMEM_SMD_BASE_ID,
176 SMEM_SMEM_LOG_IDX = SMEM_SMD_BASE_ID + SMEM_NUM_SMD_CHANNELS,
177 SMEM_SMEM_LOG_EVENTS,
178 SMEM_SMEM_STATIC_LOG_IDX,
179 SMEM_SMEM_STATIC_LOG_EVENTS,
180 SMEM_SMEM_SLOW_CLOCK_SYNC,
181 SMEM_SMEM_SLOW_CLOCK_VALUE,
182 SMEM_BIO_LED_BUF,
183 SMEM_SMSM_SHARED_STATE,
184 SMEM_SMSM_INT_INFO,
185 SMEM_SMSM_SLEEP_DELAY,
186 SMEM_SMSM_LIMIT_SLEEP,
187 SMEM_SLEEP_POWER_COLLAPSE_DISABLED,
188 SMEM_KEYPAD_KEYS_PRESSED,
189 SMEM_KEYPAD_STATE_UPDATED,
190 SMEM_KEYPAD_STATE_IDX,
191 SMEM_GPIO_INT,
192 SMEM_MDDI_LCD_IDX,
193 SMEM_MDDI_HOST_DRIVER_STATE,
194 SMEM_MDDI_LCD_DISP_STATE,
195 SMEM_LCD_CUR_PANEL,
196 SMEM_MARM_BOOT_SEGMENT_INFO,
197 SMEM_AARM_BOOT_SEGMENT_INFO,
198 SMEM_SLEEP_STATIC,
199 SMEM_SCORPION_FREQUENCY,
200 SMEM_SMD_PROFILES,
201 SMEM_TSSC_BUSY,
202 SMEM_HS_SUSPEND_FILTER_INFO,
203 SMEM_BATT_INFO,
204 SMEM_APPS_BOOT_MODE,
205 SMEM_VERSION_FIRST,
206 SMEM_VERSION_LAST = SMEM_VERSION_FIRST + 24,
207 SMEM_OSS_RRCASN1_BUF1,
208 SMEM_OSS_RRCASN1_BUF2,
209 SMEM_ID_VENDOR0,
210 SMEM_ID_VENDOR1,
211 SMEM_ID_VENDOR2,
212 SMEM_HW_SW_BUILD_ID,
213 SMEM_SMD_BLOCK_PORT_BASE_ID,
214 SMEM_SMD_BLOCK_PORT_PROC0_HEAP = SMEM_SMD_BLOCK_PORT_BASE_ID + SMEM_NUM_SMD_CHANNELS,
215 SMEM_SMD_BLOCK_PORT_PROC1_HEAP = SMEM_SMD_BLOCK_PORT_PROC0_HEAP + SMEM_NUM_SMD_CHANNELS,
216 SMEM_I2C_MUTEX = SMEM_SMD_BLOCK_PORT_PROC1_HEAP + SMEM_NUM_SMD_CHANNELS,
217 SMEM_SCLK_CONVERSION,
218 SMEM_SMD_SMSM_INTR_MUX,
219 SMEM_SMSM_CPU_INTR_MASK,
220 SMEM_APPS_DEM_SLAVE_DATA,
221 SMEM_QDSP6_DEM_SLAVE_DATA,
222 SMEM_CLKREGIM_BSP,
223 SMEM_CLKREGIM_SOURCES,
224 SMEM_SMD_FIFO_BASE_ID,
225 SMEM_USABLE_RAM_PARTITION_TABLE = SMEM_SMD_FIFO_BASE_ID + SMEM_NUM_SMD_CHANNELS,
226 SMEM_POWER_ON_STATUS_INFO,
227 SMEM_DAL_AREA,
228 SMEM_SMEM_LOG_POWER_IDX,
229 SMEM_SMEM_LOG_POWER_WRAP,
230 SMEM_SMEM_LOG_POWER_EVENTS,
231 SMEM_ERR_CRASH_LOG,
232 SMEM_ERR_F3_TRACE_LOG,
233 SMEM_NUM_ITEMS,
234} smem_mem_type;
235
236
237#define SMD_SS_CLOSED 0x00000000
238#define SMD_SS_OPENING 0x00000001
239#define SMD_SS_OPENED 0x00000002
240#define SMD_SS_FLUSHING 0x00000003
241#define SMD_SS_CLOSING 0x00000004
242#define SMD_SS_RESET 0x00000005
243#define SMD_SS_RESET_OPENING 0x00000006
244
245#define SMD_BUF_SIZE 8192
246#define SMD_CHANNELS 64
247
248#define SMD_HEADER_SIZE 20
249
250struct smd_alloc_elm {
251 char name[20];
252 uint32_t cid;
253 uint32_t ctype;
254 uint32_t ref_count;
255};
256
257struct smd_half_channel {
258 unsigned state;
259 unsigned char fDSR;
260 unsigned char fCTS;
261 unsigned char fCD;
262 unsigned char fRI;
263 unsigned char fHEAD;
264 unsigned char fTAIL;
265 unsigned char fSTATE;
266 unsigned char fUNUSED;
267 unsigned tail;
268 unsigned head;
269} __attribute__(( aligned(4), packed ));
270
271
272struct smd_shared_v1 {
273 struct smd_half_channel ch0;
274 unsigned char data0[SMD_BUF_SIZE];
275 struct smd_half_channel ch1;
276 unsigned char data1[SMD_BUF_SIZE];
277};
278
279
280struct smd_shared_v2 {
281 struct smd_half_channel ch0;
282 struct smd_half_channel ch1;
283};
284
285struct smd_channel {
286 volatile struct smd_half_channel *send;
287 volatile struct smd_half_channel *recv;
288 unsigned char *send_data;
289 unsigned char *recv_data;
290
291 unsigned fifo_mask;
292 unsigned fifo_size;
293 unsigned current_packet;
294 unsigned n;
295
296 struct list_head ch_list;
297
298 void *priv;
299 void (*notify)(void *priv, unsigned flags);
300
301 int (*read)(struct smd_channel *ch, void *data, int len);
302 int (*write)(struct smd_channel *ch, const void *data, int len);
303 int (*read_avail)(struct smd_channel *ch);
304 int (*write_avail)(struct smd_channel *ch);
305
306 void (*update_state)(struct smd_channel *ch);
307 unsigned last_state;
308 void (*notify_other_cpu)(void);
309 unsigned type;
310
311 char name[32];
312 struct platform_device pdev;
313};
314
315#define SMD_TYPE_MASK 0x0FF
316#define SMD_TYPE_APPS_MODEM 0x000
317#define SMD_TYPE_APPS_DSP 0x001
318#define SMD_TYPE_MODEM_DSP 0x002
319
320#define SMD_KIND_MASK 0xF00
321#define SMD_KIND_UNKNOWN 0x000
322#define SMD_KIND_STREAM 0x100
323#define SMD_KIND_PACKET 0x200
324
325extern struct list_head smd_ch_closed_list;
326extern struct list_head smd_ch_list_modem;
327extern struct list_head smd_ch_list_dsp;
328
329extern spinlock_t smd_lock;
330extern spinlock_t smem_lock;
331
332void *smem_find(unsigned id, unsigned size);
333void *smem_item(unsigned id, unsigned *size);
334uint32_t raw_smsm_get_state(enum smsm_state_item item);
335
336extern void msm_init_last_radio_log(struct module *);
337
338#ifdef CONFIG_MSM_SMD_PKG3
339
340
341
342
343static inline int _smd_alloc_channel(struct smd_channel *ch)
344{
345 struct smd_shared_v1 *shared1;
346
347 shared1 = smem_alloc(ID_SMD_CHANNELS + ch->n, sizeof(*shared1));
348 if (!shared1) {
349 pr_err("smd_alloc_channel() cid %d does not exist\n", ch->n);
350 return -1;
351 }
352 ch->send = &shared1->ch0;
353 ch->recv = &shared1->ch1;
354 ch->send_data = shared1->data0;
355 ch->recv_data = shared1->data1;
356 ch->fifo_size = SMD_BUF_SIZE;
357 return 0;
358}
359#else
360
361
362
363
364static inline int _smd_alloc_channel(struct smd_channel *ch)
365{
366 struct smd_shared_v2 *shared2;
367 void *buffer;
368 unsigned buffer_sz;
369
370 shared2 = smem_alloc(SMEM_SMD_BASE_ID + ch->n, sizeof(*shared2));
371 buffer = smem_item(SMEM_SMD_FIFO_BASE_ID + ch->n, &buffer_sz);
372
373 if (!buffer)
374 return -1;
375
376
377 if (buffer_sz & (buffer_sz - 1))
378 return -1;
379
380 buffer_sz /= 2;
381 ch->send = &shared2->ch0;
382 ch->recv = &shared2->ch1;
383 ch->send_data = buffer;
384 ch->recv_data = buffer + buffer_sz;
385 ch->fifo_size = buffer_sz;
386 return 0;
387}
388#endif
389
390#if defined(CONFIG_ARCH_MSM7X30)
391static inline void msm_a2m_int(uint32_t irq)
392{
393 writel(1 << irq, MSM_GCC_BASE + 0x8);
394}
395#else
396static inline void msm_a2m_int(uint32_t irq)
397{
398 writel(1, MSM_CSR_BASE + 0x400 + (irq * 4));
399}
400#endif
401
402
403#endif
404
