1/* 2 * arch/arm/mach-netx/include/mach/netx-regs.h 3 * 4 * Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 8 * as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20#ifndef __ASM_ARCH_NETX_REGS_H 21#define __ASM_ARCH_NETX_REGS_H 22 23/* offsets relative to the beginning of the io space */ 24#define NETX_OFS_SYSTEM 0x00000 25#define NETX_OFS_MEMCR 0x00100 26#define NETX_OFS_DPMAS 0x03000 27#define NETX_OFS_GPIO 0x00800 28#define NETX_OFS_PIO 0x00900 29#define NETX_OFS_UART0 0x00a00 30#define NETX_OFS_UART1 0x00a40 31#define NETX_OFS_UART2 0x00a80 32#define NETX_OF_MIIMU 0x00b00 33#define NETX_OFS_SPI 0x00c00 34#define NETX_OFS_I2C 0x00d00 35#define NETX_OFS_SYSTIME 0x01100 36#define NETX_OFS_RTC 0x01200 37#define NETX_OFS_EXTBUS 0x03600 38#define NETX_OFS_LCD 0x04000 39#define NETX_OFS_USB 0x20000 40#define NETX_OFS_XMAC0 0x60000 41#define NETX_OFS_XMAC1 0x61000 42#define NETX_OFS_XMAC2 0x62000 43#define NETX_OFS_XMAC3 0x63000 44#define NETX_OFS_XMAC(no) (0x60000 + (no) * 0x1000) 45#define NETX_OFS_PFIFO 0x64000 46#define NETX_OFS_XPEC0 0x70000 47#define NETX_OFS_XPEC1 0x74000 48#define NETX_OFS_XPEC2 0x78000 49#define NETX_OFS_XPEC3 0x7c000 50#define NETX_OFS_XPEC(no) (0x70000 + (no) * 0x4000) 51#define NETX_OFS_VIC 0xff000 52 53/* physical addresses */ 54#define NETX_PA_SYSTEM (NETX_IO_PHYS + NETX_OFS_SYSTEM) 55#define NETX_PA_MEMCR (NETX_IO_PHYS + NETX_OFS_MEMCR) 56#define NETX_PA_DPMAS (NETX_IO_PHYS + NETX_OFS_DPMAS) 57#define NETX_PA_GPIO (NETX_IO_PHYS + NETX_OFS_GPIO) 58#define NETX_PA_PIO (NETX_IO_PHYS + NETX_OFS_PIO) 59#define NETX_PA_UART0 (NETX_IO_PHYS + NETX_OFS_UART0) 60#define NETX_PA_UART1 (NETX_IO_PHYS + NETX_OFS_UART1) 61#define NETX_PA_UART2 (NETX_IO_PHYS + NETX_OFS_UART2) 62#define NETX_PA_MIIMU (NETX_IO_PHYS + NETX_OF_MIIMU) 63#define NETX_PA_SPI (NETX_IO_PHYS + NETX_OFS_SPI) 64#define NETX_PA_I2C (NETX_IO_PHYS + NETX_OFS_I2C) 65#define NETX_PA_SYSTIME (NETX_IO_PHYS + NETX_OFS_SYSTIME) 66#define NETX_PA_RTC (NETX_IO_PHYS + NETX_OFS_RTC) 67#define NETX_PA_EXTBUS (NETX_IO_PHYS + NETX_OFS_EXTBUS) 68#define NETX_PA_LCD (NETX_IO_PHYS + NETX_OFS_LCD) 69#define NETX_PA_USB (NETX_IO_PHYS + NETX_OFS_USB) 70#define NETX_PA_XMAC0 (NETX_IO_PHYS + NETX_OFS_XMAC0) 71#define NETX_PA_XMAC1 (NETX_IO_PHYS + NETX_OFS_XMAC1) 72#define NETX_PA_XMAC2 (NETX_IO_PHYS + NETX_OFS_XMAC2) 73#define NETX_PA_XMAC3 (NETX_IO_PHYS + NETX_OFS_XMAC3) 74#define NETX_PA_XMAC(no) (NETX_IO_PHYS + NETX_OFS_XMAC(no)) 75#define NETX_PA_PFIFO (NETX_IO_PHYS + NETX_OFS_PFIFO) 76#define NETX_PA_XPEC0 (NETX_IO_PHYS + NETX_OFS_XPEC0) 77#define NETX_PA_XPEC1 (NETX_IO_PHYS + NETX_OFS_XPEC1) 78#define NETX_PA_XPEC2 (NETX_IO_PHYS + NETX_OFS_XPEC2) 79#define NETX_PA_XPEC3 (NETX_IO_PHYS + NETX_OFS_XPEC3) 80#define NETX_PA_XPEC(no) (NETX_IO_PHYS + NETX_OFS_XPEC(no)) 81#define NETX_PA_VIC (NETX_IO_PHYS + NETX_OFS_VIC) 82 83/* virtual addresses */ 84#define NETX_VA_SYSTEM (NETX_IO_VIRT + NETX_OFS_SYSTEM) 85#define NETX_VA_MEMCR (NETX_IO_VIRT + NETX_OFS_MEMCR) 86#define NETX_VA_DPMAS (NETX_IO_VIRT + NETX_OFS_DPMAS) 87#define NETX_VA_GPIO (NETX_IO_VIRT + NETX_OFS_GPIO) 88#define NETX_VA_PIO (NETX_IO_VIRT + NETX_OFS_PIO) 89#define NETX_VA_UART0 (NETX_IO_VIRT + NETX_OFS_UART0) 90#define NETX_VA_UART1 (NETX_IO_VIRT + NETX_OFS_UART1) 91#define NETX_VA_UART2 (NETX_IO_VIRT + NETX_OFS_UART2) 92#define NETX_VA_MIIMU (NETX_IO_VIRT + NETX_OF_MIIMU) 93#define NETX_VA_SPI (NETX_IO_VIRT + NETX_OFS_SPI) 94#define NETX_VA_I2C (NETX_IO_VIRT + NETX_OFS_I2C) 95#define NETX_VA_SYSTIME (NETX_IO_VIRT + NETX_OFS_SYSTIME) 96#define NETX_VA_RTC (NETX_IO_VIRT + NETX_OFS_RTC) 97#define NETX_VA_EXTBUS (NETX_IO_VIRT + NETX_OFS_EXTBUS) 98#define NETX_VA_LCD (NETX_IO_VIRT + NETX_OFS_LCD) 99#define NETX_VA_USB (NETX_IO_VIRT + NETX_OFS_USB) 100#define NETX_VA_XMAC0 (NETX_IO_VIRT + NETX_OFS_XMAC0) 101#define NETX_VA_XMAC1 (NETX_IO_VIRT + NETX_OFS_XMAC1) 102#define NETX_VA_XMAC2 (NETX_IO_VIRT + NETX_OFS_XMAC2) 103#define NETX_VA_XMAC3 (NETX_IO_VIRT + NETX_OFS_XMAC3) 104#define NETX_VA_XMAC(no) (NETX_IO_VIRT + NETX_OFS_XMAC(no)) 105#define NETX_VA_PFIFO (NETX_IO_VIRT + NETX_OFS_PFIFO) 106#define NETX_VA_XPEC0 (NETX_IO_VIRT + NETX_OFS_XPEC0) 107#define NETX_VA_XPEC1 (NETX_IO_VIRT + NETX_OFS_XPEC1) 108#define NETX_VA_XPEC2 (NETX_IO_VIRT + NETX_OFS_XPEC2) 109#define NETX_VA_XPEC3 (NETX_IO_VIRT + NETX_OFS_XPEC3) 110#define NETX_VA_XPEC(no) (NETX_IO_VIRT + NETX_OFS_XPEC(no)) 111#define NETX_VA_VIC (NETX_IO_VIRT + NETX_OFS_VIC) 112 113/********************************* 114 * System functions * 115 *********************************/ 116 117/* Registers */ 118#define NETX_SYSTEM_REG(ofs) __io(NETX_VA_SYSTEM + (ofs)) 119#define NETX_SYSTEM_BOO_SR NETX_SYSTEM_REG(0x00) 120#define NETX_SYSTEM_IOC_CR NETX_SYSTEM_REG(0x04) 121#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08) 122 123/* FIXME: Docs are not consistent */ 124/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */ 125#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c) 126 127#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10) 128#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34) 129#define NETX_SYSTEM_IOC_ACCESS_KEY NETX_SYSTEM_REG(0x70) 130#define NETX_SYSTEM_WDG_TR NETX_SYSTEM_REG(0x200) 131#define NETX_SYSTEM_WDG_CTR NETX_SYSTEM_REG(0x204) 132#define NETX_SYSTEM_WDG_IRQ_TIMEOUT NETX_SYSTEM_REG(0x208) 133#define NETX_SYSTEM_WDG_RES_TIMEOUT NETX_SYSTEM_REG(0x20c) 134 135/* Bits */ 136#define NETX_SYSTEM_RES_CR_RSTIN (1<<0) 137#define NETX_SYSTEM_RES_CR_WDG_RES (1<<1) 138#define NETX_SYSTEM_RES_CR_HOST_RES (1<<2) 139#define NETX_SYSTEM_RES_CR_FIRMW_RES (1<<3) 140#define NETX_SYSTEM_RES_CR_XPEC0_RES (1<<4) 141#define NETX_SYSTEM_RES_CR_XPEC1_RES (1<<5) 142#define NETX_SYSTEM_RES_CR_XPEC2_RES (1<<6) 143#define NETX_SYSTEM_RES_CR_XPEC3_RES (1<<7) 144#define NETX_SYSTEM_RES_CR_DIS_XPEC0_RES (1<<16) 145#define NETX_SYSTEM_RES_CR_DIS_XPEC1_RES (1<<17) 146#define NETX_SYSTEM_RES_CR_DIS_XPEC2_RES (1<<18) 147#define NETX_SYSTEM_RES_CR_DIS_XPEC3_RES (1<<19) 148#define NETX_SYSTEM_RES_CR_FIRMW_FLG0 (1<<20) 149#define NETX_SYSTEM_RES_CR_FIRMW_FLG1 (1<<21) 150#define NETX_SYSTEM_RES_CR_FIRMW_FLG2 (1<<22) 151#define NETX_SYSTEM_RES_CR_FIRMW_FLG3 (1<<23) 152#define NETX_SYSTEM_RES_CR_FIRMW_RES_EN (1<<24) 153#define NETX_SYSTEM_RES_CR_RSTOUT (1<<25) 154#define NETX_SYSTEM_RES_CR_EN_RSTOUT (1<<26) 155 156#define PHY_CONTROL_RESET (1<<31) 157#define PHY_CONTROL_SIM_BYP (1<<30) 158#define PHY_CONTROL_CLK_XLATIN (1<<29) 159#define PHY_CONTROL_PHY1_EN (1<<21) 160#define PHY_CONTROL_PHY1_NP_MSG_CODE 161#define PHY_CONTROL_PHY1_AUTOMDIX (1<<17) 162#define PHY_CONTROL_PHY1_FIXMODE (1<<16) 163#define PHY_CONTROL_PHY1_MODE(mode) (((mode) & 0x7) << 13) 164#define PHY_CONTROL_PHY0_EN (1<<12) 165#define PHY_CONTROL_PHY0_NP_MSG_CODE 166#define PHY_CONTROL_PHY0_AUTOMDIX (1<<8) 167#define PHY_CONTROL_PHY0_FIXMODE (1<<7) 168#define PHY_CONTROL_PHY0_MODE(mode) (((mode) & 0x7) << 4) 169#define PHY_CONTROL_PHY_ADDRESS(adr) ((adr) & 0xf) 170 171#define PHY_MODE_10BASE_T_HALF 0 172#define PHY_MODE_10BASE_T_FULL 1 173#define PHY_MODE_100BASE_TX_FX_FULL 2 174#define PHY_MODE_100BASE_TX_FX_HALF 3 175#define PHY_MODE_100BASE_TX_HALF 4 176#define PHY_MODE_REPEATER 5 177#define PHY_MODE_POWER_DOWN 6 178#define PHY_MODE_ALL 7 179 180/* Bits */ 181#define VECT_CNTL_ENABLE (1 << 5) 182 183/******************************* 184 * GPIO and timer module * 185 *******************************/ 186 187/* Registers */ 188#define NETX_GPIO_REG(ofs) __io(NETX_VA_GPIO + (ofs)) 189#define NETX_GPIO_CFG(gpio) NETX_GPIO_REG(0x0 + ((gpio)<<2)) 190#define NETX_GPIO_THRESHOLD_CAPTURE(gpio) NETX_GPIO_REG(0x40 + ((gpio)<<2)) 191#define NETX_GPIO_COUNTER_CTRL(counter) NETX_GPIO_REG(0x80 + ((counter)<<2)) 192#define NETX_GPIO_COUNTER_MAX(counter) NETX_GPIO_REG(0x94 + ((counter)<<2)) 193#define NETX_GPIO_COUNTER_CURRENT(counter) NETX_GPIO_REG(0xa8 + ((counter)<<2)) 194#define NETX_GPIO_IRQ_ENABLE NETX_GPIO_REG(0xbc) 195#define NETX_GPIO_IRQ_DISABLE NETX_GPIO_REG(0xc0) 196#define NETX_GPIO_SYSTIME_NS_CMP NETX_GPIO_REG(0xc4) 197#define NETX_GPIO_LINE NETX_GPIO_REG(0xc8) 198#define NETX_GPIO_IRQ NETX_GPIO_REG(0xd0) 199 200/* Bits */ 201#define NETX_GPIO_CFG_IOCFG_GP_INPUT (0x0) 202#define NETX_GPIO_CFG_IOCFG_GP_OUTPUT (0x1) 203#define NETX_GPIO_CFG_IOCFG_GP_UART (0x2) 204#define NETX_GPIO_CFG_INV (1<<2) 205#define NETX_GPIO_CFG_MODE_INPUT_READ (0<<3) 206#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_CONT_RISING (1<<3) 207#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_ONCE_RISING (2<<3) 208#define NETX_GPIO_CFG_MODE_INPUT_CAPTURE_HIGH_LEVEL (3<<3) 209#define NETX_GPIO_CFG_COUNT_REF_COUNTER0 (0<<5) 210#define NETX_GPIO_CFG_COUNT_REF_COUNTER1 (1<<5) 211#define NETX_GPIO_CFG_COUNT_REF_COUNTER2 (2<<5) 212#define NETX_GPIO_CFG_COUNT_REF_COUNTER3 (3<<5) 213#define NETX_GPIO_CFG_COUNT_REF_COUNTER4 (4<<5) 214#define NETX_GPIO_CFG_COUNT_REF_SYSTIME (7<<5) 215 216#define NETX_GPIO_COUNTER_CTRL_RUN (1<<0) 217#define NETX_GPIO_COUNTER_CTRL_SYM (1<<1) 218#define NETX_GPIO_COUNTER_CTRL_ONCE (1<<2) 219#define NETX_GPIO_COUNTER_CTRL_IRQ_EN (1<<3) 220#define NETX_GPIO_COUNTER_CTRL_CNT_EVENT (1<<4) 221#define NETX_GPIO_COUNTER_CTRL_RST_EN (1<<5) 222#define NETX_GPIO_COUNTER_CTRL_SEL_EVENT (1<<6) 223#define NETX_GPIO_COUNTER_CTRL_GPIO_REF /* FIXME */ 224 225#define GPIO_BIT(gpio) (1<<(gpio)) 226#define COUNTER_BIT(counter) ((1<<16)<<(counter)) 227 228/******************************* 229 * PIO * 230 *******************************/ 231 232/* Registers */ 233#define NETX_PIO_REG(ofs) __io(NETX_VA_PIO + (ofs)) 234#define NETX_PIO_INPIO NETX_PIO_REG(0x0) 235#define NETX_PIO_OUTPIO NETX_PIO_REG(0x4) 236#define NETX_PIO_OEPIO NETX_PIO_REG(0x8) 237 238/******************************* 239 * MII Unit * 240 *******************************/ 241 242/* Registers */ 243#define NETX_MIIMU __io(NETX_VA_MIIMU) 244 245/* Bits */ 246#define MIIMU_SNRDY (1<<0) 247#define MIIMU_PREAMBLE (1<<1) 248#define MIIMU_OPMODE_WRITE (1<<2) 249#define MIIMU_MDC_PERIOD (1<<3) 250#define MIIMU_PHY_NRES (1<<4) 251#define MIIMU_RTA (1<<5) 252#define MIIMU_REGADDR(adr) (((adr) & 0x1f) << 6) 253#define MIIMU_PHYADDR(adr) (((adr) & 0x1f) << 11) 254#define MIIMU_DATA(data) (((data) & 0xffff) << 16) 255 256/******************************* 257 * xmac / xpec * 258 *******************************/ 259 260/* XPEC register offsets relative to NETX_VA_XPEC(no) */ 261#define NETX_XPEC_R0_OFS 0x00 262#define NETX_XPEC_R1_OFS 0x04 263#define NETX_XPEC_R2_OFS 0x08 264#define NETX_XPEC_R3_OFS 0x0c 265#define NETX_XPEC_R4_OFS 0x10 266#define NETX_XPEC_R5_OFS 0x14 267#define NETX_XPEC_R6_OFS 0x18 268#define NETX_XPEC_R7_OFS 0x1c 269#define NETX_XPEC_RANGE01_OFS 0x20 270#define NETX_XPEC_RANGE23_OFS 0x24 271#define NETX_XPEC_RANGE45_OFS 0x28 272#define NETX_XPEC_RANGE67_OFS 0x2c 273#define NETX_XPEC_PC_OFS 0x48 274#define NETX_XPEC_TIMER_OFS(timer) (0x30 + ((timer)<<2)) 275#define NETX_XPEC_IRQ_OFS 0x8c 276#define NETX_XPEC_SYSTIME_NS_OFS 0x90 277#define NETX_XPEC_FIFO_DATA_OFS 0x94 278#define NETX_XPEC_SYSTIME_S_OFS 0x98 279#define NETX_XPEC_ADC_OFS 0x9c 280#define NETX_XPEC_URX_COUNT_OFS 0x40 281#define NETX_XPEC_UTX_COUNT_OFS 0x44 282#define NETX_XPEC_PC_OFS 0x48 283#define NETX_XPEC_ZERO_OFS 0x4c 284#define NETX_XPEC_STATCFG_OFS 0x50 285#define NETX_XPEC_EC_MASKA_OFS 0x54 286#define NETX_XPEC_EC_MASKB_OFS 0x58 287#define NETX_XPEC_EC_MASK0_OFS 0x5c 288#define NETX_XPEC_EC_MASK8_OFS 0x7c 289#define NETX_XPEC_EC_MASK9_OFS 0x80 290#define NETX_XPEC_XPU_HOLD_PC_OFS 0x100 291#define NETX_XPEC_RAM_START_OFS 0x2000 292 293/* Bits */ 294#define XPU_HOLD_PC (1<<0) 295 296/* XMAC register offsets relative to NETX_VA_XMAC(no) */ 297#define NETX_XMAC_RPU_PROGRAM_START_OFS 0x000 298#define NETX_XMAC_RPU_PROGRAM_END_OFS 0x3ff 299#define NETX_XMAC_TPU_PROGRAM_START_OFS 0x400 300#define NETX_XMAC_TPU_PROGRAM_END_OFS 0x7ff 301#define NETX_XMAC_RPU_HOLD_PC_OFS 0xa00 302#define NETX_XMAC_TPU_HOLD_PC_OFS 0xa04 303#define NETX_XMAC_STATUS_SHARED0_OFS 0x840 304#define NETX_XMAC_CONFIG_SHARED0_OFS 0x844 305#define NETX_XMAC_STATUS_SHARED1_OFS 0x848 306#define NETX_XMAC_CONFIG_SHARED1_OFS 0x84c 307#define NETX_XMAC_STATUS_SHARED2_OFS 0x850 308#define NETX_XMAC_CONFIG_SHARED2_OFS 0x854 309#define NETX_XMAC_STATUS_SHARED3_OFS 0x858 310#define NETX_XMAC_CONFIG_SHARED3_OFS 0x85c 311 312#define RPU_HOLD_PC (1<<15) 313#define TPU_HOLD_PC (1<<15) 314 315/******************************* 316 * Pointer FIFO * 317 *******************************/ 318 319/* Registers */ 320#define NETX_PFIFO_REG(ofs) __io(NETX_VA_PFIFO + (ofs)) 321#define NETX_PFIFO_BASE(pfifo) NETX_PFIFO_REG(0x00 + ((pfifo)<<2)) 322#define NETX_PFIFO_BORDER_BASE(pfifo) NETX_PFIFO_REG(0x80 + ((pfifo)<<2)) 323#define NETX_PFIFO_RESET NETX_PFIFO_REG(0x100) 324#define NETX_PFIFO_FULL NETX_PFIFO_REG(0x104) 325#define NETX_PFIFO_EMPTY NETX_PFIFO_REG(0x108) 326#define NETX_PFIFO_OVEFLOW NETX_PFIFO_REG(0x10c) 327#define NETX_PFIFO_UNDERRUN NETX_PFIFO_REG(0x110) 328#define NETX_PFIFO_FILL_LEVEL(pfifo) NETX_PFIFO_REG(0x180 + ((pfifo)<<2)) 329#define NETX_PFIFO_XPEC_ISR(xpec) NETX_PFIFO_REG(0x400 + ((xpec) << 2)) 330 331 332/******************************* 333 * Memory Controller * 334 *******************************/ 335 336/* Registers */ 337#define NETX_MEMCR_REG(ofs) __io(NETX_VA_MEMCR + (ofs)) 338#define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */ 339#define NETX_MEMCR_SDRAM_CFG_CTRL NETX_MEMCR_REG(0x40) 340#define NETX_MEMCR_SDRAM_TIMING_CTRL NETX_MEMCR_REG(0x44) 341#define NETX_MEMCR_SDRAM_MODE NETX_MEMCR_REG(0x48) 342#define NETX_MEMCR_SDRAM_EXT_MODE NETX_MEMCR_REG(0x4c) 343#define NETX_MEMCR_PRIO_TIMESLOT_CTRL NETX_MEMCR_REG(0x80) 344#define NETX_MEMCR_PRIO_ACCESS_CTRL NETX_MEMCR_REG(0x84) 345 346/* Bits */ 347#define NETX_MEMCR_SRAM_CTRL_WIDTHEXTMEM(x) (((x) & 0x3) << 24) 348#define NETX_MEMCR_SRAM_CTRL_WSPOSTPAUSEEXTMEM(x) (((x) & 0x3) << 16) 349#define NETX_MEMCR_SRAM_CTRL_WSPREPASEEXTMEM(x) (((x) & 0x3) << 8) 350#define NETX_MEMCR_SRAM_CTRL_WSEXTMEM(x) (((x) & 0x1f) << 0) 351 352 353/******************************* 354 * Dual Port Memory * 355 *******************************/ 356 357/* Registers */ 358#define NETX_DPMAS_REG(ofs) __io(NETX_VA_DPMAS + (ofs)) 359#define NETX_DPMAS_SYS_STAT NETX_DPMAS_REG(0x4d8) 360#define NETX_DPMAS_INT_STAT NETX_DPMAS_REG(0x4e0) 361#define NETX_DPMAS_INT_EN NETX_DPMAS_REG(0x4f0) 362#define NETX_DPMAS_IF_CONF0 NETX_DPMAS_REG(0x608) 363#define NETX_DPMAS_IF_CONF1 NETX_DPMAS_REG(0x60c) 364#define NETX_DPMAS_EXT_CONFIG(cs) NETX_DPMAS_REG(0x610 + 4 * (cs)) 365#define NETX_DPMAS_IO_MODE0 NETX_DPMAS_REG(0x620) /* I/O 32..63 */ 366#define NETX_DPMAS_DRV_EN0 NETX_DPMAS_REG(0x624) 367#define NETX_DPMAS_DATA0 NETX_DPMAS_REG(0x628) 368#define NETX_DPMAS_IO_MODE1 NETX_DPMAS_REG(0x630) /* I/O 64..84 */ 369#define NETX_DPMAS_DRV_EN1 NETX_DPMAS_REG(0x634) 370#define NETX_DPMAS_DATA1 NETX_DPMAS_REG(0x638) 371 372/* Bits */ 373#define NETX_DPMAS_INT_EN_GLB_EN (1<<31) 374#define NETX_DPMAS_INT_EN_MEM_LCK (1<<30) 375#define NETX_DPMAS_INT_EN_WDG (1<<29) 376#define NETX_DPMAS_INT_EN_PIO72 (1<<28) 377#define NETX_DPMAS_INT_EN_PIO47 (1<<27) 378#define NETX_DPMAS_INT_EN_PIO40 (1<<26) 379#define NETX_DPMAS_INT_EN_PIO36 (1<<25) 380#define NETX_DPMAS_INT_EN_PIO35 (1<<24) 381 382#define NETX_DPMAS_IF_CONF0_HIF_DISABLED (0<<28) 383#define NETX_DPMAS_IF_CONF0_HIF_EXT_BUS (1<<28) 384#define NETX_DPMAS_IF_CONF0_HIF_UP_8BIT (2<<28) 385#define NETX_DPMAS_IF_CONF0_HIF_UP_16BIT (3<<28) 386#define NETX_DPMAS_IF_CONF0_HIF_IO (4<<28) 387#define NETX_DPMAS_IF_CONF0_WAIT_DRV_PP (1<<14) 388#define NETX_DPMAS_IF_CONF0_WAIT_DRV_OD (2<<14) 389#define NETX_DPMAS_IF_CONF0_WAIT_DRV_TRI (3<<14) 390 391#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO35 (1<<26) 392#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO36 (1<<27) 393#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO40 (1<<28) 394#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO47 (1<<29) 395#define NETX_DPMAS_IF_CONF1_IRQ_POL_PIO72 (1<<30) 396 397#define NETX_EXT_CONFIG_TALEWIDTH(x) (((x) & 0x7) << 29) 398#define NETX_EXT_CONFIG_TADRHOLD(x) (((x) & 0x7) << 26) 399#define NETX_EXT_CONFIG_TCSON(x) (((x) & 0x7) << 23) 400#define NETX_EXT_CONFIG_TRDON(x) (((x) & 0x7) << 20) 401#define NETX_EXT_CONFIG_TWRON(x) (((x) & 0x7) << 17) 402#define NETX_EXT_CONFIG_TWROFF(x) (((x) & 0x1f) << 12) 403#define NETX_EXT_CONFIG_TRDWRCYC(x) (((x) & 0x1f) << 7) 404#define NETX_EXT_CONFIG_WAIT_POL (1<<6) 405#define NETX_EXT_CONFIG_WAIT_EN (1<<5) 406#define NETX_EXT_CONFIG_NRD_MODE (1<<4) 407#define NETX_EXT_CONFIG_DS_MODE (1<<3) 408#define NETX_EXT_CONFIG_NWR_MODE (1<<2) 409#define NETX_EXT_CONFIG_16BIT (1<<1) 410#define NETX_EXT_CONFIG_CS_ENABLE (1<<0) 411 412#define NETX_DPMAS_IO_MODE0_WRL (1<<13) 413#define NETX_DPMAS_IO_MODE0_WAIT (1<<14) 414#define NETX_DPMAS_IO_MODE0_READY (1<<15) 415#define NETX_DPMAS_IO_MODE0_CS0 (1<<19) 416#define NETX_DPMAS_IO_MODE0_EXTRD (1<<20) 417 418#define NETX_DPMAS_IO_MODE1_CS2 (1<<15) 419#define NETX_DPMAS_IO_MODE1_CS1 (1<<16) 420#define NETX_DPMAS_IO_MODE1_SAMPLE_NPOR (0<<30) 421#define NETX_DPMAS_IO_MODE1_SAMPLE_100MHZ (1<<30) 422#define NETX_DPMAS_IO_MODE1_SAMPLE_NPIO36 (2<<30) 423#define NETX_DPMAS_IO_MODE1_SAMPLE_PIO36 (3<<30) 424 425/******************************* 426 * I2C * 427 *******************************/ 428#define NETX_I2C_REG(ofs) __io(NETX_VA_I2C, (ofs)) 429#define NETX_I2C_CTRL NETX_I2C_REG(0x0) 430#define NETX_I2C_DATA NETX_I2C_REG(0x4) 431 432#endif /* __ASM_ARCH_NETX_REGS_H */ 433