LXR linux/arch/arm/mach-orion5x/pci.c

   1/*
   2 * arch/arm/mach-orion5x/pci.c
   3 *
   4 * PCI and PCIe functions for Marvell Orion System On Chip
   5 *
   6 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7 *
   8 * This file is licensed under the terms of the GNU General Public
   9 * License version 2.  This program is licensed "as is" without any
  10 * warranty of any kind, whether express or implied.
  11 */
  12
  13#include <linux/kernel.h>
  14#include <linux/pci.h>
  15#include <linux/slab.h>
  16#include <linux/mbus.h>
  17#include <asm/irq.h>
  18#include <asm/mach/pci.h>
  19#include <plat/pcie.h>
  20#include "common.h"
  21
  22/*****************************************************************************
  23 * Orion has one PCIe controller and one PCI controller.
  24 *
  25 * Note1: The local PCIe bus number is '0'. The local PCI bus number
  26 * follows the scanned PCIe bridged busses, if any.
  27 *
  28 * Note2: It is possible for PCI/PCIe agents to access many subsystem's
  29 * space, by configuring BARs and Address Decode Windows, e.g. flashes on
  30 * device bus, Orion registers, etc. However this code only enable the
  31 * access to DDR banks.
  32 ****************************************************************************/
  33
  34
  35/*****************************************************************************
  36 * PCIe controller
  37 ****************************************************************************/
  38#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
  39
  40void __init orion5x_pcie_id(u32 *dev, u32 *rev)
  41{
  42        *dev = orion_pcie_dev_id(PCIE_BASE);
  43        *rev = orion_pcie_rev(PCIE_BASE);
  44}
  45
  46static int pcie_valid_config(int bus, int dev)
  47{
  48        /*
  49         * Don't go out when trying to access --
  50         * 1. nonexisting device on local bus
  51         * 2. where there's no device connected (no link)
  52         */
  53        if (bus == 0 && dev == 0)
  54                return 1;
  55
  56        if (!orion_pcie_link_up(PCIE_BASE))
  57                return 0;
  58
  59        if (bus == 0 && dev != 1)
  60                return 0;
  61
  62        return 1;
  63}
  64
  65
  66/*
  67 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
  68 * and then reading the PCIE_CONF_DATA register. Need to make sure these
  69 * transactions are atomic.
  70 */
  71static DEFINE_SPINLOCK(orion5x_pcie_lock);
  72
  73static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
  74                        int size, u32 *val)
  75{
  76        unsigned long flags;
  77        int ret;
  78
  79        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  80                *val = 0xffffffff;
  81                return PCIBIOS_DEVICE_NOT_FOUND;
  82        }
  83
  84        spin_lock_irqsave(&orion5x_pcie_lock, flags);
  85        ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
  86        spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
  87
  88        return ret;
  89}
  90
  91static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
  92                           int where, int size, u32 *val)
  93{
  94        int ret;
  95
  96        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
  97                *val = 0xffffffff;
  98                return PCIBIOS_DEVICE_NOT_FOUND;
  99        }
 100
 101        /*
 102         * We only support access to the non-extended configuration
 103         * space when using the WA access method (or we would have to
 104         * sacrifice 256M of CPU virtual address space.)
 105         */
 106        if (where >= 0x100) {
 107                *val = 0xffffffff;
 108                return PCIBIOS_DEVICE_NOT_FOUND;
 109        }
 110
 111        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
 112                                    bus, devfn, where, size, val);
 113
 114        return ret;
 115}
 116
 117static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 118                        int where, int size, u32 val)
 119{
 120        unsigned long flags;
 121        int ret;
 122
 123        if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
 124                return PCIBIOS_DEVICE_NOT_FOUND;
 125
 126        spin_lock_irqsave(&orion5x_pcie_lock, flags);
 127        ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
 128        spin_unlock_irqrestore(&orion5x_pcie_lock, flags);
 129
 130        return ret;
 131}
 132
 133static struct pci_ops pcie_ops = {
 134        .read = pcie_rd_conf,
 135        .write = pcie_wr_conf,
 136};
 137
 138
 139static int __init pcie_setup(struct pci_sys_data *sys)
 140{
 141        struct resource *res;
 142        int dev;
 143
 144        /*
 145         * Generic PCIe unit setup.
 146         */
 147        orion_pcie_setup(PCIE_BASE, &orion5x_mbus_dram_info);
 148
 149        /*
 150         * Check whether to apply Orion-1/Orion-NAS PCIe config
 151         * read transaction workaround.
 152         */
 153        dev = orion_pcie_dev_id(PCIE_BASE);
 154        if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
 155                printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
 156                                   "read transaction workaround\n");
 157                orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
 158                                          ORION5X_PCIE_WA_SIZE);
 159                pcie_ops.read = pcie_rd_conf_wa;
 160        }
 161
 162        /*
 163         * Request resources.
 164         */
 165        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 166        if (!res)
 167                panic("pcie_setup unable to alloc resources");
 168
 169        /*
 170         * IORESOURCE_IO
 171         */
 172        res[0].name = "PCIe I/O Space";
 173        res[0].flags = IORESOURCE_IO;
 174        res[0].start = ORION5X_PCIE_IO_BUS_BASE;
 175        res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
 176        if (request_resource(&ioport_resource, &res[0]))
 177                panic("Request PCIe IO resource failed\n");
 178        sys->resource[0] = &res[0];
 179
 180        /*
 181         * IORESOURCE_MEM
 182         */
 183        res[1].name = "PCIe Memory Space";
 184        res[1].flags = IORESOURCE_MEM;
 185        res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
 186        res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
 187        if (request_resource(&iomem_resource, &res[1]))
 188                panic("Request PCIe Memory resource failed\n");
 189        sys->resource[1] = &res[1];
 190
 191        sys->resource[2] = NULL;
 192        sys->io_offset = 0;
 193
 194        return 1;
 195}
 196
 197/*****************************************************************************
 198 * PCI controller
 199 ****************************************************************************/
 200#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE | (x))
 201#define PCI_MODE                ORION5X_PCI_REG(0xd00)
 202#define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 203#define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
 204#define PCI_CONF_ADDR           ORION5X_PCI_REG(0xc78)
 205#define PCI_CONF_DATA           ORION5X_PCI_REG(0xc7c)
 206
 207/*
 208 * PCI_MODE bits
 209 */
 210#define PCI_MODE_64BIT                  (1 << 2)
 211#define PCI_MODE_PCIX                   ((1 << 4) | (1 << 5))
 212
 213/*
 214 * PCI_CMD bits
 215 */
 216#define PCI_CMD_HOST_REORDER            (1 << 29)
 217
 218/*
 219 * PCI_P2P_CONF bits
 220 */
 221#define PCI_P2P_BUS_OFFS                16
 222#define PCI_P2P_BUS_MASK                (0xff << PCI_P2P_BUS_OFFS)
 223#define PCI_P2P_DEV_OFFS                24
 224#define PCI_P2P_DEV_MASK                (0x1f << PCI_P2P_DEV_OFFS)
 225
 226/*
 227 * PCI_CONF_ADDR bits
 228 */
 229#define PCI_CONF_REG(reg)               ((reg) & 0xfc)
 230#define PCI_CONF_FUNC(func)             (((func) & 0x3) << 8)
 231#define PCI_CONF_DEV(dev)               (((dev) & 0x1f) << 11)
 232#define PCI_CONF_BUS(bus)               (((bus) & 0xff) << 16)
 233#define PCI_CONF_ADDR_EN                (1 << 31)
 234
 235/*
 236 * Internal configuration space
 237 */
 238#define PCI_CONF_FUNC_STAT_CMD          0
 239#define PCI_CONF_REG_STAT_CMD           4
 240#define PCIX_STAT                       0x64
 241#define PCIX_STAT_BUS_OFFS              8
 242#define PCIX_STAT_BUS_MASK              (0xff << PCIX_STAT_BUS_OFFS)
 243
 244/*
 245 * PCI Address Decode Windows registers
 246 */
 247#define PCI_BAR_SIZE_DDR_CS(n)  (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
 248                                 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
 249                                 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
 250                                 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
 251#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
 252                                 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
 253                                 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
 254                                 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
 255#define PCI_BAR_ENABLE          ORION5X_PCI_REG(0xc3c)
 256#define PCI_ADDR_DECODE_CTRL    ORION5X_PCI_REG(0xd3c)
 257
 258/*
 259 * PCI configuration helpers for BAR settings
 260 */
 261#define PCI_CONF_FUNC_BAR_CS(n)         ((n) >> 1)
 262#define PCI_CONF_REG_BAR_LO_CS(n)       (((n) & 1) ? 0x18 : 0x10)
 263#define PCI_CONF_REG_BAR_HI_CS(n)       (((n) & 1) ? 0x1c : 0x14)
 264
 265/*
 266 * PCI config cycles are done by programming the PCI_CONF_ADDR register
 267 * and then reading the PCI_CONF_DATA register. Need to make sure these
 268 * transactions are atomic.
 269 */
 270static DEFINE_SPINLOCK(orion5x_pci_lock);
 271
 272static int orion5x_pci_cardbus_mode;
 273
 274static int orion5x_pci_local_bus_nr(void)
 275{
 276        u32 conf = readl(PCI_P2P_CONF);
 277        return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 278}
 279
 280static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
 281                                        u32 where, u32 size, u32 *val)
 282{
 283        unsigned long flags;
 284        spin_lock_irqsave(&orion5x_pci_lock, flags);
 285
 286        writel(PCI_CONF_BUS(bus) |
 287                PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
 288                PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 289
 290        *val = readl(PCI_CONF_DATA);
 291
 292        if (size == 1)
 293                *val = (*val >> (8*(where & 0x3))) & 0xff;
 294        else if (size == 2)
 295                *val = (*val >> (8*(where & 0x3))) & 0xffff;
 296
 297        spin_unlock_irqrestore(&orion5x_pci_lock, flags);
 298
 299        return PCIBIOS_SUCCESSFUL;
 300}
 301
 302static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
 303                                        u32 where, u32 size, u32 val)
 304{
 305        unsigned long flags;
 306        int ret = PCIBIOS_SUCCESSFUL;
 307
 308        spin_lock_irqsave(&orion5x_pci_lock, flags);
 309
 310        writel(PCI_CONF_BUS(bus) |
 311                PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
 312                PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
 313
 314        if (size == 4) {
 315                __raw_writel(val, PCI_CONF_DATA);
 316        } else if (size == 2) {
 317                __raw_writew(val, PCI_CONF_DATA + (where & 0x3));
 318        } else if (size == 1) {
 319                __raw_writeb(val, PCI_CONF_DATA + (where & 0x3));
 320        } else {
 321                ret = PCIBIOS_BAD_REGISTER_NUMBER;
 322        }
 323
 324        spin_unlock_irqrestore(&orion5x_pci_lock, flags);
 325
 326        return ret;
 327}
 328
 329static int orion5x_pci_valid_config(int bus, u32 devfn)
 330{
 331        if (bus == orion5x_pci_local_bus_nr()) {
 332                /*
 333                 * Don't go out for local device
 334                 */
 335                if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
 336                        return 0;
 337
 338                /*
 339                 * When the PCI signals are directly connected to a
 340                 * Cardbus slot, ignore all but device IDs 0 and 1.
 341                 */
 342                if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
 343                        return 0;
 344        }
 345
 346        return 1;
 347}
 348
 349static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
 350                                int where, int size, u32 *val)
 351{
 352        if (!orion5x_pci_valid_config(bus->number, devfn)) {
 353                *val = 0xffffffff;
 354                return PCIBIOS_DEVICE_NOT_FOUND;
 355        }
 356
 357        return orion5x_pci_hw_rd_conf(bus->number, PCI_SLOT(devfn),
 358                                        PCI_FUNC(devfn), where, size, val);
 359}
 360
 361static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
 362                                int where, int size, u32 val)
 363{
 364        if (!orion5x_pci_valid_config(bus->number, devfn))
 365                return PCIBIOS_DEVICE_NOT_FOUND;
 366
 367        return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
 368                                        PCI_FUNC(devfn), where, size, val);
 369}
 370
 371static struct pci_ops pci_ops = {
 372        .read = orion5x_pci_rd_conf,
 373        .write = orion5x_pci_wr_conf,
 374};
 375
 376static void __init orion5x_pci_set_bus_nr(int nr)
 377{
 378        u32 p2p = readl(PCI_P2P_CONF);
 379
 380        if (readl(PCI_MODE) & PCI_MODE_PCIX) {
 381                /*
 382                 * PCI-X mode
 383                 */
 384                u32 pcix_status, bus, dev;
 385                bus = (p2p & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS;
 386                dev = (p2p & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS;
 387                orion5x_pci_hw_rd_conf(bus, dev, 0, PCIX_STAT, 4, &pcix_status);
 388                pcix_status &= ~PCIX_STAT_BUS_MASK;
 389                pcix_status |= (nr << PCIX_STAT_BUS_OFFS);
 390                orion5x_pci_hw_wr_conf(bus, dev, 0, PCIX_STAT, 4, pcix_status);
 391        } else {
 392                /*
 393                 * PCI Conventional mode
 394                 */
 395                p2p &= ~PCI_P2P_BUS_MASK;
 396                p2p |= (nr << PCI_P2P_BUS_OFFS);
 397                writel(p2p, PCI_P2P_CONF);
 398        }
 399}
 400
 401static void __init orion5x_pci_master_slave_enable(void)
 402{
 403        int bus_nr, func, reg;
 404        u32 val;
 405
 406        bus_nr = orion5x_pci_local_bus_nr();
 407        func = PCI_CONF_FUNC_STAT_CMD;
 408        reg = PCI_CONF_REG_STAT_CMD;
 409        orion5x_pci_hw_rd_conf(bus_nr, 0, func, reg, 4, &val);
 410        val |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 411        orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 412}
 413
 414static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
 415{
 416        u32 win_enable;
 417        int bus;
 418        int i;
 419
 420        /*
 421         * First, disable windows.
 422         */
 423        win_enable = 0xffffffff;
 424        writel(win_enable, PCI_BAR_ENABLE);
 425
 426        /*
 427         * Setup windows for DDR banks.
 428         */
 429        bus = orion5x_pci_local_bus_nr();
 430
 431        for (i = 0; i < dram->num_cs; i++) {
 432                struct mbus_dram_window *cs = dram->cs + i;
 433                u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
 434                u32 reg;
 435                u32 val;
 436
 437                /*
 438                 * Write DRAM bank base address register.
 439                 */
 440                reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
 441                orion5x_pci_hw_rd_conf(bus, 0, func, reg, 4, &val);
 442                val = (cs->base & 0xfffff000) | (val & 0xfff);
 443                orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, val);
 444
 445                /*
 446                 * Write DRAM bank size register.
 447                 */
 448                reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
 449                orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
 450                writel((cs->size - 1) & 0xfffff000,
 451                        PCI_BAR_SIZE_DDR_CS(cs->cs_index));
 452                writel(cs->base & 0xfffff000,
 453                        PCI_BAR_REMAP_DDR_CS(cs->cs_index));
 454
 455                /*
 456                 * Enable decode window for this chip select.
 457                 */
 458                win_enable &= ~(1 << cs->cs_index);
 459        }
 460
 461        /*
 462         * Re-enable decode windows.
 463         */
 464        writel(win_enable, PCI_BAR_ENABLE);
 465
 466        /*
 467         * Disable automatic update of address remapping when writing to BARs.
 468         */
 469        orion5x_setbits(PCI_ADDR_DECODE_CTRL, 1);
 470}
 471
 472static int __init pci_setup(struct pci_sys_data *sys)
 473{
 474        struct resource *res;
 475
 476        /*
 477         * Point PCI unit MBUS decode windows to DRAM space.
 478         */
 479        orion5x_setup_pci_wins(&orion5x_mbus_dram_info);
 480
 481        /*
 482         * Master + Slave enable
 483         */
 484        orion5x_pci_master_slave_enable();
 485
 486        /*
 487         * Force ordering
 488         */
 489        orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
 490
 491        /*
 492         * Request resources
 493         */
 494        res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
 495        if (!res)
 496                panic("pci_setup unable to alloc resources");
 497
 498        /*
 499         * IORESOURCE_IO
 500         */
 501        res[0].name = "PCI I/O Space";
 502        res[0].flags = IORESOURCE_IO;
 503        res[0].start = ORION5X_PCI_IO_BUS_BASE;
 504        res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
 505        if (request_resource(&ioport_resource, &res[0]))
 506                panic("Request PCI IO resource failed\n");
 507        sys->resource[0] = &res[0];
 508
 509        /*
 510         * IORESOURCE_MEM
 511         */
 512        res[1].name = "PCI Memory Space";
 513        res[1].flags = IORESOURCE_MEM;
 514        res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
 515        res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
 516        if (request_resource(&iomem_resource, &res[1]))
 517                panic("Request PCI Memory resource failed\n");
 518        sys->resource[1] = &res[1];
 519
 520        sys->resource[2] = NULL;
 521        sys->io_offset = 0;
 522
 523        return 1;
 524}
 525
 526
 527/*****************************************************************************
 528 * General PCIe + PCI
 529 ****************************************************************************/
 530static void __devinit rc_pci_fixup(struct pci_dev *dev)
 531{
 532        /*
 533         * Prevent enumeration of root complex.
 534         */
 535        if (dev->bus->parent == NULL && dev->devfn == 0) {
 536                int i;
 537
 538                for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 539                        dev->resource[i].start = 0;
 540                        dev->resource[i].end   = 0;
 541                        dev->resource[i].flags = 0;
 542                }
 543        }
 544}
 545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
 546
 547static int orion5x_pci_disabled __initdata;
 548
 549void __init orion5x_pci_disable(void)
 550{
 551        orion5x_pci_disabled = 1;
 552}
 553
 554void __init orion5x_pci_set_cardbus_mode(void)
 555{
 556        orion5x_pci_cardbus_mode = 1;
 557}
 558
 559int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
 560{
 561        int ret = 0;
 562
 563        if (nr == 0) {
 564                orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
 565                ret = pcie_setup(sys);
 566        } else if (nr == 1 && !orion5x_pci_disabled) {
 567                orion5x_pci_set_bus_nr(sys->busnr);
 568                ret = pci_setup(sys);
 569        }
 570
 571        return ret;
 572}
 573
 574struct pci_bus __init *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys)
 575{
 576        struct pci_bus *bus;
 577
 578        if (nr == 0) {
 579                bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 580        } else if (nr == 1 && !orion5x_pci_disabled) {
 581                bus = pci_scan_bus(sys->busnr, &pci_ops, sys);
 582        } else {
 583                bus = NULL;
 584                BUG();
 585        }
 586
 587        return bus;
 588}
 589
 590int __init orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 591{
 592        int bus = dev->bus->number;
 593
 594        /*
 595         * PCIe endpoint?
 596         */
 597        if (orion5x_pci_disabled || bus < orion5x_pci_local_bus_nr())
 598                return IRQ_ORION5X_PCIE0_INT;
 599
 600        return -1;
 601}
 602