1/* linux/arch/arm/mach-s5pv210/include/mach/regs-clock.h 2 * 3 * Copyright (c) 2010 Samsung Electronics Co., Ltd. 4 * http://www.samsung.com/ 5 * 6 * S5PV210 - Clock register definitions 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11*/ 12 13#ifndef __ASM_ARCH_REGS_CLOCK_H 14#define __ASM_ARCH_REGS_CLOCK_H __FILE__ 15 16#include <mach/map.h> 17 18#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) 19 20#define S5P_APLL_LOCK S5P_CLKREG(0x00) 21#define S5P_MPLL_LOCK S5P_CLKREG(0x08) 22#define S5P_EPLL_LOCK S5P_CLKREG(0x10) 23#define S5P_VPLL_LOCK S5P_CLKREG(0x20) 24 25#define S5P_APLL_CON S5P_CLKREG(0x100) 26#define S5P_MPLL_CON S5P_CLKREG(0x108) 27#define S5P_EPLL_CON S5P_CLKREG(0x110) 28#define S5P_EPLL_CON1 S5P_CLKREG(0x114) 29#define S5P_VPLL_CON S5P_CLKREG(0x120) 30 31#define S5P_CLK_SRC0 S5P_CLKREG(0x200) 32#define S5P_CLK_SRC1 S5P_CLKREG(0x204) 33#define S5P_CLK_SRC2 S5P_CLKREG(0x208) 34#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) 35#define S5P_CLK_SRC4 S5P_CLKREG(0x210) 36#define S5P_CLK_SRC5 S5P_CLKREG(0x214) 37#define S5P_CLK_SRC6 S5P_CLKREG(0x218) 38 39#define S5P_CLK_SRC_MASK0 S5P_CLKREG(0x280) 40#define S5P_CLK_SRC_MASK1 S5P_CLKREG(0x284) 41 42#define S5P_CLK_DIV0 S5P_CLKREG(0x300) 43#define S5P_CLK_DIV1 S5P_CLKREG(0x304) 44#define S5P_CLK_DIV2 S5P_CLKREG(0x308) 45#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) 46#define S5P_CLK_DIV4 S5P_CLKREG(0x310) 47#define S5P_CLK_DIV5 S5P_CLKREG(0x314) 48#define S5P_CLK_DIV6 S5P_CLKREG(0x318) 49#define S5P_CLK_DIV7 S5P_CLKREG(0x31C) 50 51#define S5P_CLKGATE_MAIN0 S5P_CLKREG(0x400) 52#define S5P_CLKGATE_MAIN1 S5P_CLKREG(0x404) 53#define S5P_CLKGATE_MAIN2 S5P_CLKREG(0x408) 54 55#define S5P_CLKGATE_PERI0 S5P_CLKREG(0x420) 56#define S5P_CLKGATE_PERI1 S5P_CLKREG(0x424) 57 58#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x440) 59#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x444) 60#define S5P_CLKGATE_IP0 S5P_CLKREG(0x460) 61#define S5P_CLKGATE_IP1 S5P_CLKREG(0x464) 62#define S5P_CLKGATE_IP2 S5P_CLKREG(0x468) 63#define S5P_CLKGATE_IP3 S5P_CLKREG(0x46C) 64#define S5P_CLKGATE_IP4 S5P_CLKREG(0x470) 65 66#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x480) 67#define S5P_CLKGATE_BUS0 S5P_CLKREG(0x484) 68#define S5P_CLKGATE_BUS1 S5P_CLKREG(0x488) 69#define S5P_CLK_OUT S5P_CLKREG(0x500) 70 71/* DIV/MUX STATUS */ 72#define S5P_CLKDIV_STAT0 S5P_CLKREG(0x1000) 73#define S5P_CLKDIV_STAT1 S5P_CLKREG(0x1004) 74#define S5P_CLKMUX_STAT0 S5P_CLKREG(0x1100) 75#define S5P_CLKMUX_STAT1 S5P_CLKREG(0x1104) 76 77/* CLKSRC0 */ 78#define S5P_CLKSRC0_MUX200_SHIFT (16) 79#define S5P_CLKSRC0_MUX200_MASK (0x1 << S5P_CLKSRC0_MUX200_SHIFT) 80#define S5P_CLKSRC0_MUX166_MASK (0x1<<20) 81#define S5P_CLKSRC0_MUX133_MASK (0x1<<24) 82 83/* CLKSRC2 */ 84#define S5P_CLKSRC2_G3D_SHIFT (0) 85#define S5P_CLKSRC2_G3D_MASK (0x3 << S5P_CLKSRC2_G3D_SHIFT) 86#define S5P_CLKSRC2_MFC_SHIFT (4) 87#define S5P_CLKSRC2_MFC_MASK (0x3 << S5P_CLKSRC2_MFC_SHIFT) 88 89/* CLKSRC6*/ 90#define S5P_CLKSRC6_ONEDRAM_SHIFT (24) 91#define S5P_CLKSRC6_ONEDRAM_MASK (0x3 << S5P_CLKSRC6_ONEDRAM_SHIFT) 92 93/* CLKDIV0 */ 94#define S5P_CLKDIV0_APLL_SHIFT (0) 95#define S5P_CLKDIV0_APLL_MASK (0x7 << S5P_CLKDIV0_APLL_SHIFT) 96#define S5P_CLKDIV0_A2M_SHIFT (4) 97#define S5P_CLKDIV0_A2M_MASK (0x7 << S5P_CLKDIV0_A2M_SHIFT) 98#define S5P_CLKDIV0_HCLK200_SHIFT (8) 99#define S5P_CLKDIV0_HCLK200_MASK (0x7 << S5P_CLKDIV0_HCLK200_SHIFT) 100#define S5P_CLKDIV0_PCLK100_SHIFT (12) 101#define S5P_CLKDIV0_PCLK100_MASK (0x7 << S5P_CLKDIV0_PCLK100_SHIFT) 102#define S5P_CLKDIV0_HCLK166_SHIFT (16) 103#define S5P_CLKDIV0_HCLK166_MASK (0xF << S5P_CLKDIV0_HCLK166_SHIFT) 104#define S5P_CLKDIV0_PCLK83_SHIFT (20) 105#define S5P_CLKDIV0_PCLK83_MASK (0x7 << S5P_CLKDIV0_PCLK83_SHIFT) 106#define S5P_CLKDIV0_HCLK133_SHIFT (24) 107#define S5P_CLKDIV0_HCLK133_MASK (0xF << S5P_CLKDIV0_HCLK133_SHIFT) 108#define S5P_CLKDIV0_PCLK66_SHIFT (28) 109#define S5P_CLKDIV0_PCLK66_MASK (0x7 << S5P_CLKDIV0_PCLK66_SHIFT) 110 111/* CLKDIV2 */ 112#define S5P_CLKDIV2_G3D_SHIFT (0) 113#define S5P_CLKDIV2_G3D_MASK (0xF << S5P_CLKDIV2_G3D_SHIFT) 114#define S5P_CLKDIV2_MFC_SHIFT (4) 115#define S5P_CLKDIV2_MFC_MASK (0xF << S5P_CLKDIV2_MFC_SHIFT) 116 117/* CLKDIV6 */ 118#define S5P_CLKDIV6_ONEDRAM_SHIFT (28) 119#define S5P_CLKDIV6_ONEDRAM_MASK (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT) 120 121#define S5P_SWRESET S5P_CLKREG(0x2000) 122 123#define S5P_ARM_MCS_CON S5P_CLKREG(0x6100) 124 125/* Registers related to power management */ 126#define S5P_PWR_CFG S5P_CLKREG(0xC000) 127#define S5P_EINT_WAKEUP_MASK S5P_CLKREG(0xC004) 128#define S5P_WAKEUP_MASK S5P_CLKREG(0xC008) 129#define S5P_PWR_MODE S5P_CLKREG(0xC00C) 130#define S5P_NORMAL_CFG S5P_CLKREG(0xC010) 131#define S5P_IDLE_CFG S5P_CLKREG(0xC020) 132#define S5P_STOP_CFG S5P_CLKREG(0xC030) 133#define S5P_STOP_MEM_CFG S5P_CLKREG(0xC034) 134#define S5P_SLEEP_CFG S5P_CLKREG(0xC040) 135 136#define S5P_OSC_FREQ S5P_CLKREG(0xC100) 137#define S5P_OSC_STABLE S5P_CLKREG(0xC104) 138#define S5P_PWR_STABLE S5P_CLKREG(0xC108) 139#define S5P_MTC_STABLE S5P_CLKREG(0xC110) 140#define S5P_CLAMP_STABLE S5P_CLKREG(0xC114) 141 142#define S5P_WAKEUP_STAT S5P_CLKREG(0xC200) 143#define S5P_BLK_PWR_STAT S5P_CLKREG(0xC204) 144 145#define S5P_OTHERS S5P_CLKREG(0xE000) 146#define S5P_OM_STAT S5P_CLKREG(0xE100) 147#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C) 148#define S5P_DAC_CONTROL S5P_CLKREG(0xE810) 149 150#define S5P_INFORM0 S5P_CLKREG(0xF000) 151#define S5P_INFORM1 S5P_CLKREG(0xF004) 152#define S5P_INFORM2 S5P_CLKREG(0xF008) 153#define S5P_INFORM3 S5P_CLKREG(0xF00C) 154#define S5P_INFORM4 S5P_CLKREG(0xF010) 155#define S5P_INFORM5 S5P_CLKREG(0xF014) 156#define S5P_INFORM6 S5P_CLKREG(0xF018) 157#define S5P_INFORM7 S5P_CLKREG(0xF01C) 158 159#define S5P_RST_STAT S5P_CLKREG(0xA000) 160#define S5P_OSC_CON S5P_CLKREG(0x8000) 161#define S5P_MDNIE_SEL S5P_CLKREG(0x7008) 162#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200) 163#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204) 164#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814) 165 166#define S5P_IDLE_CFG_TL_MASK (3 << 30) 167#define S5P_IDLE_CFG_TM_MASK (3 << 28) 168#define S5P_IDLE_CFG_TL_ON (2 << 30) 169#define S5P_IDLE_CFG_TM_ON (2 << 28) 170#define S5P_IDLE_CFG_DIDLE (1 << 0) 171 172#define S5P_CFG_WFI_CLEAN (~(3 << 8)) 173#define S5P_CFG_WFI_IDLE (1 << 8) 174#define S5P_CFG_WFI_STOP (2 << 8) 175#define S5P_CFG_WFI_SLEEP (3 << 8) 176 177#define S5P_OTHER_SYS_INT 24 178#define S5P_OTHER_STA_TYPE 23 179#define S5P_OTHER_SYSC_INTOFF (1 << 0) 180#define STA_TYPE_EXPON 0 181#define STA_TYPE_SFR 1 182 183#define S5P_PWR_STA_EXP_SCALE 0 184#define S5P_PWR_STA_CNT 4 185 186#define S5P_PWR_STABLE_COUNT 85500 187 188#define S5P_SLEEP_CFG_OSC_EN (1 << 0) 189#define S5P_SLEEP_CFG_USBOSC_EN (1 << 1) 190 191/* OTHERS Resgister */ 192#define S5P_OTHERS_RET_IO (1 << 31) 193#define S5P_OTHERS_RET_CF (1 << 30) 194#define S5P_OTHERS_RET_MMC (1 << 29) 195#define S5P_OTHERS_RET_UART (1 << 28) 196#define S5P_OTHERS_USB_SIG_MASK (1 << 16) 197 198/* S5P_DAC_CONTROL */ 199#define S5P_DAC_ENABLE (1) 200#define S5P_DAC_DISABLE (0) 201 202#endif /* __ASM_ARCH_REGS_CLOCK_H */ 203