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22#include <linux/kernel.h>
23#include <linux/irq.h>
24#include <linux/pci.h>
25#include <linux/spinlock.h>
26
27#include <asm/mach/pci.h>
28#include <asm/mach-types.h>
29
30#include <mach/nanoengine.h>
31
32static DEFINE_SPINLOCK(nano_lock);
33
34static int nanoengine_get_pci_address(struct pci_bus *bus,
35 unsigned int devfn, int where, unsigned long *address)
36{
37 int ret = PCIBIOS_DEVICE_NOT_FOUND;
38 unsigned int busnr = bus->number;
39
40 *address = NANO_PCI_CONFIG_SPACE_VIRT +
41 ((bus->number << 16) | (devfn << 8) | (where & ~3));
42
43 ret = (busnr > 255 || devfn > 255 || where > 255) ?
44 PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
45
46 return ret;
47}
48
49static int nanoengine_read_config(struct pci_bus *bus, unsigned int devfn, int where,
50 int size, u32 *val)
51{
52 int ret;
53 unsigned long address;
54 unsigned long flags;
55 u32 v;
56
57
58
59
60 if (bus->number != 0 || (devfn >> 3) != 0) {
61 v = -1;
62 nanoengine_get_pci_address(bus, devfn, where, &address);
63 goto exit_function;
64 }
65
66 spin_lock_irqsave(&nano_lock, flags);
67
68 ret = nanoengine_get_pci_address(bus, devfn, where, &address);
69 if (ret != PCIBIOS_SUCCESSFUL)
70 return ret;
71 v = __raw_readl(address);
72
73 spin_unlock_irqrestore(&nano_lock, flags);
74
75 v >>= ((where & 3) * 8);
76 v &= (unsigned long)(-1) >> ((4 - size) * 8);
77
78exit_function:
79 *val = v;
80 return PCIBIOS_SUCCESSFUL;
81}
82
83static int nanoengine_write_config(struct pci_bus *bus, unsigned int devfn, int where,
84 int size, u32 val)
85{
86 int ret;
87 unsigned long address;
88 unsigned long flags;
89 unsigned shift;
90 u32 v;
91
92 shift = (where & 3) * 8;
93
94 spin_lock_irqsave(&nano_lock, flags);
95
96 ret = nanoengine_get_pci_address(bus, devfn, where, &address);
97 if (ret != PCIBIOS_SUCCESSFUL)
98 return ret;
99 v = __raw_readl(address);
100 switch (size) {
101 case 1:
102 v &= ~(0xFF << shift);
103 v |= val << shift;
104 break;
105 case 2:
106 v &= ~(0xFFFF << shift);
107 v |= val << shift;
108 break;
109 case 4:
110 v = val;
111 break;
112 }
113 __raw_writel(v, address);
114
115 spin_unlock_irqrestore(&nano_lock, flags);
116
117 return PCIBIOS_SUCCESSFUL;
118}
119
120static struct pci_ops pci_nano_ops = {
121 .read = nanoengine_read_config,
122 .write = nanoengine_write_config,
123};
124
125static int __init pci_nanoengine_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
126{
127 return NANOENGINE_IRQ_GPIO_PCI;
128}
129
130struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
131{
132 return pci_scan_bus(sys->busnr, &pci_nano_ops, sys);
133}
134
135static struct resource pci_io_ports = {
136 .name = "PCI IO",
137 .start = 0x400,
138 .end = 0x7FF,
139 .flags = IORESOURCE_IO,
140};
141
142static struct resource pci_non_prefetchable_memory = {
143 .name = "PCI non-prefetchable",
144 .start = NANO_PCI_MEM_RW_PHYS,
145
146
147 .end = NANO_PCI_MEM_RW_PHYS + NANO_PCI_MEM_RW_SIZE - 1,
148
149 .flags = IORESOURCE_MEM,
150};
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220static struct resource pci_prefetchable_memory = {
221 .name = "PCI prefetchable",
222 .start = 0x78000000,
223 .end = 0x78000000 + NANO_PCI_MEM_RW_SIZE - 1,
224 .flags = IORESOURCE_MEM | IORESOURCE_PREFETCH,
225};
226
227static int __init pci_nanoengine_setup_resources(struct resource **resource)
228{
229 if (request_resource(&ioport_resource, &pci_io_ports)) {
230 printk(KERN_ERR "PCI: unable to allocate io port region\n");
231 return -EBUSY;
232 }
233 if (request_resource(&iomem_resource, &pci_non_prefetchable_memory)) {
234 release_resource(&pci_io_ports);
235 printk(KERN_ERR "PCI: unable to allocate non prefetchable\n");
236 return -EBUSY;
237 }
238 if (request_resource(&iomem_resource, &pci_prefetchable_memory)) {
239 release_resource(&pci_io_ports);
240 release_resource(&pci_non_prefetchable_memory);
241 printk(KERN_ERR "PCI: unable to allocate prefetchable\n");
242 return -EBUSY;
243 }
244 resource[0] = &pci_io_ports;
245 resource[1] = &pci_non_prefetchable_memory;
246 resource[2] = &pci_prefetchable_memory;
247
248 return 1;
249}
250
251int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
252{
253 int ret = 0;
254
255 if (nr == 0) {
256 sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
257 sys->io_offset = 0x400;
258 ret = pci_nanoengine_setup_resources(sys->resource);
259
260
261
262 GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
263 GAFR |= GPIO_MBGNT | GPIO_MBREQ;
264 TUCR |= TUCR_MBGPIO;
265 }
266
267 return ret;
268}
269
270static struct hw_pci nanoengine_pci __initdata = {
271 .map_irq = pci_nanoengine_map_irq,
272 .nr_controllers = 1,
273 .scan = pci_nanoengine_scan_bus,
274 .setup = pci_nanoengine_setup,
275};
276
277static int __init nanoengine_pci_init(void)
278{
279 if (machine_is_nanoengine())
280 pci_common_init(&nanoengine_pci);
281 return 0;
282}
283
284subsys_initcall(nanoengine_pci_init);
285
